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4-3 PLL CIRCUITS

4-3-1 VCO CIRCUITS (MAIN UNIT)

A VCO (Voltage Controlled Oscillator) is an oscillator whose
oscillating frequency is controlled by adding voltage (lock
voltage).

This transceiver has 2 VCO’s; RX VCO (Q72, D51, D52) and
TX/CH70-RX VCO (Q4, Q5, D1, D3). The RX VCO oscillates
the 1st LO signals for voice communications channels
reception, and the TX/CH70-RX VCO oscillates the transmit
signal and the 1st LO signals for DSC channel reception.

4-3-1-1 RX VCO

The RX VCO (Q72, D51, D52) output signals are amplified by
the buffer amplifiers (Q74, Q76), and applied to the 1st mixer
(D32, L40, L41) via the LPF (L12, C78, C79), to be mixed with
the received signals to produce the 21.7 MHz 1st IF signal.

A portion of the VCO output is applied to the PLL IC (IC1, pin 2)
via the buffer amplifiers (Q74, Q75) and the BPF (L75, C624,
C625).

4-3-1-2 TX/CH70-RX VCO

The TX/CH70-RX VCO (Q4, Q5, D1, D3) output signals are
amplified by the buffer amplifiers (Q6, Q7),

• While receiving

The buffer-amplified TX/CH70-RX VCO output signals are
applied to the 1st mixer (D39, L55, L56) via the TX/RX switch
(D7 is OFF, D8 is ON) and the LPF (L65, C535, C537), to be
mixed with the received signals to produce the 31.05 MHz 1st
IF signal.

• While transmitting

The buffer-amplified TX/CH70-RX VCO output signals are
applied to the transmit amplifiers via the TX/RX switch (D7 is
ON, D8 is OFF).

A portion of the VCO output is applied to the PLL IC (IC1, pin 19)
via the buffer amplifiers (Q3, Q6) and the BPF (L2, C34, C35).

4-3-2 PLL CIRCUIT (MAIN UNIT)

The PLL circuit provides stable oscillation of the transmit and
receive 1st LO frequencies. The PLL output frequencies are
controlled by the divided ratio (N-data) from the CPU.

• RX VCO LOOP

The RX VCO output signals from the BPF (L75, C624, C625) are
applied to the PLL IC (IC1, pin 2). The applied signals are divided
at the prescaler and programmable counter according to the
“PDATA” signal from the CPU (LOGIC BOARD; IC1, pin 49). The
divided signal is phase-compared with the reference frequency
signal from the reference frequency oscillator (X1), at the phase
detector.

The phase difference is output from pin 8 as a pulse type
signal after being passed through the internal charge pump.
The output signal is converted into the DC voltage (lock
voltage) by passing through the loop filter (R602, R603, R606,
C602, C603, C606). The lock voltage is applied to the variable
capacitors (D51 and D52 of RX VCO) and locked to keep the
VCO frequency constant.

• TX/CH70-RX VCO LOOP

The output signal of TX/CH70-RX VCO from the BPF (L2, C34,
C35) are applied to the PLL IC (IC1, pin 2). The applied signals
are divided at the prescaler and programmable counter. The
divided signal is phase-compared with the reference frequency
signal from the reference frequency oscillator (X1), at the
phase detector.

The phase difference is output from pin 8 as a pulse type
signal. The output signal is converted into the DC voltage (lock
voltage) by passing through the loop filter (R7−R9, R41, C4,
C5, C43). The lock voltage is applied to the variable capacitors
(D53 of TX/CH70-RX VCO) and locked to keep the VCO
frequency constant.

If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the VCO oscillating frequency.

4 - 3

DATA interface

Prescaler

Phase

detector 2

Phase

detector 1

Loop

filter

Programmable

counter 2

Ref.