4 - 3
4-2-4 POWER AMPLIFIER CIRCUIT (MAIN-E UNIT)
The power amplifier circuit amplifies the driver signal to an
output power level.
IC3 is a power module which has amplification output capa-
bilities of about 35 W with 50 mW input. The output from IC3
(pin 4) is passed through the antenna switching circuit (D14)
and is then applied to the antenna connector via the low-
pass filter.
4-2-5 APC CIRCUIT (MAIN-E UNIT)
The APC circuit stabilizes transmit output power.
The RF output signal from the power amplifier (IC3; pin 4) is
detected at the power detector circuit (D12, D13, L19, C121,
C124) and is then applied to one of the differential amplifier
inputs (Q16, pin 5) via the High/Low control circuit (Q17,
R114). The applied voltage controls the differential amplifier
output (Q16, pin 2) and the bias voltage control (Q13). Thus
the APC circuit maintains a constant output power.
4-3 PLL CIRCUITS
4-3-1 GENERAL
The PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL circuit com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by a
crystal oscillator and the divided ratio of the programmable
divider.
IC1 on the MAIN-E unit is a dual PLL IC which controls both
VCO circuits for Tx and Rx, and contains a prescaler, pro-
grammable counter, programmable divider, phase detector,
charge pump, etc.
The PLL circuit, using a one chip PLL IC (MAIN-E unit; IC1),
directly generates the transmit frequency and receive 1st IF
frequency with VCOs. The PLL sets the divided ratio based
on serial data from the CPU on the LOGIC-E board and
compares the phases of VCO signals with the reference
oscillator frequency. The PLL IC detects the out-of-step
phase and output from pins 8 for Tx and Rx. The reference
frequency (21.25 MHz) is oscillated at X1 (MAIN-E unit).
T5
D12
D13
L19
"TMUT" signal from the CPU
(LOGIC-E board; IC1, pin 83)
Vcc
1
2
3
4
HI/LO
"TXDET" signal to the CPU
(LOGIC-E board; IC1, pin 92)
Q13
Q16
Q15
Q17
C137
C121
R112
R113
Q12
YGR
amp.
RF signal
from PLL
to antenna
RF detector
circuit
APC control circuit
Power module
IC3
R125
R116
R115
R114
C124
Shift register
Prescaler
Phase
detector
Loop
filter
Programmable
counter
Programmable
divider
X1
21.25 MHz
21.25 MHz signal to the
FM IF IC (IC2, pin 2)
VCO
Buffer
Buffer
Buffer
Q7
Q3
Q6
3
4
5
PSTB
IC1 (PLL IC)
PCK
PDATA
to transmitter circuit
to 1st mixer circuit
D7
D8
17
16
8
2
Q4, Q5, D3, D4
• APC CIRCUIT
• PLL CIRCUIT
