5 - 3
LO
SW
D25
Q13,D6
MODULATION
D26
BUFF
Q10
BUFF
Q11
TX VCO
From the TX AF circuits
To the TX AMP circuits
MOD
LPF
PWR
DET
D1,D11,D12
MUTE
SW
Q6
ANT
SW
D3,D5,D6,D68
PWR
AM P
IC3
APC
AMP
IC2
DRIVE
AMP
Q8
TMUT
ANT
From the TX VCO
To the RX circuits
LPF
LPF
LO
SW
D14,D15
Q24,D33
Q23,D16
FILTER
LOOP
PLL
IC
SO,SCL,PLST
IC3
X3
Q4
Q3
To the TX AMPs
BPF
BUFF
Q10
BUFF
Q11
BUFF
Q12
X2
TCXO
LV
ADJ
D64
LV
ADJ
D62
ATT
IF IC
RX VCO
TX VCO
IC4
VCON
15.3MHz
45.9MHz
1st IF mixer
LV
LVA
Transmit circuits
Receive circuits
TX/RX common circuits
VCOs and LO buffers
AF power AMP
Logic circuits
CPU
+3
REG
Q1017,Q1019
+8
REG
IC1002
+5
REG
Q1014,Q1015
+3
REG
IC1001
W2
SW
POWE R
Q 1003
Q1001
T8
REG
Q1013,Q1016
R8
REG
+3.3V
RXC
CPU3.3V
R8V
VCC
PWON
8V
8V
VCC
8V
VCC
8V
+5V
TXC
8V
T8V
HV
VCC
D1008,Q1011,
Q1018,Q1021
5-4 VOLTAGE DIAGRAMS
MODULATION CIRCUITS
The modulation signal from the TX AF circuits is applied to
D26 of the TX VCO (Q23, D16, D26, D64) to modulate it (FM
for the analog mode, 4FSK for the digital mode). The modu-
lated signal from the TX VCO is buffer-amplifi ed by two buf-
fers (Q11, Q10), and applied to the TX AMP circuits through
the LO SW (D25).
• MODULATION CIRCUIT
TX AMPLIFIER
The buffer amplified signal from the LO SW (D25) is se-
quentially amplifi ed by the pre-drive AMP (Q25), drive AMP
(Q8) and power AMP (IC3), to obtain TX power. The ampli-
fi ed TX signal is passed through the antenna SW (D5, D24)
and the LPFs, which eliminates harmonics, and then applied
to the antenna.
APC CIRCUIT
D11, D12 and D29 rectify a portion of the TX signal to direct
current, and the APC AMP (IC2) compares the voltage and
the TX power control reference voltage, “T1.” The resulting
voltage controls the gain of the power AMP (IC3) to keep the
TX power constant.
• TX AMPLIFIERS AND APC CIRCUIT
5-3 FREQUENCY SYNTHESIZER CIRCUIT
The RX VCO is composed of Q24, D33 and D62. The VCO
output signal is buffer-amplified by two buffers (Q11 and
Q10), and then applied to the 1st IF mixer, through the LO
SW (D15) and the attenuator.
The TX VCO is composed of Q23, D16, D26 and D64. The
VCO output signal is buffer-amplified by two buffers (Q11
and Q10), and then applied to the pre-drive AMP (Q25),
through the LO SW (D25) and the LPF.
A portion of signal generated by each VCO is fed back to the
PLL IC (IC8, pin 17), through the buffer (Q12) and the LPF
(L13, C298–C300).
The applied VCO output signal is divided and phase-com-
pared with a 15.3 MHz reference frequency signal from the
TCXO (X2), which is also divided. The resulting signal is
output from the PLL IC (IC3), and DC-converted by the loop
fi lter, and then applied to the VCO as the lock voltage.
When the oscillation frequency drifts, its phase changes
from that of the reference frequency, causing a lock voltage
change to compensate for the drift in the VCO oscillating fre-
quency.
• FREQUENCY SYNTHESIZER CIRCUIT
