Icom IC-F3, Service Manual

Page: 11 / 52

4 - 3
The signal output from the current sensor circuit (Q9, Q28;
IC-F3/S) or the power detector circuit (D2; IC-F4/S) is
applied to the differential amplifier (IC3a, pin 2), and the “T4”
signal from the expander (IC10, pin 14), controlled by the
CPU (IC8), is applied to the other input for reference.
When the driving current is increased, input voltage of the
differential amplifier (pin 2) will be increased. In such cases,
the differential amplifier output voltage (pin 1) is decreased
to reduce the driving current.
4-3 PLL CIRCUIT
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL output com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the VCO circuit (Q7, Q8). The oscil-
lated signal is amplified at the buffer-amplifiers (Q5, Q6) and
then applied to the PLL IC (IC1, pin 2).
The PLL IC contains a prescaler, programmable counter,
programmable divider, phase detector and charge pump,
etc. The entered signal is divided at the prescaler and pro-
grammable counter section by the N-data ratio from the
CPU. The divided signal is detected on phase at the phase
detector using the reference frequency.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
A portion of the VCO signal is amplified at the buffer-ampli-
fier (Q4) and is then applied to the receive 1st mixer or trans-
mit buffer-amplifier circuit via the T/R switching diode (D3,
D4).
4-4 POWER SUPPLY CIRCUITS
VOLTAGE LINE
• PLL circuit for IC-F3/S
Shift register
×
2
Prescaler
Phase
detector
Loop
filter
Programmable
counter
Programmable
divider
X1
15.3 MHz
30.6 MHz signal
to the FM IF IC
16
Q7, Q8
VCO circuit
Buffer
Q6 Buffer
Q4
Buffer
Q5
3
4
5
PLST
SCK
SO
to transmitter circuit
to 1st mixer circuit
D4
D3
17
8 2
Line
HV
VCC
CPU5
5V
T5
R5
S5
OPT
Description
The voltage from the attached battery pack.
The same voltage as the HV line (battery volt-
age) which is controlled by the power switch
([VOL] control).
Common 5 V converted from the VCC line by
the reference regulator circuit (IC6). The output
voltage is applied to the CPU (IC8) and the 5V
regulator circuit.
Common 5 V converted from the VCC line by
the 5 V regulator circuit (Q18, Q19) using the
reference regulator (IC6).
5 V for transmitter circuits regulated by the T5
regulator circuit (Q22).
5 V for receiver circuits regulated by the R5 reg-
ulator circuit (Q21).
Common 5 V converted from the 5V line by the
S5 regulator circuit (Q20).
The same voltage as the 5V line for the optional
HM-75A or HS-51 through a resistor (R132).