4 - 3
ALC5V
"VORDET" signal from
the AM detector (Q18)
IC12
IC11
IC13
IC14
3
5
5
1
1
14
8
2
2
10 kHz
30 kHz
BPF
BPF
BIAS
Buff.
Limit.
FM
DET
7
7
7
3
Phase
shift
LPF
3
6
Comp.
Comp.
"VORS" signal to the
CPU (IC1, pin 2)
"VORC" signal to the
CPU (IC1, pin 3)
"VORD" signal to the
CPU (IC1, pin 28)
Amp.
To IC2, pin 6
R102
D18
R99
R100
Q21
C115
R101
AM AF signal
from Q18
"ANLC" signal
from IC5, pin 7
• ANL CIRCUIT
• VOR NAVIGATION CIRCUIT
4-1-8 ANL CIRCUIT (RF UNIT)
The ANL (Automatic Noise Limiter) circuit (Q21, D18)
reduces noise components.
The AM detector output signal from the Q18 is applied to
the cathode of D18 passing through R99 where it is divided
by R99 and R100. The signal is also applied to the anode of
D18, passing through R101 and R102.
When the ANL function is activated (Q21 is ON), C115 is
grounded. The detector output, including noise components,
are applied to the cathode of D18 only. If noise components
are received, the cathode voltage of D18 becomes higher
than the anode voltage and D18 turns OFF. Thus, while
noise components are received, the detected signal is not
applied to IC2.
4-1-9 VOR NAVIGATION CIRCUIT (LOGIC UNIT)
(IC-A24/E ONLY)
From the AF signal, the VOR circuit detects a variable signal
(VORC) and reference signal (VORS) from a VOR station.
The VOR circuit sends these signals to the CPU (IC1).
When the transceiver is set in the navigation band (108.000
–117.975 MHz), the VORON port of the CPU (IC1, pin 118)
becomes “HIGH” turning the VOR circuit ON via Q15. Q15
controls a 5 V power source for the VOR circuit.
The signal from the AM detector (VORDET) is buffer ampli-
fied at the OP-AMP IC (IC12).
The “VORDET” signal includes 30 Hz variable phase com-
ponents and 9960 Hz reference phase components.
The 30 Hz component passes through the 30 Hz bandpass
filter (IC12, R83–R88, C112, C113), and is converted to
a square-wave signal at the VORS comparator (IC14).
The square-wave signal is then applied to the CPU (IC1,
pin 2) as variable signal (VORS).
The 9960 Hz component passes through the 10 kHz
bandpass filter (IC12, R79–R82, C108, C109). These com-
ponents are FM modulated with 480 Hz deviation and 30 Hz
modulation.
Signals are then amplified at a limiter amplifier (IC11), and
detected at an FM detector (IC11) to obtain a 30 Hz refer-
ence signal.
The 30 Hz signal is compensated on phase at IC12. This
signal is passed through the 30 Hz low-pass filter (IC12)
and is converted to a square-wave signal at the VORC com-
parator (IC14). This signal is applied to the CPU (IC1, pin 3)
as a reference signal (VORC).
A portion of output from the buffer amplifier (IC12) is applied
to the amplifier (Q13). When VOR level is low or receiving
the signal except VOR signal, output from IC12 is reduced.
Output signal from Q13 is applied to the CPU (IC1, pin 28)
as a “OFF FLAG” signal (VORD).
