3-5
3-3 MAIN UNIT (continued)
• FPGA
FPGA (Field-Programmable Gate Array) is a device that can
digitally confi gure the virtual circuit in the chip.
The program that determines how it operates is written in the
external EEPROM, and loaded when the transceiver power is
turned ON. So the circuit can be reconfi gured, even after the
device is mounted on the PCB, by reprogramming it.
Using mathematical functions, the FPGA (IC1351) performs
down conversion and fi ltering by controlling digital bits.
The received signal from the RF UNIT has been converted into
a digital data stream by the A/D converter. The converted data
is applied to the FPGA as a bit stream with the sampled signal
spectrum, and then processed by manipulating the digital bits.
The FPGA processes the signal mathematically to digitally ob-
tain the oscillation and mixing (Image rejection mixer), as if
the signal is processed in a hardware down conversion circuit.
The processed signal is applied to the DSP (IC901).
• Demodulator and D/A converter
The 36 kHz IF signal is digitally demodulated and processed
by the DSP (IC901), whose design is based totally on that of
the IC-7100. The internal AGC control, demodulation, noise
reduction (NB, NR and Notch fi lter) and squelch functions are
also the same as those of the IC-7100.
The demodulated and processed signal from the DSP (IC901)
is applied to the D/A converter (IC991) to be converted into
an analog AF signal. The AF signal is then applied to the AF
circuit.
• AF circuit
The AF signal is amplifi ed by the AF AMP (IC992), and then
by the D-class AF power AMP (IC721) to obtain up to 2.5
watts (at 8 ohms, 1 kHz, 10% distortion) of output power. The
amplifi ed signal is applied to the speaker through the LPF
(L731, L732 and C731 ~ C735), which attenuates unwanted
frequency components, and to the speaker SW (Q746).
When an external speaker is connected to the [EXT-SP] jack,
the audio output from the internal speaker (SP1) is discon-
nected.
A/D
D/A
D/A
ATT
90
Phase
shift
90
Phase
shift
BPF
BPF
DET
BPF
AGC
DET
IF
AMP
LO (DDS)
36 kHz
Image
Rejection
Mixer
36 kHz
FPGA (IC1351)
DSP (IC901)
Mixer
SP
• FPGA BLOCK DIAGRAM (Receive circuits)
