4 - 4
4-2-5 VHF APC CIRCUIT
The APC circuit protects the power amplifier from a mis-
matched output load and stabilizes transmit output power.
The APC detector circuit (L12, D7, D8) detects forward sig-
nals and refrection signals at D7 and D8 respectively. The
combined voltage is at a minimum level when the antenna
impedance is matched at 50
Ω
and is increased when it is
mismatched.
The detected voltage is applied to the APC amplifier (IC5, pin
3) and compared with a reference voltage which is supplied
from the CPU (IC19, pin 68–pin 75) as a D/A control signal.
When antenna impedance is mismatched, the detected volt-
age exceeds the reference voltage. The output voltage of the
APC amplifier (IC5, pin 4) controls the bias voltage of the
power module (IC1) and drive amplifeir (Q12) to reduce the
output power via the APC controller (Q30, Q31).
4-2-6 UHF MODULATION CIRCUIT
Audio signals from the splatter filter (IC23a) pass through the
frequency deviation control (R78), and are then applied to
the modulation circuit (D20) to change the reactance of D20
and modulate the oscillated signal at the U-VCO circuit (Q20,
Q21). The VCO output is amplified at the buffer amplifiers
(Q22, Q24), and is then applied to the T/R switching circuit
(D23) via the low-pass filter (L33, C153, C154).
4-2-7 UHF DRIVE AMPLIFIER CIRCUIT
The VCO signals from the T/R switch (D23) are amplified at
the buffer-amplifier (Q27), pre-drive amplifier (Q28) and drive
(Q29, D24) amplifier to obtain an approximate 400 mW sig-
nal level. The amplified signal is then applied to the RF power
amplifier (IC4).
4-2-8 UHF POWER AMPLIFIER CIRCUIT
IC4 is a power module which has amplification output capa-
bilities of about 50 W.
The RF signal from the drive amplifier (Q29) is applied to IC4
(pin 5). The amplified signal from the power amplifier (IC4,
pin 1) is passed through the antenna switching circuit (D27)
and is then applied to the antenna connector via a bandpass
filter (L42–L45, L82, C186–C190, C467, C493).
4-2-9 UHF APC CIRCUIT
The APC detector circuit (D25 and D26) detects forward sig-
nals and refrection signals respectively. The combined volt-
age is at a minimum level when the antenna is matched at 50
Ω
and increases when it is mismatched.
The combined voltage is applied to the APC amplifier (IC5,
pin 3), and the power setting voltage from the CPU (IC19, pin
68–pin 75) as a D/A control signal is applied to the other input
(IC5, pin 1) for the reference.
The output voltage from IC5 (pin 4) is applied to the APC
control circuit (Q30, Q31) to control the bias voltage of the PA
module (IC4) and drive amplifier (Q29).
4-3 PLL CIRCUITS
4-3-1 GENERAL
A PLL circuit provides stable oscillation of the transmit fre-
quency and the receive local frequency. The PLL circuit com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by a
crystal oscillator and the divided ratio of the programmable
divider. IC2 is a dual PLL IC which controls both VCO circuits
for VHF and UHF.
4-3-2 VHF LOOP
The generated signal at the V-VCO (Q4, Q5, D3) enters the
PLL IC (IC2, pin 6) via buffer-amplifiers (Q6, Q8) and is divid-
ed at the programmable divider section and is then applied to
the phase detector section.
The phase detector compares the input signal with a refer-
ence frequency, and then outputs the out-of-phase signal
(pulse-type signal) from pin 8.
The pulse-type signal is converted into DC voltage (lock volt-
age) at the loop filter (Q99, Q100, R531, C476–C478), and
then applied to the V-VCO to stabilize the oscillated frequen-
cy.
• VHF APC circuit
D7
D8
L12
HV
VTX
APC
Q30
APC control
Q32
Q31
D9
Power
module
Drive
APC amplifier
to antenna
antenna
switch
APC
detector
POWC
Q12
Q11
IC1
IC5
Pre-drive
RF signal
from PLL circuit
