IBM ThinkVision L170, Service Manual

Page: 22 / 54

IBM L170 Service Manual
22
+PV
GPIO5/UART_DO
DVI_PLUG
R201
4.7K 1/16W
R241 NC
HOST_PROTOCOL
RMADDR0
RED- P.2
ER2
RMADDR0
GND
A3.3V
GPIO6
R235
0 1/16W
C253
0.1uF/16V
RMDATA3
C207
0.1uF/16V
R202
0 1/16W
GND
+PV
PBIAS P.5
SCL
RMDATA5
RMADDR2
RMDATA7
SCLPOL
ROM_ADDR13
SPEC(60mA)
GPIO3 P.5
OB3
SCL
+
C222
47uF/16V
DIGITAL PORT
PPWR P.5
OB5
ROM_ADDR8
gm5120 A
gm5120
AOC
C
3 6 Friday, October 25, 2002
Title
Size Document Number Rev
Date: Sheet of
A2.5V
GPIO5/UART_DO
RMADDR3
RMADDR10
R249 0 1/16W
A2.5V
DVI_PLUG P.2
C213
0.1uF/16V
D3.3V
RMADDR14
RMDATA4
BLUE- P.2
BLUE+ P.2
DDC_SCL_A P.2
OB4
Int_Test
U203
PQFP208
GM5120
171
170
167
166
163
162
179
180
185
186
191
192
151
152
40
41
42
43
44
45
46
47
49
50
51
52
118
115
117
116
195
194
174
120
121
122
123
124
125
126
127
128
206
207
208
1
205
204
5
4
6
7
48
39
201
25
24
23
22
19
18
17
16
15
8
35
34
33
32
31
30
29
28
9
10
14
12
13
11
36
155 153
165
169
161
158
157
178
2 20 53 67 81 97 111 129 26 88 134 203 176
113
114
175
182
184
188
190
197
198
199
150
149
148 146 144 141 139
145
140
137
136
3 21 38 54 68 82 98 112 130 89 133 202 135 156 154 177 183 189 147 143 138
200
159
61
62
65
66
69
70
71
72
94
93
75
76
77
78
79
80
74
73
85
86
87
90
91
92
84
83
95
96
99
100
101
102
64
63
105
106
107
108
109
110
104
103
119
27
131
142
132
60
59
58
57
56
55
37 160 164 168 172 173 181 187 193 196
RED+
RED-
GREEN+
GREEN-
BLUE+
BLUE-
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
XTAL
TCLK
GPIO0/PWM0
GPIO1/PWM1
GPIO2/PWM2
GPIO3/TIMER1
GPIO4/UART_D1
GPIO5/UART_D0
GPIO6/EXTCLK
GPIO7
GPIO10/TCON_ROE3
GPIO11
GPIO12
GPIO13
DCLK/TCON_OCLK
DEN/TCON_ECLK
DVS/TCON_FSYNC
DHS/TCON_LP
RXC-
RXC+
REXT
TCON_OPOL
TCON_OINV
TCON_ESP
TCON_EPOL
TCON_EINV
TCON_RSP2
TCON_RSP3
TCON_RCLK
TCON_ROE
GPIO20/HDATA3
GPIO19/HDATA2
GPIO18/HDATA1
GPIO17/HDATA0
GPIO16/HFS
GPIO22/HCLK
RESETn
GPIO21/IRQn
DDC_SCL
DDC_SDA
GPIO9/TCON_ROE2
GPIO8/IRQINn
CLKOUT
ROM_ADDR0
ROM_ADDR1
ROM_ADDR2
ROM_ADDR3
ROM_ADDR4
ROM_ADDR5
ROM_ADDR6
ROM_ADDR7
ROM_ADDR8
ROM_ADDR15
ROM_DATA0
ROM_DATA1
ROM_DATA2
ROM_DATA3
ROM_DATA4
ROM_DATA5
ROM_DATA6
ROM_DATA7
ROM_ADDR14
ROM_ADDR13
ROM_ADDR9
ROM_ADDR11
ROM_ADDR10
ROM_ADDR12
ROM_OEn
VD
D1_A
DC
_2.
5
VD
D2_A
DC
_2.
5
AGND_GREEN
AGND_RED
AGND_BLUE
AGND_ADC
SGND_ADC
AGND_RX2
RVDD RVDD RVDD RVDD RVDD RVDD RVDD RVDD
CVDD_
2.
5
CVDD_
2.
5
CVDD_
2.
5
CVDD_
2.
5
VD
D_
RX
2_2.
5
PPWR
PBIAS
AGND_IMB
VD
D_
RX
1_2.
5
AGND_RX1
VD
D_
RX
0_2.
5
AGND_RX0
AGND_RXC
AGND_RXPLL
VDD_RXPLL_2.5
AVDD_
RPL
L
AVSS_RPLL
VD
D_
DP
LL_3.
3
AVDD_
SDDS
VDD_
SDDS_
3.
3
AVDD_
DDDS
VDD_
DDDS_
3.
3
AVSS_SDDS
AVSS_DDDS
HSYNC
VSYNC
RVSS RVSS RVSS RVSS RVSS RVSS RVSS RVSS RVSS CVSS CVSS CVSS CVSS GND1
_A
DC
GND2
_A
DC
GND_
RX2
GND_
RX1
GND_
RX0
VSS_
DPL
L
VSS_
SDDS
VSS_
DDDS
N/C
ADC_TEST
PD6/ER6
PD7/ER7
PD10/EG2
PD11/EG3
PD12/EG4
PD13/EG5
PD14/EG6
PD15/EG7
PD33/OG1
PD32/OG0
PD18/EB2
PD19/EB3
PD20/EB4
PD21/EB5
PD22/EB6
PD23/EB7
PD17/EB1
PD16/EB0
PD26/OR2
PD27/OR3
PD28/OR4
PD29/OR5
PD30/OR6
PD31/OR7
PD25/OR1
PD24/OR0
PD34/OG2
PD35/OG3
PD36/OG4
PD37/OG5
PD38/OG6
PD39/OG7
PD9/EG1
PD8/EG0
PD42/OB2
PD43/OB3
PD44/OB4
PD45/OB5
PD46/OB6
PD47/OB7
PD41/OB1
PD40/OB0
TCON_OSP
CVSS
Reserved
N/C
Reserved
PD5/ER5
PD4/ER4
PD3/ER3
PD2/ER2
PD1/ER1
PD0/ER0
RVDD
AVDD_
ADC
AVDD_
BL
UE
AVDD_
GREEN
AVDD_
RED
AVDD_
IM
B
AVDD_
RX2
AVDD_
RX1
AVDD_
RX0
AVDD_
RXC
ROM_ADDR(12:10)
Close to respective power Pins
BANK0
RMADDR14
HS P.2
DDC_SDA P.2
OG7
R234
10K
1/
16W
C216
0.1uF/16V
DESCRIPTION
+3.3V
ROM_OEn
RMADDR11
C201
0.1uF/16V
R208
10K 1/16W
VS P.2
+2.5V
OR2
RED+ P.2
RMADDR12
GPIO7
OG6
C258
0.01uF
RMADDR12
EB6
C251
0.1uF/16V
ROM_ADDR9
RS232
+PV
R237
10K
1/
16W
VOL
GPIO4/UART_DI
RMADDR5
FB207
600OHM
NAME
Reserved
GND
+
C245
10uF/16V
OB[0..7] P.5
DDC_SCL P.2
DDC_SDA_A P.2
/ROM_WE
RMADDR10
R244 0 1/16W
FB204
600OHM
SPEC(50mA)
DVS P.5
GPIO2 P.5
EG[0..7] P.5
EB[0..7] P.5
R233
10K
1/
16W
FB208
600OHM
ROM_ADDR7
Available for reading from a status register
D3.3V
GPIO7 P.5
ER1
RMADDR13
RMADDR14
C240
0.1uF/16V
ROM_ADDR6
ER7
OR5
RMDATA1
R221
10K 1/16W
R223
10K 1/16W
R247
4.7K 1/16W
32-Pin PLCC Socket
C215
0.1uF/16V
C256
0.01uF
NC Analog
GND
RMADDR2
OB1
U204
M24C16-MN6T
1
2
3
4
5
6
7
8
A0
A1
A2
VSS SI
SCK
WP
VCC
LED_GRN
P.5
RMADDR15
1 GPIO(22:16) is on "Host Port" pins
GND
+PV
GREEN- P.2
VGA_PG P.2
C206
0.1uF/16V
R231 NC
EB2
ROM_ADDR5
GPIO6 P.5
VGA_PLUG
SOT-23
+T3.3V
DEN P.5
ER0
RMDATA0
C249
0.1uF/16V
C234
0.1uF/16V
LED_ORANGE
P.5
RMADDR13
ER5
R248 0 1/16W
(use 0 or 2 level smith trigger)
GND
GND
OG3
RMADDR2
/ROM_WE
C202
0.1uF/16V
10/24
GND
GND
/ROM_WE
C244
0.1uF/16V
Available for reading from a status register
GREEN+ P.2
OG[0..7] P.5
C242
0.1uF/16V
C204
0.1uF/16V
R210
0
1/
16W
10/17
GND
+5V
GND
DISP_CLK P.5
OG0
RMADDR4
RX0- P.2
BANK0
C209
0.1uF/16V
CN202
NC
1
2
3
4
+5V
TXD
RXD
GND
C248
0.1uF/16V
MUTE
DHS P.5
EG3
TEST PAD
GND
D2.5V
RXC+ P.2
R215
10K
1/
16W
LVDS_EN P.5
RMADDR9
EG6
D3.3V
+PV
/ROM_WE
OB7
RMADDR5
OSC_SEL
x
1 = All 48K of ROM is in external ROM
GPIO4/UART_DI
OR4
ER6
EG4
+ C250
22uF/16V
C259
22pF(NC)
R227
0 1/16W
10/17
UART_DI P.2
C220
0.1uF/16V
C252
0.01uF
R209
4.7K (NC)
+5V
RMADDR7
C231
0.1uF/16V
FB202
600OHM
R238 NC
C247
5pF
A3.3V
+5V
RX1+ P.2
RX2+ P.2
DVS
(use 1 level smith trigger)
RMADDR4
EG0
EG2
C246
5pF
ADDRESS
RXC- P.2
C212
0.1uF/16V
+
C211
100uF/16V
1 = OCM becomes active after OCM_CLK is stable
0
1
STDBY
FUNCTION1 P.5
ER4
RMDATA6
C238
0.1uF/16V
GND
RMDATA4
+5V
PWM0 P.4
EG1
C226
0.1uF/16V
R206
10K
1/
16W
R236
NC
C214
0.1uF/16V
+3.3V
RMADDR1
R204 2.7K 1/16W
R240 47 1/16W
10/17
D2.5V
10K input H/V Reversed
R213
0 1/16W
0 = XTAL and TCLK pins are connected
x
0
EB0
R232 NC
R245 4.7K 1/16W
GND
RMADDR6
C254
0.01uF
U201
MCP809(NC)
3
2
1
VCC
RSTN
GND
+T3.3V
OR6
OR3
NC S/W Power Key
ER3
RMADDR7
USER_BITS(4:0)
RMDATA0
R205
1K 1/16W
If using 6-wire host protocol, program this bit to 1
1
GND
OR1
EB4
RMADDR11
RMADDR1
C210
0.1uF/16V
Close to respective power Pins
A2.5V
EB5
RMDATA3
C233
0.1uF/16V
R218 1K 1/16W
C205
0.1uF/16V
10/17
DEN
RMADDR15
EG5
+2.5V
EG7
R246
4.7K 1/16W
C227
0.1uF/16V
USER_BITS(7:5)
x
+PV
RMADDR1
RMADDR10
RMADDR12
R203 22 (NC)
OB2
R212
NC
SPEC(500mA)
RX1- P.2
EB3
C219
0.1uF/16V
10/17
GND
RMADDR9
C208
0.1uF/16V
R224
4.7K 1/16W
FB210
0 1/16W
BOOTSTRAP SIGNALS
C228
0.1uF/16V
R237---10K DUAL
GND
FB206
600OHM
SDA
+
C230
47uF/16V
R222
10K 1/16W
OCM_START
x
RMADDR3
SDA
RMDATA1
R219 0 1/16W
OB0
Close to respective power Pins
UART_DO P.2
10/17
GND
GND
OB6
OR7
RMADDR4
ROM_ADDR(4:0)
+5V
OR[0..7] P.5
WP
C241
0.1uF/16V
C257
0.1uF/16V
U202
W39F010P
3
29
28
4
25
23
26
27
5
6
7
8
9
10
11
12
21
20
19
18
17
15
14
13
24
31
32
1
16
2
30
22
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
OE
WE
VCC
NC
GND
A16
NC/A17
CE
RMADDR3
R239 NC
C260
NC
SET
RMDATA2
RMDATA5
OG5
XTAL
+
C221
47uF/16V
C239
0.1uF/16V
D3.3V
RMADDR9
EB1
GPIO3
R207
10K
1/
16W
SPEC(150mA)
DHS
C217
0.1uF/16V
R242 0 1/16W
R234---NC input H/V not Reversed
D3.3V
D3.3V
RMADDR11
RX0+ P.2
OR0
GND
GPIO8 P.5
RMDATA2
C203
0.1uF/16V
Determines polarity of HCLK signal
OCM_ROM_CFG(1)
OG4
A3.3V
RX2- P.2
R214
10K
1/
16W
C232
0.1uF/16V
HOST_PORT_EN
Close to respective power Pins
OG2
R243 0 1/16W
R233---10K H/W Power Key
D2.5V
RMDATA7
C255
0.1uF/16V
C218
0.1uF/16V
D201
LL4148
RMADDR8
WP
ER[0..7]
P.5
GPIO0/PWM0
OG1
RMADDR8
FLASH/ Prom-Jet Socket
A3.3V
GND
RMDATA6
RMADDR8
RMADDR0
If using 6-wire host protocol, program this bit to 0
ROM_ADDR14
EB7
RMADDR6
X201
14.318MHz
1
2