IBM RT Hardware Reference Manual Download

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Summary of Contents for RT

Page 1: ......

Page 2: ..._ IBMRTPC Hardware Technical Reference Volume III Personal Computer Hardware Reference Library...

Page 3: ...nd either express or implied including but not limited to the implied warranties of merchantability and fitness for a particular purpose IBM may make improvements and or changes in the product s and o...

Page 4: ...ion of the IBM RT PC Product Family How to Use This Book This manual is modular in format with each module providing information about a specific option or adapter available for the IBM RT PC family o...

Page 5: ...iv Reference Manual...

Page 6: ...DISPLAYS DISPLAY ADAPTERS MEMORY EXPANSION MULTI PURPOSE ADAPTERS...

Page 7: ..._ IBM Advanced Color Graphics Display Personal Computer Hardware Reference Library...

Page 8: ...ii Advanced Color Graphics Display...

Page 9: ...Contents Description 1 Operating Characteristics 1 Connector Specifications 3 Contents iii...

Page 10: ...iv Advanced Color Graphics Display...

Page 11: ...de ray tube CRT The CRT and associated analog circuits of the display are packaged in an enclosure that allows the display to sit either on top of the mM 6151 on a nearby tabletop or desk with the IBM...

Page 12: ...llator Normally low positive going TTL pulse Nominal vertical frequency of 92 Hz Nominal frame rate of 46 Hz Retrace blanking time of 527 0 usec Operator Control Size Brightness control adjusts bright...

Page 13: ...round for vertical sync Vertical sync R1 signal ground Low order red bit R1 R2 signal ground High order red bit R2 G 1 signal ground Low order green bit G1 G2 signal ground High order green bit G2 B1...

Page 14: ...4 Advanced Color Graphics Display...

Page 15: ..._ Advanced Monochrome Graphics Display Personal Computer Hardware Reference Library...

Page 16: ...ii Advanced Monochrome Graphics Display...

Page 17: ...Contents Description 1 Operating Characteristics 1 Connector Specifications 3 Contents iii...

Page 18: ...iv Advanced Monochrome Graphics Display...

Page 19: ...ay operates on 120 vac 60 Hz power line voltage The display uses a 12 inch diagonal high contrast monochrome CRT The CRT and associated analog circuits of the display are packaged in an enclosure that...

Page 20: ...y of 92 Hz Nominal frame rate of 46 Hz Operator Control Size Brightness control adjusts brightness of displayed image Clockwise rotation of control increases brightness Raster switch diagnostic aid pr...

Page 21: ...nction 1 Signal ground for vertical sync 2 Vertical sync 3 Signal ground 4 Reserved 5 Signal ground 6 Reserved 7 Signal ground for video 8 Video 9 Signal ground 10 Reserved 11 Signal ground 12 Reserve...

Page 22: ...4 Advanced Monochrome Graphics Display...

Page 23: ..._ Enhanced Color Display Personal Computer Hardware Reference Library...

Page 24: ...ii...

Page 25: ...Contents Description 1 Operating Characteristics 2 Specifications 5 Connector Information 6 iii...

Page 26: ...iv...

Page 27: ...rd wall outlet The display has its own power control and indicator Three models are provided Model 001 is for northern hemisphere operation and operates on 120 volts 50 60 Hz Model 002 is for northern...

Page 28: ...ered inoperative and contrast is determined by the setting of the contrast default value adjustment on the rear of the display Pulling the contrast control knob out engages the front contrast control...

Page 29: ...ode 2 is selected by a normally high negative going TTL pulse Screen may be refreshed from 50 to 60 Hz At 60 Hz there are either 200 or 350 vertical lines of resolution depending on the mode selected...

Page 30: ...0 Red 1 0 00 00 0 1 0 1 Magenta 1 0 00 1 0 0 1 1 0 Brown 1 0 01 00 0 1 1 1 Grav 1 1 0 1 0 1 0 1 0 0 0 Grav 2 01 01 01 1 0 0 1 Light Blue 01 01 1 1 1 0 1 0 Light Green 01 1 1 01 1 0 1 1 Light Cvan 01 1...

Page 31: ...s Size Length 15 4 in 392 mm Depth 15 6 in 407 mm Height 11 7 in 297 mm Weight 321bs Heat Output 300 BTU hr Power Cable Length 6 ft 1 83 m Size 18 AWG Signal Cable Length 3 5 ft 1 07 m IBM Enhanced Co...

Page 32: ...xpected to be TTL levels supplied by totem pole drivers Pin Mode 1 16 Color Mode 2 64 Color 1 Shield Gnd Ground 2 Signal Gnd r 3 Red R 4 Green G 5 Blue B 6 Intensity a 7 Unused b 8 Horiz SYnc Horiz Sy...

Page 33: ..._ Extended Monochrome Graphics Display Personal Computer Hardware Reference Library...

Page 34: ...TNL SN20 9844 March 1987 to 75X0235 ii Extended Monochrome Graphics Display...

Page 35: ...TNL SN20 9844 March 1987 to 75X0235 Contents Description 1 Operating Characteristics 1 Connector Characteristics 4 Contents iii...

Page 36: ...TNL SN20 9844 March 1987 to 75X0235 iv Extended Monochrome Graphics Display...

Page 37: ...s a 15 inch diagonal high contrast monochrome cathode ray tube CRT The CRT and associated analog circuits of the display are packaged in an enclosure that allows the display to sit either on top of th...

Page 38: ...ve Free running vertical oscillator Normally high negative going TTL pulse Nominal vertical frequency of 60 Hz Retrace blanking time of 505 0 usec Operator Control Brightness control adjusts the overa...

Page 39: ...1987 to 75X0235 Size Width 372 mm 14 6 in Depth 400 mm 17 7 in Height 360 mm 14 2 in Weight 13 75 Kg 30 25 pounds Power Cable Length 2 8 m 9 19 t Signal Cable Length 2 5 m 8 2 ft Extended Monochrome...

Page 40: ...Pin Function 1 Gnd Vertical sync 2 Vertical sync 3 Fteserved 4 Fteserved 5 Gnd Video 6 Video 7 Gnd Video 8 Video 9 Gnd Video 10 Video 11 Gnd Video 12 Video 13 Gnd Video 14 Video 15 Gnd Horizontal syn...

Page 41: ..._ Monochrome Display Personal Computer Hardware Reference Library...

Page 42: ...ii...

Page 43: ...Contents Description 1 Specifications 3 Logic Diagrams 5 iii...

Page 44: ...iv...

Page 45: ...e placed on the system unit or on a nearby table or desk Brightness and contrast controls are on the front surface and are easily accessible to the operator The characteristics of the display are as f...

Page 46: ...2 Monochrome Display...

Page 47: ...ength Depth Weight Heat Output Power Cable Length Size Signal Cable Length Size Physical Specifications 280 mm 11 in 380 mm 14 9 in 350 mm 3 7 in 7 9 kg 17 3Ib 325 BTU hr 0 914 m 3 ft 18AWG 1 22 m 4 f...

Page 48: ...4 Monochrome Display...

Page 49: ...Logic Diagrams The IBM Monochrome Display has two models a 110 Vac model and a 220 240 Vac model A logic diagram for each follows Monochrome Display S...

Page 50: ...S500K R506 lOOK II2W w f fmJ IOV r D IBIIllI3 Ipm 12 1m ro R rn IIW IO rn 19 II KO r 050 I 5W B30 I I TOAII70 I ROIBEB3 I m il B t _ r _ _ _ _ _ _ i _ I b f8 I IJ I 12 IIlIII IUZI 10 m m I C 09 I 1 r...

Page 51: ..._ _ _ ___ E I 1 i 11 ICL _ l HB r C401 0022 VERT 9 0401 IS2413 C410 100 0402 2SV GIB 0403 GIB l W fllTIl 22 I OV l501 SSOOK Dg II m 2W RS04 C 2 S 210 B 3 S 2 fl3p rn 410 r ill 9 IC40lToA1110 111 J i 3...

Page 52: ...8 Monochrome Display...

Page 53: ..._ IBM 5080 Peripheral Adapter rersonat compurer Hardware Reference Library...

Page 54: ...ii 5080 Peripheral Adapter...

Page 55: ...Adapter Switch Settings 3 Modes of Operation 5 Interrupts 8 Serial Data Format 9 External Interface Description 10 Asynchronous Communications Element Pin Description 12 Programming Considerations 18...

Page 56: ...iv 5080 Peripheral Adapter...

Page 57: ...ive 6 7 or 8 bit characters with 1 1 1 2 or 2 stop bits are supported A priority interrupt system controls transmit receive error line status and data set interrupts Three 10 pin male connectors on th...

Page 58: ...16450 DRVRS r RCVRS Data 0 7 Address 0 15 Addr 16450 DRVRS Decode RCVRS r Clock __ Int Req 9 Int __ Int Req 10 CnU __ Int Req 11 Reset 16450 DRVRS RCVRS Figure 1 mM 5080 Peripheral Adapter Block Diag...

Page 59: ...d the address range of adapters installed 12345678 Switch Bank One Switch Bank Two Figure 2 mM 5080 Peripheral Adapter Switches Interrupt Switch Bank One Setting Level Selected Switch 1 Switch 2 Switc...

Page 60: ...dapters Switch 1 Switch 2 Switch 3 Switch 4 1230 1247 On Off Off Off 2230 2247 Off On Off Off 3230 3247 Off Off On Off 4230 4247 Off Off Off On Figure 4 Switch Bank Two Settings Note Switches 5 throug...

Page 61: ...variable determined by the setting of switch bank two Switches 1 2 3 and 4 of switch bank two allow the card to operate and select the appropriate address range 110 Decode In Hex PortH PortA Register...

Page 62: ...MSB DLAB l n241 Interrupt Enable Register DLAB O n242 Interrupt Identification Register n243 Line Control Register n244 Modem Control Register n245 Line Status Register n246 Modem Status Register Fig...

Page 63: ...Divisor Latch LSB 0 0 1 1 Divisor Latch MSB Figure 7 Address Bits Notes 1 Bits A9 through A3 are used to select specific adapter an serial port 2 A2 AI and AO bits are don t cares and are used to sele...

Page 64: ...e first digit of address range is provided to store pending port interrupts Interrupt register bit assignment as shown in Figure 8 Hex Address n237 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 1 1 0 1 0 Figure 8 Int...

Page 65: ...Parity Stop Marking Bit Bit Bit Data bit 0 is the first bit to be transmitted or received The adapter automatically inserts the start bit the correct parity bit if programmed to do so and the stop bit...

Page 66: ...o determine the state of the interface or peripheral device The drivers and receivers used on the adapter are the inverting type therefore a 0 EIA level on the line is received or transmitted as a 0 T...

Page 67: ...when the voltage is more positive than 3 Vdc with respect to signal ground and is off when the voltage is more negative than 3 Vdc with respect to signal ground Interface Interchange Binary Signal Con...

Page 68: ...rmation or data from a selected register of the NS16450 Note Only an active DISTR or DISTR input is required to transfer data from the NS16450 during a read operation Therefore tie either the DISTR in...

Page 69: ...ransmitter Holding Register Write 0 0 0 1 Interrupt Enable x 0 1 0 Interrupt Identification Read Only x 0 1 1 Line Control x 1 0 0 Modem Control x 1 0 1 Line Status x 1 1 0 Modem Status x 1 1 1 Scratc...

Page 70: ...Reset All Bits Low Register Line Status Register Master Reset All Bits Low except Bits 5 and 6 are High Modem Status Master Reset Bits 0 3 are Low Register Bits 4 7 Input Signal SOUT Master Reset Hig...

Page 71: ...ng of the modem status register Note This pin is permanently tied low Received Line Signal Detect RLSD Pin 38 The RLSD signal is a modem control function input whose condition the processor can test b...

Page 72: ...programming bit 3 OUT 2 of the modem control register to a high level The OUT 2 signal is set high by a master reset operation The OUT 2 signal is set high during the loop mode operation Note No conn...

Page 73: ...to the marking logic 1 state on a master reset operation Note Provides data to attached device Input Output Signals Data Bus 07 00 Pins 1 8 This bus consists of eight tri state I O lines The bus prov...

Page 74: ...hange through the line control register In addition to controlling the format the programmer may retrieve the contents of the line control register for inspection This feature simplifies system progra...

Page 75: ...This bit is the even parity select bit When bit 3 is a logical 1 and bit 4 is a logical 0 an odd number of logical 1 is transmitted or checked in the data word bits and parity bit When bit 3 is a logi...

Page 76: ...s transferred into the receiver buffer register and thereby destroyed the previous character The OE indicator is reset whenever the processor reads the contents of the line status register Bit 2 This...

Page 77: ...reset to alogical 0 whenever either the THR or TSR contain a data character Bit 6 is a read only bit Bit 7 This bit is permanently set to logical O Interrupt Identification Register The NS16450 has an...

Page 78: ...whether an interrupt is pending When bit 0 is a logical 0 an interrupt is pending and the IIR contents may be used as a pointer to the appropriate interrupt service routine When bit 0 is a logical 1...

Page 79: ...or Break Intrpt 1 0 0 Second Received Receiver Data Reading the Receiver Data Available Buffer Register Available 0 1 0 Third Transmitter Transmitter Holding Reading the IIR Holding Register Empty Reg...

Page 80: ...ding the setting of the line status and modem status registers The contents of the interrupt enable register are described below Bit 0 Bit 1 Bit 2 Bit 3 Bits 4 7 Interrupt Enable Register DLAB 0 Hex A...

Page 81: ...output Bit 1 affects the RTS output in a manner identical to that described above for bit O Note The RTS output of the NS16450 may be applied to an EIA inverting line driver to obtain the proper pola...

Page 82: ...perational The modem control interrupts are also operational but the sources of the interrupts are now the lower 4 bits of the modem control register instead of the 4 modem control inputs The interrup...

Page 83: ...ve line signal detect Bit 0 This bit is the delta clear to send DCTS indicator Bit 0 indicates that the CTS input to the chip has changed state since the last time it was read by the processor Bit 1 T...

Page 84: ...ical l this bit is equivalent to OUT 1 in the MCR Bit 7 This bit is the complement of the received line signal detect RLSD input If bit 4 loop of the MCR is set to a logicall this bit is equivalent to...

Page 85: ...erator The NS16450 contains a programmable baud rate generator that can divide the clock input 1 8 432 MHz by any divisor from 1 to 655 535 or 216_1 The output frequency of the baud rate generator is...

Page 86: ...or Latch Least Significant Byte Divisor Latch Most Significant Byte Hex Address n231 n239 n241 Bit 7 6 5 4 3 2 1 0 LS Data bit 8 Databit9 Data bit 10 L _ _ _ _ _ _ Data bit 11 L _ _ _ _ _ _ _ Data bit...

Page 87: ...ata rate should never be greater than 19 200 baud Desired Divisor Used to Generate Percent Error Baud 16x Clock Difference Between Rate Decimal Hex Desired and Actual 50 2304 900 75 1536 600 110 1047...

Page 88: ...dapter The following figure shows the signals and their pin assignments Transmit Data 1 12 2 5 3 Not Used 4 12 5 External 5080 Device Receive Data 6 Peripheral Adapter Not Used 7 Not Used 8 Not Used 9...

Page 89: ..._ Advanced Color Graphics Display Adapter Personal Computer Hardware Reference Library...

Page 90: ...ii Advanced Color Graphics Display Adapter...

Page 91: ...Contents Description 1 Operation 3 Bit Map Memory Operations 5 110 Operations 6 Connector Specifications 12 Contents iii...

Page 92: ...iv Advanced Color Graphics Display Adapter...

Page 93: ...o rotate bits within a byte and a logic unit to combine source bytes before they are written into the bit map In addition a plane select register and foreground or background register are provided as...

Page 94: ...ADDRESS 20 BUS FG BG PLNSEL STATUS SYS DATA 16 BUS CNTL A LOGIC UNIT 4 1 DECODES 3 2 0 64KX8 MEMORY 8X4 Figure 1 Advanced Color Graphics Display Adapter Functional Block Diagram 2 Advanced Color Graph...

Page 95: ...rol registers See the section entitled I O Operations on page 6 for specific register addresses and bit assignments The second address range occupied by the adapter is the bit map memory that consists...

Page 96: ...annel address denoted as C in the equations is shown as folluws for each of the increase and decrease bits and the X and Y status bits Word Storage Location I O Channel Inc Dec X V Physical to I O Cha...

Page 97: ...e mask controls the write to the bit map This operation will not affect the contents of the system data latches Preloading the system data latches with the proper constant makes it possible to AND or...

Page 98: ...the data path but is used only to update D1 D2 and D3 This allows the fast Store operation to be used for block transfer operations with no Loads required To get the alternate read write operations i...

Page 99: ...the bit map or written from the system are merged before being written into the bit map When set to 101 B the bit fields masked off by the data mask register are merged with system data before being w...

Page 100: ...y location accessed is stored in a pointer register on the card This address is adjusted to point at the next memory location at the end of each memory cycle That is the X or Y address is increased or...

Page 101: ...round bit data 1 or into the background bit data 0 This allows all selected planes to be updated simultaneously with the selected foreground and background colors Reserved Foreground Background Regist...

Page 102: ...intense R2 Bit 10 Green Gl Bit 11 Green intense G2 Bit 12 Blue Bl Bit 13 Blue intense B2 Bits 14 15 Reserved Video Look up Table Register X 0158 Write Only The video look up table is selected via the...

Page 103: ...s I O location loads the address of the next memory access into the on card address pointer register No significant data is returned when this location is read See Data Control Register X 0150 Write O...

Page 104: ...gnal ground 8 Low order green bit G1 Advanced Advanced Color Color Graphics Display 9 G2 signal ground Graphics Displ Adapter 10 High order green bit G2 11 B1 signal ground 12 Low order blue bit B 1 1...

Page 105: ..._ Advanced Monochrome Graphics Display Adapter Personal Computer Hardware Reference Library...

Page 106: ...ii Advanced Monochrome Graphics Display Adapter...

Page 107: ...Contents Description 1 Operation 3 Bit Map Memory Operations 5 110 Operations 6 Specifications 10 Logic Diagrams 12 Contents iii...

Page 108: ...iv Advanced Monochrome Graphics Display Adapter...

Page 109: ...e screen as 720 pels horizontally by 512 pels vertically one bit per pel The adapter includes a number of hardware performance assists including a write mask to protect bit fields within a byte a barr...

Page 110: ...SYNCS SYS ADDRESS 24 t BUS STATUS SYS DATA BUS 64KX8 ADR DO I r 01 CONTROL MEMORY LOGIC UNIT Figure 1 Advanced Monochrome Graphics Display Adapter Functional Block Diagram 2 Advanced Monochrome Graphi...

Page 111: ...egisters See the section entitled I O Operations on page 6 for specific register addresses and bit assignments The second address range occupied by the adapter is the bit map memory that consists of 1...

Page 112: ...dress denoted as C in the equations shown as follows for each of the increase and decrease bits and the X and Y status bits Word Storage Location I O Channel Inc Dec X V Physical to I O Channel to Phy...

Page 113: ...s it possible to AND or OR system data with the bit map memory in one memory operation Adapter Write Operation Mode 10 This operation writes data from the on card data latches D1 D2 D3 to the bit map...

Page 114: ...ous registers on the adapter a set of I O operations are required Data Mask Register X 0162 Typically these two 8 bit registers DMI and DM2 are initialized with data representing the inverse of each o...

Page 115: ...mask register 1 DMl is written into the bit map memory This is the function normally needed in system write and overlay write modes When set to OOO B the bit field masked off by data mask register 2 D...

Page 116: ...e memory address supplied on the data bus is ignored and the pointer is used to access memory To reload the pointer register either clear and set the block transfer bit again or read from the block tr...

Page 117: ...information regarding the use of this I O command Interrupts The adapter generates a level 11 interrupt at the start of vertical sync if bit 13 interrupt enable of the control register is a 1 This in...

Page 118: ...Specifications The adapter has a 16 pin connector at the rear of the adapter The following figure shows the signals and their pin assignments 10 Advanced Monochrome Graphics Display Adapter...

Page 119: ...8 Graphics Display GNO S Reserved 10 _ Busy GNO 11 _ PE Reserved 12 _ GNO 13 Reserved 14 GNO 15 Horizontal Sync 16 Figure 3 Advanced Monochrome Graphics Display Adapter Interface Specifications Advan...

Page 120: ...SCLK 5 t r t o B03 t f 1 B29 DI6 lCl 13Cl lC2 62C2 01 F BOI BID 831 01B liD SLOT A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A2B A29 A30 A31 CO2 C03 C04 C05 C07 C06 COB B2B B14 B13 C09 Cl0 All B02...

Page 121: ...3 13 16 BAOORID SHT 1 SAODRQ 17 5 SHT3 13 16 BAODRQ SHT 1 SADDR8 3 SHT 3 13 16 BAODRB 2 74lS244 SHT 1 SADDRI5 lr i4 j 1 21 8_________________ SHT 3 13 BAOORI5 SHT 1 SAOOR14 6 UQ4 16 SHT 3 13 BADDRI4 S...

Page 122: ...3 I g SHT 12 MCLK 7 r S H T 16 IORW AEN 8HT 15 IOR AEN 74LS04 SHT 1 SAEN I U40 SHT 2 800R15 SHT 2 BADDR5 l I SHT 2 BADDR8 I SHT 2 BADDR6 4 _ SHT 2 BAOORI4 lJ SHT 2 BADDRI3 iJ SHT 2 BADDRI2 2 l SHT 2 B...

Page 123: ...HT81 CLK15 I 5C i RP 4 6 c d ISHT 81 SRESET1 jf t ISHT 91 CLK 16 1 WJJ O ISHT 5_ 61 MEMCYCLE h ISHT 51 LATCH CLK2 ISHT 61 SET LATCH CLK L ISHT81 CLK 16 1 74S08 ISHT 61 LATCH CLK I ISHT 13_ 151 LATCH C...

Page 124: ...SHT 21 DMEMR 1 i SHT 21 DMEMW _t_ i 74F74 U55 74ALS08 74ALS08 74FOO 5 5 RP5 RP5 10 1 11 SHT 151 MlIMO t H t I 74F04 74LSOO 74LSOO 12 l U57 J I_ t_ SHT 131 DMEMR o l _l_ _l_l_ _ __ _ _ SHT 13 151 DMEMW...

Page 125: ...F00 lJ 1 2 U66 3 74S51 i l l 131 I I I I 8 I 9 U91 8 I I I 10 I 191 I 1 1 L U89 J 74LSOO 5 6 74lS20 4 U45 9 lOl 12 U38 131 74LS04 1 U40 2 9 74LS20 8 13 U44 J 10 4 74LS20 f tIl U44 6 I 6 74F00 2 3 8 RP...

Page 126: ...TAO I j15 RP4 f RP4 B U5B SHTB CLK12 13 r 1 SHT 9 670WE 12 Ull l 9 P SHT 16 VIDEOEN SHT 8 CLK8 10 SHT 14 FDATA3 2 9 U12 SHT 14 FDATA2 1 7 6 rt1 SHT 14 FDATAI 7 PIt __ 6 _ 4 L r Jt 13 74S195 14 SHT 14...

Page 127: ...9 CLK6 F t__ _t_ t__ _ SHT 6 7 9 11 CLK7 tl 12 n m i i _ _ r1 u F04 2 L_ _ l_3_U_ 4_7F_04_12 __ _11_U_ _FO 4 10 SHT6 9 CLK5 V I t__ SHT6 7 10 CLK6 SHT 6 CLK7 9 74F194 SHT7 9 CLK8 10 _ SHT 7 9 10 CLKI2...

Page 128: ...6 RAS li__________ SHT 6 SET CAS SHT B ClK8 SHT 8 ClK12 74F04 h 1 U57 SHT7 670WAI 1 1 1 TIII U89 I 1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1 SHT 8 ClK4 74F20 U SHT 14 lATCHClKl 74FOO _______L ______________ SH...

Page 129: ...4LS08 I SHT II HC4 74LS74 SHT II HEN U27 74LSI0 I SHT 13 HC2 SHT II 13 HCO SHTII VS _____________ ______ ______1____ 74AS808B SHT II VSOUT SHT 131 HCI SHT 16 SYNCEN lH t JJ 74LSOB SHT I HSOUT SHT 8 CL...

Page 130: ...8 O B 1 r 1 t t 1 7418163 r 74W i t i t I 18HT 13 VCI 18HTB 8RE8ETl J l J J9 U35 B 74l811 74l810 18HTI3 VC2 4 1 4 H l I l lJ3 U36 1 6 t I f t j U26 6 14 13 r 1 2 ttjjt j l f 18HT13 VC4 Hf d9 11 18HT 1...

Page 131: ...28 5 29 6 30 7 31 8 32 9 33 17 34 18 35 19 36 20 37 U30 21 38 22 39 23 40 24 41 36 42 37 43 38 44 39 45 46 47 48 15 L 74LS04 3 U63 4 SHT 15 BDATA7 SHT 16 BDATA6 SHT 15 BDATA5 SHT 16 BDATA4 SHT 15 BDAT...

Page 132: ...HT 11 VCO _ t t t I SO f 7 12 h ISHT 11 VC4 f I l l ISHT 14 MAODR4 ISHT 11 VCl 11 9 ISHT 14 MADDRS ISHT 11 VCS 14 2 L J 11 6 r ti 7 ISHT 2 BADDR8 t 1f I U75 3 H hl 4 ISHT 2 8AODR9 10 4 k j 3 ISHT 2 8A...

Page 133: ...1 MDATAI5 Zl 0 5 3 RP2 p 0 SHT 15 161 WE4 8HT 121 MDATAI4 0 1 5 iJ 21 3 115 49 1310 1112 6 7 5 14 23 15 4 9 13 RP2 1 U8 N I 2600 12 2600 12 2600 12 U18 U7 139 4153 2 14 57 612 1110 139 4 15 3 2 14 I I...

Page 134: ...U79 5 3 9 13 74lS08 9 8 10 I U53 74S11 13 74S11 3 6 74lS00 9 8 10 U65 1 74lS374 11 5 13 6 14 9 17 12 18 U31 15 4 16 b 19 2 J 5 18 4 17 16 9 15 U92 8 14 7 13 6 12 11 SHT 14 16J WEO SHT 14 16J WEI SHT...

Page 135: ...Tl tt ili f 11 7 4L S 27 3 r ti rt 15 l r 1 SHT 31 CNTLCLK3 5 RP6 5 8 4 7 08 6 8 S 10 t1 2 1 it U88 6 SHT 111 VS j U34 74LS04 74LSDO p B ___ 1 13 U63 1 2 2c jl U65 ___Ll7 5 SHT6 151 MD 8 U32 6 SHT 6 1...

Page 136: ...28 Advanced Monochrome Graphics Display Adapter...

Page 137: ...Enhanced Graphics Adapter Personal Computer Hardware Reference Library...

Page 138: ...ii...

Page 139: ...2 Character Set 70 Creating an 80 by 43 Alphanumeric Mode 71 Vertical Interrupt Feature 72 Creating a Split Screen 73 Compatibility Issues 74 Interface 76 Feature Connector 76 Specifications 79 System...

Page 140: ...Notes iv...

Page 141: ...with resolution of 640x350 for the IBM Enhanced Color Display In alphanumeric modes characters are formed from one of two ROM Read Only Memory character generators on the adapter One character generat...

Page 142: ...ctor provides an interface for graphics memory expansion The following is a block diagram of the Enhanced Graphics Adapter CPU Addr CPU Data J rl v 4 r CRTC LSI 4 r 0 r SEQ LSI I MUX GRAPH LSI GRAPH L...

Page 143: ...cs Controller The Graphics Controller directs the data from the memory to the attribute controller and the processor In graphics modes memory data is sent in serialized form to the attribute chip In a...

Page 144: ...emory Module Kit adds two additional 16K banks to each bit plane bringing the graphics memory to its maximum of 256K bytes The address of the display buffer can be changed to remain compatible with ot...

Page 145: ...6 40x25 88000 8x8 8 320x200 2 A N 16 80x25 88000 8x8 8 640x200 3 A N 16 80x25 88000 8x8 8 640x200 4 APA 4 40x25 88000 8x8 1 320x200 5 APA 4 40x25 88000 8x8 1 320x200 6 APA 2 80x25 88000 8x8 1 640x200...

Page 146: ...IBM Enhanced Color Display Parameter TV Frequency High Resolution Horiz Scan Rate 15 75 KHz 21 85 KHz Vertical Scan Rate 60 Hz 60 Hz Video Bandwidth 14 318 MHz 16 257 MHz Displayable Colors 16 Maximu...

Page 147: ...d Color Display ALPHA BUFFER BOX MAX MODE TYPE COLORS FORMAT START SIZE PAGES RESOLUTION 0 A N 16 64 40x25 88000 8x14 8 320x350 1 A N 16 64 40x25 88000 8x14 8 320x350 2 A N 16 64 80x25 88000 8x14 8 64...

Page 148: ...ata in bit plane 1 The programmer can view bit planes 0 and 1 as a single buffer in alphanumeric modes The CRTC generates sequential addresses and fetches one character code byte and one attribute byt...

Page 149: ...els are given in the following table The video bit plane is denoted by CO and the Intensity Bit Plane is denoted by C2 C2 co Pixel Color Valid Attributes 0 0 Black 0 0 1 Video 3 1 0 Blinking Video C 1...

Page 150: ...llowing table I R G B Color 0 0 0 0 Black 0 0 0 1 Blue 0 0 1 0 Green 0 0 1 1 Cyan 0 1 0 0 Red 0 1 0 1 Magenta 0 1 1 0 Brown 0 1 1 1 White 1 0 0 0 Dark Gray 1 0 0 1 Light Blue 1 0 1 0 Light Green 1 0 1...

Page 151: ...available Character Mode 10H Mode 10H Attribute Monochrome 64KB 64KB OOH Black Black Black 01H Video Blue Blue 02H Black Black Green 03H Video Blue Cyan 04H Blinking Red Red OSH Intensified White Mage...

Page 152: ...port address is hex 3C2 A hardware reset causes all bits to reset to zero Miscellaneous Output Register Format Bit 7 6 5 4 3 2 1 0 Bit 0 I O Address Select Enable Ram Clock Select 0 J Clock Select 1 D...

Page 153: ...al clock source from the feature connector 1 1 Not used Disable Internal Video Drivers A logical 0 activates internal video drivers a logical 1 disables internal video drivers When the internal video...

Page 154: ...ter Format Bit 7 6 5 4 3 2 1 0 Bits 0 and 1 Feature Control Bit 0 Feature Control Bit 1 Reserved Not Used Feature Control Bits These bits are used to convey information to the feature connector The ou...

Page 155: ...termined by reading byte 40 88H in RAM Bit 3 Switch 4 Logical 0 switch closed Bit 2 Switch 3 Logical 0 switch closed Bit 1 Switch 2 Logical 0 switch closed Bit 0 Switch 1 Logical 0 switch closed Featu...

Page 156: ...litches in the display image Light Pen Strobe A logical 0 indicates that the light pen trigger has not been set a logical 1 indicates that the light pen trigger has been set Light Pen Switch A logical...

Page 157: ...register controls the multiplexer for the video wiring The following table illustrates the combinations available and the color output wiring Input Status Register One BitS Bit4 Red Blue Secondary Bl...

Page 158: ...value that points to the sequencer data register where data is to be written This value is referred to as Index in the table above Sequencer Address Register Format Bit 7 6 5 4 3 2 1 0 Bit O Bit 3 Re...

Page 159: ...ss in the dynamic RAMs Synchronous Reset A logical 0 commands the sequencer to synchronous clear and halt Bits 1 and 0 must both be ones to allow the sequencer to operate Reset the sequencer with this...

Page 160: ...ovide the CRTC with 4 out of 5 memory cycles in order to refresh the display image Shift Load When set to 0 the video serializers are reloaded every character clock when set to 1 the video serializers...

Page 161: ...uces the overhead on the CPU during display update cycles in graphics modes Data scrolling operations are also enhanced by setting this register to a value of OFH and writing the display buffer addres...

Page 162: ...a 1 according to the following table Map Selected Table Location 0 1st 8K of Plane 2 Bank 0 1 2nd 8K of Plane 2 Bank 1 2 3rd 8K of Plane 2 Bank 2 3 4th 8K of Plane 2 Bank 3 In alphanumeric modes bit 3...

Page 163: ...l 0 indicates that a non alpha mode is active A logical 1 indicates that alpha mode is active and enables the character generator map select function Extended Memory A logical 0 indicates that the mem...

Page 164: ...10 Vertical Retrace End 3 5 11 Light Pen Low 3 5 11 Vertical Display End 3 5 12 Offset 3 5 13 Underline Location 3 5 14 Start Vertical Blank 3 5 15 End Vertical Blank 3 5 16 Mode Control 3 5 17 Line C...

Page 165: ...5 4 3 2 1 0 I J1L L 1 L 1 I 1 L 1 I Horizontal Total This register defines the total number of characters in the horizontal scan interval including the retrace time The value directly controls the pe...

Page 166: ...nking Register This is a write only register pointed to when the value in the CRT Controller address register is hex 02 The processor output port address for this register is hex 3B5 or hex 3D5 Start...

Page 167: ...decode outputs are multiplexed on the memory address outputs and the cursor outputs respectively during the blanking interval These outputs are latched external to the CRT Controller with the falling...

Page 168: ...d vertical retrace signals The bit values and amount of skew are shown in the following table Bits 6 5 o 0 Zero character clock skew o lOne character clock skew 1 0 Two character clock skew 1 1 Three...

Page 169: ...4 Bit 5 Bit 6 End Horizontal Retrace A value equal to the five least significant bits of the horizontal character counter value at which time the horizontal retrace signal becomes inactive logical 0 T...

Page 170: ...RT Controller address register is hex 06 The processor output port address for this register is hex 3B5 or 3D5 Vertical Total Register Format Bit 7 6 5 4 3 2 1 0 I I I I I I I I Vertical Total Bit O B...

Page 171: ...ical Display Enable End register index hex 12 Vertical Retrace Start Bit 8 of the Vertical Retrace Start register index hex 10 Start Vertical Blank Bit 8 of the Start Vertical Blank register index hex...

Page 172: ...imum Scan Line Register This is a write only register pointed to when the value in the CRT Controller address register is hex 09 The processor output port address for this register is hex 3B5 or hex 3...

Page 173: ...rsor row scan Cursor End R gister This is a write only register pointed to when the value in the CRT Controller address register is hex OB The processor output port address for this register is hex 3B...

Page 174: ...I I I I I High Order Start Address Bit O Bit 7 Start Address High These are the high order eight bits of the start address The 16 bit value from the high order and low order start address registers is...

Page 175: ...it O Bit 7 I I I I I I High Order Cursor Location Cursor Location High These are the high order 8 bits of the cursor location Cursor Location Low Register This is a read write register pointed to when...

Page 176: ...8 is in the overflow register location hex 07 Light Pen High Register This is a read only register pointed to when the value in the CRT Controller address register is hex 10 The processor input port a...

Page 177: ...To obtain a vertical retrace signal of width W the following algorithm is used Value of Start Vertical Retrace Register width of vertical retrace signal in horizontal scan units 4 bit result to be pr...

Page 178: ...ster is hex 3B5 or hex 3D5 Vertical Display Enable End Register Format Bit 7 6 5 4 3 2 1 0 I I I I I I I Low Order Vertical Display Enable End Bit O Bit 7 Vertical Display Enable End These are the low...

Page 179: ...r This is a write only register pointed to when the value in the CRT Controller address register is hex 14 The processor output port address for this register is hex 3B5 or hex 3D5 Underline Location...

Page 180: ...is hex 16 The processor output port address for this register is hex 3B5 or hex 3D5 End Vertical Blanking Register Format Bit 7 6 5 4 3 2 1 0 I I I Bit O Bit 4 I I I I End Vertical Blanking Not Used E...

Page 181: ...s bit 13 during active display time A logical 1 enables memory address bit 13 to appear on the memory address output bit 13 signal of the CRT Controller The CRT Controller used on the IBM Color Graphi...

Page 182: ...ided by 2 Count By Two When this bit is set to 0 the memory address counter is clocked with the character clock input A logical 1 clocks the memory address counter with the character clock input divid...

Page 183: ...iplexer Byte Address Word Address Mode Mode MAO MA 15 or MA 13 MA1 MAO MA2 MA1 MA3 MA2 MA14 MA13 MA15 MA14 Hardware Reset A logical 0 forces horizontal and vertical retrace to clear A logical 1 forces...

Page 184: ...s this value the internal start of the line counter is cleared This allows an area of the screen to be immune to scrolling Bit 8 of this register is in the overflow register hex 07 44 IBM Enhanced Gra...

Page 185: ...hics 1 Position Register This is a write only register The processor output port address for this register is hex 3CC Graphics I Position Register Format Bit 7 6 5 4 3 2 1 0 IIIIIII Position 0 Positio...

Page 186: ...ssor data bus to which each chip responds Graphics 2 must be programmed with a position register value of 1 for this card Graphics 1 and 2 Address Register This is a write only register and the proces...

Page 187: ...Used Set Reset These bits represent the value written to the respective memory planes when the processor does a memory write with write mode 0 selected and set reset mode is enabled Set Reset can be...

Page 188: ...s written with the value of the processor data Color Compare Register This is a write only register pointed to by the value in the Graphics 1 and 2 address register This value must be hex 02 before wr...

Page 189: ...ster is hex 3CF Data Rotate Register Format Bit 7 6 5 4 3 2 1 0 Bit O Bit 2 Bit 3 Bit 4 Rotate Count Rotate Count 1 Rotate Count 2 Function Select Not Used Rotate Count These bits represent a binary e...

Page 190: ...er This value must be hex 04 before writing can take place The processor output port address for this register is hex 3CF Read Map Select Register Format Bit 7 6 5 4 3 2 1 0 Bit O Bit 2 Mode Register...

Page 191: ...ed for the plane Planes for which Set Reset is enabled are written with 8 bits of the value contained in the Set Reset register for that plane o 1 Each memory plane is written with the contents of the...

Page 192: ...llows the value of the Memory Mode Register bit 3 of the Sequencer Shift Register A logical 1 directs the shift registers on each graphics chip to format the serial data stream with even numbered bits...

Page 193: ...emory Map These bits control the mapping of the regenerative buffer into the processor address space Bits 3 2 o 0 Hex AOOO for 128K bytes o 1 Hex AOOO for 64K bytes 1 0 Hex BOOO for 32K bytes 1 1 Hex...

Page 194: ...is set to 1 Color Don t Care Color plane 2 don t care when reading color compare when this bit is set to 1 Color Don t Care Color plane 3 don t care when reading color compare when this bit is set to...

Page 195: ...eded writes to the corresponding bits in the bit planes The bit mask applies to any data written by the processor rotate AND ed OR ed XOR ed DX and SIR To preserve bits using the bit mask data must be...

Page 196: ...sity Secondary Red Video Not Used Attribute Address Bits The Address Register is a pointer register located at hex 3CO This register is loaded with a binary value that points to the attribute data reg...

Page 197: ...I_II_I Attribute Address Palette Address Source Not Used Bit O Bit 5 Palette These 6 bit registers allow a dynamic mapping between the text attribute or graphic color input value and the display color...

Page 198: ...al 1 selects graphics mode Monochrome Display Color Display A logical oselects IBM monochrome display attributes A logical 1 selects color Display attributes Enable Line Graphics Character Codes When...

Page 199: ...gister pointed to by the value in the Attribute address register This value must be hex 11 before writing can take place The processor output port address for this register is hex 3CO Overscan Color R...

Page 200: ...ables the respective display memory color plane Video Status MUX Selects two of the six color outputs to be available on the status port The following table illustrates the combinations available and...

Page 201: ...eo data horizontally to the left Pel panning is available in both A N and APA modes In Monochrome A N mode the image can be shifted a maximum of 9 pels In all other A N and APA modes the image can be...

Page 202: ...O address They are distinguished by the pointer index in the address register To write to a data register the address register is loaded with the index of the appropriate data register then the selec...

Page 203: ...ers Register Mode of Operation Nlme Port Index 0 1 2 3 4 5 6 7 0 E F 10 F 10 0 1 2 3 Seq Address 3C4 Reset 3C5 00 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 Clock Mode 3C5 01 OB OB Q1 01 OB...

Page 204: ...5B 5B Vert Total 3 5 06 04 04 04 04 04 04 04 70 04 04 70 6C 70 6C 6C 6C 6C 6C Over1low 3 5 07 11 11 11 11 11 11 11 1F 11 11 1F 1F 1F 1F 1F 1F 1F 1F Preset Row SC 3 5 08 00 00 00 00 00 00 00 00 00 00...

Page 205: ...28 28 14 14 28 28 Underline Loc 3 5 14 08 08 08 08 Q 00 00 00 00 00 OD OF 00 OF OF OF OF OF Strt Vert Blk 3 5 15 EO EO EO EO EO EO OF 5E EO OF 5E 5F 5E 5F 5E 5E 5E 5E End Vert Blk 3 5 16 FO FO FO FO...

Page 206: ...00 00 Data Rotate 3CF 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Read Map Sel 3CF 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Mode Register 3CF 05 10 10 10 10 30 30 00 10 0...

Page 207: ...18 07 18 05 05 05 05 05 Palette 3CO 06 06 06 06 06 06 06 17 08 06 06 00 00 00 06 14 14 14 14 Palette 3CO 07 07 07 07 07 07 07 17 08 07 07 00 00 00 07 07 07 07 07 Palette 3CO 08 10 10 10 10 10 10 17 1...

Page 208: ...17 00 00 00 3F 3F 3F 3F 3F 3F Mode Control 3CO 10 08 08 08 08 01 01 01 OE 01 01 OB OB OB 01 08 08 08 08 Overscan 3CO 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Color Plane 3CO 12 OF OF...

Page 209: ...e 2 This effectively gives the user access to 512 characters instead of 256 character tables may be loaded off line The adapter must have 128K bytes of storage to support this function Up to four tabl...

Page 210: ...printed on the printer This is a special application which the Enhanced Graphics Adapter will support The 9 by 14 characters will be displayed when attribute bit 3 is a logical 0 and the IBM Color Gra...

Page 211: ...table write char string with attribute bit 3 1 cx character string length write character on line 22 of display pointer to character string location write char string with attribute bit 3 0 cx charact...

Page 212: ...d 8 by 8 double dot character font 43 character rows video interrupt call alternate screen routine alternate print screen routine video interrupt call Vertical Interrupt Feature The Enhanced Graphics...

Page 213: ...le IRQ latch 7 Update Enhanced Graphics Adapter during vertical blanking interval 8 Wait for next vertical interrupt Creating a Split Screen The Enhanced Graphics Adapter hardware supports an alphanum...

Page 214: ...at location zero and each subsequent row address is is determined by the 16 bit addition of the start of line latch and the offset register Screen B can be smoothly scrolled onto the CRT screen by upd...

Page 215: ...ich do screen centering may cause loss of the screen image if centering is attempted The Enhanced Graphics Adapter offers a wider variety of displayable monochrome character attributes than the IBM Mo...

Page 216: ...put ATRS L Attribute shift load This signal controls the serialization of the video information The shift register parallel loads at the dot clock leading edge when this signal is low G OUT Primary gr...

Page 217: ...ary blue output B OUT Blue output G Green input B Blue input R OUT Red output BLANK This is a composite horizontal and vertical blanking signal from the CRTC FEAT 1 This signal is output to bit 6 Feat...

Page 218: ...feature connector Signal Name Signal Name Gnd 1 2 12V 12V J1 J2 G OUT R OUT B OUT ATRS L BOUT GOUT G R B R ROUT FEAT 1 BLANK FEAT 0 FC1 FCO G I S N HIN VIN 14MHz Internal EXT OSC VOUT HOUT GND 31 32...

Page 219: ...Reference Manual System Board Component Diagram The Personal Computer has two DIP switch blocks the switch settings shown pertain to DIP Switch Block 1 The Personal Computer XT has one DIP switch bloc...

Page 220: ...on Switches The following diagram shows the location and orientation of the configuration switches on the Enhanced Graphics Adapter Optional Graphics Memory Expansion Card Off On 80 IBM Enhanced Graph...

Page 221: ...Display Adapter Configuration Enhanced Monochrome Color Graphics SWI SW2 SW3 SW4 Adapter Adapter Adapter On Off Off On Color Display Secondary 40x25 Off Off Off On Color Display Secondary 80x25 On On...

Page 222: ...W2 SW3 SW4 Adapter Adapter Adapter On On On On Color Display Primary 40x25 Off On On On Color Display Primary 80x25 On Off On On Enhanced Display Primary Emulation Mode Off Off On On Enhanced Display...

Page 223: ...e Signal Signal Name Description Pin Ground 1 Secondary Red 2 Primary Red 3 Primary Green 4 Primary Blue 5 Secondary Green Intensity 6 Secondary Blue Mono Video 7 Horizontal Retrace 8 Vertical Retrace...

Page 224: ...Pen Interface P 2 Connector P 2 Connector Pin Light Pen Input 1 Light Pen Not used 2 Enhanced Attachment Graphics Adapter Light Pen Switch 3 Ground 4 5 Volts 5 12 Volts 6 84 IBM Enhanced Graphics Ada...

Page 225: ...placed on pin 2 of the direct drive interface connector This supports the IBM Enhanced Color Display which utilizes six color outputs on the direct drive interface Jumper P3 changes the I O address po...

Page 226: ...86 IBM Enhanced Graphics Adapter...

Page 227: ...A1 AT6 iIT W m GNO A A D A l l A12 A l l A A A l b A AI A __r __ I I2 ______ __________________________________ ____________________ t liOM rr SHT Enhanced Graphics Adapter Sheet 1 of 11 m z c l z n...

Page 228: ...Ml i1W l ln HSI SHT j 7 11 RAS SHTb 7 11 n A S O SHTb tl a A1H 1 A AitSI tlI ACAS SHT II DTr 1 CClK 8 IO CCCL 23 CRT LATCH SHT Ci b 7 8 Ul 21 CPU LATCH SHY b 7 5 8 SiC SHT b 7 WE 2b l g I So SO b e U...

Page 229: ...500 9 8 Enhanced Graphics Adapter Sheet 3 of 11 m 2 c 2 n m c C x I c AAO SHT 4 b 11 n AAI I en AA2 AA AA4 C AAS AAb AA7 SHT 4 0 11 i m MAI4 SHT 2 x I MAIS SHT 2 CRTINT SHT I 9 REF AGR SHTS SYNC SHT...

Page 230: ...HTII SHT2 SKY SHT7 SHT7 CHAlN 0 AI 102 Al Ab A7 8 AlO AI All AI AI Alb Al7 Al8 q T SHT b SHT 1 1 Cl 7 8 orR SHT I 4 Jr Enhanced Graphics Adapter Sheet 4 of 11 m 2 c l 2 n m CI C xl l n en l CI l t m x...

Page 231: ...Q I 11 70 7Q 8 8D 8Q q SA1 ClK I DE I L LSOlf 11 IZ Vfub l 18 ID IQ 1 ZD U1 ZQ 17 1D 1Q 4 40 14 O 7 D bQ 11 7D 7Q 8 SO 8Q q SA7 CLK I DE I L 1 Z LSI I 11 UZ1 IZ I LSOO I T zi U 1 I 11 LSOO IIU II r Z...

Page 232: ...1 j7 gg E 000 ool 002 usa AAO 14 003 Ha AI n AO llifz AI r AAtI AS AA7iQ A6 U40 mi AAt7 A4 I 1 _________ 116 I CAS TMS4416 L g__ J TMS4416 MIDOf l 1 MID2 MID3 L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...

Page 233: ...ow A1 Il Mlro ft A4 I AO A Rrrm Ab BA7 10 A7 Il RAS r Ib CAS TMS441b 4 HlOO W G HlDI Hl02 TI1S441b InD H D l3 H D H1Db J H DO OQO H 01 H DI UH 02 I UII GRAPHICS CONTROL H O 17 OQl C2 SHT 8 m 0 SHT 8 2...

Page 234: ...e PO 19 SHT 9 10 5HT7 f CCO PI 21 G I m f I 19 1 P2 ZZ B 0 r IJ M2D2 18 eez P1 16 M201 17 CO p 17 G I H20 1b elf PI 18 9 VSHT9 IO Q M20C 1 CC 14 6 C 5HT 7 on 7 SHT C Il LG 5HTI 21 00 I 21 01 B02 2B 0...

Page 235: ...SOl BD2 801 FCIOW SHT4 LPClR SOD SOl S02 ua b 74lSBb UB 3 lk74LS244 14LS8b c 172A4 ZY4 U YI 18 b lA lYZ lb 8 ALf In 14 I ZAI lY4 2 2 01 20 2 li b I 0 U4Q q 40 LR I 1 O1 C RP I b PIN SIP 11 PI r PE C W...

Page 236: ...Gt 21 Iq 20 17 10 28 12 II I II 13 10 22 J 7 23 I 21 8 2 30 20 2q IB q 32 27 3 2 31 I l z n m FEAT 0 SHT q C FEAT I SHT q C EXT OSC SHT 2 ROUT SHT q D GOUT II l BOUT V R OUT G OUT n B OUT HOUT en VOUT...

Page 237: ...en 1120 22 H204 21 C 20 H207 16 I 00 17 t I 101 m 02 14 c 1 1304 M OC 12 H 07 10 AAO 3 AAI AA2 60 07 trj AA4 6 us S AA7 SAO s SAl BA2 n BA1 BA4 BAS Q SAO SlH 2 RASa 4S I I RiST 47 I I RAS Q Al ASI 44...

Page 238: ...7 r a b r r r r 1 q 2 8 I 7 1 1 I 2 r 28 27 PI 21 2 2 2X 2 2 2 22 r 1 21 r 20 r 1 1 1 18 8 17 47 II b Ir F 1 1 B 12 II 10 r 2 1 E1 C1 1 10UF t Graphics Memory Expansion Card Sheet 1 of 5 m 2 c l 2 C m...

Page 239: ...lEo SHT AO I A I A2 A4 AS Ab SHT A7 b 10 8 10 UI8 4 lb 18 SV UI9 4416 18 IS b 10 UIO Ib 18 SV UII Ib 18 b 10 V U2 18 I I IOOO MODI 1 1002 MOO HOIJl HOO MODb H007 Graphics Memory Expansion Card Sheet 2...

Page 240: ...S HT 3 SHT SH T SHT SHT 3 r SHT l A AS RAS I w E I AO AI A2 A4 A 5 Ab A7 5V b 1 5 __ rI O 8 b rr 1 I O 18 L i 4 b h 18 1 5 Graphics Memory Expansio n Card Sheet 3 o f 5...

Page 241: ...SHT SCAS SHT 3 RAS 2 SHT WE 2 SHT AO I AI A2 A4 AS A SHT A7 t It II 7 6 10 SV q U22 16 f T t tr II IS SV UI4 Lt4tb UIS 416 h 2 IS r L Graphics Memory Expansion Card Sheet 4 of 5 m 2 c l 2 n m C C c l...

Page 242: ...SHT SHT 1 SHT IH r SIlT 1 4 f 11 h h h Graphics Memory Expansion Card Sheet 5 of 5 m Z c l z n m CJ C lJ l 1 1 c n en l CJ l m lJ...

Page 243: ...OS conventions established in the listing The power on routines initialize this vector to point to the parameters contained in the IBM Enhanced Graphics Adapter ROM Interrupt Hex 44 Graphics Character...

Page 244: ...AH 3 READ CURSOR POSITION BH PAGE NUMBER ON EX IT DH Dl ROW COLUMN OF CURRENT CURSOR CH Cl CURSOR MODE CURRENTLY SET AH 4 READ liGHT PEN POSITION ON EXIT AH 0 liGHT PEN SW I TCH NOT DOWN NOT TR I GGER...

Page 245: ...88 C BL 0 ENABLE I NTENS I FY 189 C BL 1 ENABLE BLINKING 190 C 191 C AH 11 CHARACTER GENERATOR ROUTINE 192 C note this cs II wi II initiate 8 mode set completely 193 C resetting the video environment...

Page 246: ...302 C 1 0 192K 1 1 256K 303 C CH FEATURE BITS 304 C CL SWITCH SETTING 305 C 306 C BL 20 SELECT ALTERNATE PRINT SCREEN ROUTINE 307 C 308 C AH 13 WR I TE STR I NG 309 C ES BP POINTER TO STRING TO BE WR...

Page 247: ...it fa r d i sp I ay ena b I e 1 Dl EGA HAS A MONOCHROME ATTACHED 1 DO set c_type emulate active 0 07 04 D3 DO FEATURE BITS SWI TCHES 04a8h labe I dword save_ptr Is 8 pointer to a table 8S described a...

Page 248: ...C YRT TOT EQU 06H C OYERFLOW EQU 07H C PRE ROW EQU 08H C MAX SCAN LN EQU 09H C CRSR START EQU OAH C CRSR END EQU OBH C STRT HGH EQU OCH C STRT LOW EQU ODH C CRSR LOC HGH EQU OEH C CRSR LOC LOW EQU OfH...

Page 249: ...F BTS 0084 08 06 0488 R 681 C OR INFO_3 AL 0088 8A 1E 0488 R 682 C HOV BL INFO 3 008C E8 00F6 R 683 C CALL HK ENV 008F E9 0247 R 684 C JMP POST 0092 685 C SKI P 0092 CB 686 C RET 0093 687 C V IDEO_SET...

Page 250: ...OFFSET PST 8 0130 0105 R 818 C ow OFFSET PST 9 013F OlEO R 819 C ow OFFSET PST_A 0141 01 F4 R 820 C OW OFFSET pst B 0143 0207 R 821 C OW OFFSET PST OUT 0145 0207 R 822 C ow OFFSET PST OUT 0147 0207 R...

Page 251: ...C C C C C C C C C C C C C C C C C C C C C PST 7 PST 8 PST OUT AND CALL CALL RET AND CALL CALL RET AND CALL CALL RET PIout OUT NOT OR CALL CALL RET may may wout OUT NOT OR CALL CALL RET MK_ENV ENDP IN...

Page 252: ...ODE CONTROL COLOR C E9 RAM BYTE CNT FOR COLOR CD SET MODE TO 0 FOR COLOR CD TEST VIDEO STG oI SABLE V IDEO FOR COLOR CD C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C c C...

Page 253: ...G TO GO FORWARD C C C C C C C C6X CLD INC JZ DEC JMP 01 C4 01 C3 AL OOOH SET POI NTER TO BEG LOCAT I ON READ WR I TE FORWARD IN SlG ADJUST POI NTER READ WR I TE BACKWARD IN STG AL O DATA COMPARE OK C...

Page 254: ...EP LOOK I NG I F NOT ENABLE STUCK OFF VERT I CAL STUCK ON ENABLE STUCK ON C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C...

Page 255: ...8 1451 C MOV oS AX SET UP SEG REGS TO POI NT 04B9 8E CO 1452 C MOV ES AX TO BUFFER AREA 04BB C7 46 02 0000 1453 C MOV WORD PTRIBPJ 2J 0 INITIALIZE 04CO C7 46 04 0000 1454 C MOV WORD PTRI BP 114 J 0 IN...

Page 256: ...BIG AH O AA5 EGA_MEM_ERROR MEMORY OK AH O AA6 EGA_MEM_ERROR DX DL SEQ_ADDR aX 0208h OUT OX DL GRAPH ADDR ax 0403h OUT_OX OX DL ATTR_READ AL DX DL ATTR_WR I TE aX 3200h OUT_OX WORD PTR BP 4J 0 HOW SIG...

Page 257: ...CX BP AX BX POOSTG_ERRO AX DX PODSTG 2 CX BP SI 51 01 51 AX DX PODSTG_ERRO 51 51 CX BP AX AX PODSTG ERRO PODSTG 4 short podst9_err2 CX AX AH AH CH CH POOSTG ERRl AH l CL CL POOSTG ERR2 AH 2 BP AX DX...

Page 258: ...4 C Graphics parameters 1825 C 0000 1826 C base 1 equ S vi deo_pa rms 071A 1827 C base I labe I byte lB28 C 1829 C defau I t modes 1830 C 1831 C 0 071A 28 18 08 1832 C db 40d 24d 08d 0710 0800 1833 C...

Page 259: ...00 00 00 00 30 1951 C DB OOOH OOOH OOOH OOOH OOOH 030H 0857 OF 00 FF 1952 C DB OOfH OOOH OfFH 1953 C 1954 C 5 085A 28 18 08 1955 C db 40d 24d 08d OB50 4000 1956 C dw 04000h 1957 C 085f DB 03 00 02 19...

Page 260: ...004H 005H 09C3 06 07 10 11 12 13 2079 C DB 006H 007H 010H 011 H 01 2H 013H 09C9 14 15 16 17 08 00 2080 C DB o 14H 0 15H 016H 017H 008H OOOH 09CF OF 00 2081 C DB OOFH OOOH 2082 C 0901 00 00 00 00 00 10...

Page 261: ...00 00 5E 2B 2201 C DB OOOH OOOH OOOH OOOH 05EH 02BH OB36 50 14 OF 5F OA 8B 2202 C DB 05DH 0 14H OOFH 05 FH OOAH 08BH OB3C FF 2203 C OB OFFH 2204 C OB3D 00 01 00 00 04 07 2205 c OB OOOH 00 1h OOOH OOOH...

Page 262: ...014H 007H 03BH 039H 03aH 03bH OC89 3C 3D 3E 3F 08 00 2326 C DB 03cH 03dH 03eH 03fH 008H OOOH OC8F OF 00 2327 C DB OOFH OOOH 2328 C OC91 00 00 00 00 00 10 2329 C DB OOOH OOOH OOOH OOOH OOOH 0 1OH OC97...

Page 263: ...45 OL OFOH OL OAH OS ENOP NEAR AL AH OX AL OX AL AH OX AL OX ROUT I NE TO SOUNO BEEPER BP_ 1 PROC NEAR WOUT OUT OX AL RET BP_l ENOP BEEP PROC G7 PUSH MOV MOV CALL MOV OEC CALL MOV CALL MOV WIN IN MOV...

Page 264: ...SETUP TO THE ADAPTER QQl ENTRY 2 POP AX PUSH AX mav dh 3 AND AL 080H AND INFO 07FH OR INFO AL POP AX AND AL 07FH MOV CRT_MODE AL MOV DL CRTC_ADDR MOV ADDR_6845 OX MOV MOV ASSUME MOV MOV PUSH POP SUB R...

Page 265: ...oy h moy i nt e emp je dec bx save_pt r bX 08h bX dword ptr eo bx ax es ax bx ahO done ol Obh al es bx ol a I Offh ahO_done 8 I crt_mode sa 2 sl 58_ ah es bx al es bx 1 eX es bx 2 dX eo bx 4 bp es bx...

Page 266: ...UT THE VALUE ALL DONE __ __ POSITION THIS SERVICE ROUTINE CALCULATES THE REGEN BUffER I NPUT ADDRESS OF A CHARACTER I N THE ALPHA MODE AX ROW COLUMN POSITION OUTPUT AX OFFSET OF CHAR POSITION IN REGEN...

Page 267: ...I GHT PEN POSITION CH RASTER POS IT I ON OLD MODES CX RASTER POSITION NEW MODES BX BEST GUESS AT PIXEL HORIZONTAL POSITION _ _ _ _ _ _ _ _ _ _ _ ASSUME CS CODE DS ABSO SUBTRACT_TABLE VI LABEL BYTE DB...

Page 268: ...UTINE SETS THE ACTIVE DISPLAY PAGE ALLOWING 3339 C FOR MULTI PLE PAGES OF DISPLAYED VIDEO 3340 C INPUT 3341 C AL HAS THE NEW ACTIVE DISPLAY PAGE 3342 C OUTPUT 3343 C THE CRTC IS RESET TO DISPLAY THAT...

Page 269: ...CALLER 1345 3464 C PART_l ENOP 3465 C 1345 3466 C PART_2 PROC NEAR 1345 B6 03 3467 C mav dh 3 1347 B2 C4 3468 C MOV OL SEQ_AOOR SEQUENCER 1349 B8 020F 3469 C MOV AX 020FH MAP MASK ALL MAPS 134C E8 001...

Page 270: ...JE JMP PUSH MOV CAll JZ ADO MOV SUB CALL ADO ADO DEC JNZ POP MOV CAll ADD DEC JNZ CALL CMP JE MOV MOV WOUT OUT JMP C MOV JMP SCROLL_UP CS CODE OS ABSO ES NOTH I NG PROC NEAR BL AL MK ES AH 4 nl AH 7 N...

Page 271: ...OV BL AL LINE COUNT TO BL CALL MK ES PUSH BX MOV AX OX CALL SCROLL POS I T ION JZ N16 SUB SI AX MOV AH DH SUB AH BL CALL SUB SUB DEC JNZ POP MOV CALL SUB DEC JNZ JMP Nl0 SI BP 01 BP AH N13 AX AL t NIl...

Page 272: ...C R17 C PROC MOV PUSH PUSH REP POP POP ADD ADD PUSH PUSH MOV REP POP POP RET ENDP NEAR CL DL SI 01 MOVSB 01 SI SI 2000H DI 2000H SI 01 CL OL MOVSB 01 SI C CLEM A SINGLE ROW C C R18 PROC MOV PUSH REP...

Page 273: ...3969 C PUSH OX SAVE LOWER RIGHT 1503 E8 151 F R 3970 C CALL GR_ST_1 3971 C SRLOAO ES SET REGEN SEGMENT 1506 8E C2 3972 C MOV ES OX 1508 5A 3973 C POP OX 1509 8B C2 3974 C MOV AX OX 150B FE C4 3975 C I...

Page 274: ...C CALL ADO RET POSITION BX AX DETERM I NE LOC I N REGEN ADD TO START Of REGEN f I NO_POSIT ION ENDP EXPAND MEO COLOR ENTRY THIS ROUTINE EXPANDS THE LOW 2 BITS IN BL TO fiLL THE ENT I RE BX REG I STER...

Page 275: ...RET C GRX_PSN ENDP C C HK_ES C C C C C C C P6_A C C MOV MOV AND CMP JNE MOV MOV RET SI OBBOOH 01 EQU I P_FLAG 0l 030H DI 030H P6 A SI OBOOOH ES SI C C C C C iiEAii A uiiRE T TH I S ROUT I NE READS THE...

Page 276: ...ADDRESSING TO STACK 179A 1f 4344 C POP OS FOR THE STR I NG COMPARE 179B BA 0080 4345 C MOV DX 128 NUMBtR TO TEST AGA I NST 179E 4346 C S17P 179E 56 4347 C PUSH SI SAVE SAVE AREA PO INTER 179F 57 4348...

Page 277: ...3 oL GRAPH ADDR OUT OX AX 518H OUT_OX AL ES SI J AL SS I BPJ AL BP SI CRT COLS BX S12 1 BX AX 510H GRX_RECG NEAR OS ABSO ES OAOOOH DX OAOOOH ES OX GR CUR SI AX BX POINTS SP BX BP SP SAVE BYTES PER CHA...

Page 278: ...AIT UNTIL IT IS NO MORE INTERRUPTS GET STATUS IS IT HIGH WAIT UNTIL IT IS RECOVER TH E CHARIATTR PUT THE CHAR ATTR I NTERRU PTS BACK ON AS MANY TIMES C WR I TE CHARACTER ONLY AT CURRENT CURSOR POS I T...

Page 279: ...MP JAE AX AL 80H 51 IMAGE IS IN FIRST HALF CONTAINED IN ROM WLXS LOS JMP DS SI GRX_SET SI GRX_SET SHORT S2 I MAGE I SIN SECOND HALF I N USER RAM SUB WLXS LOS AL 80H DS SI EXT_PTR 51 EXT_PTR C C C DETE...

Page 280: ...C C C C C C C C C C C C C C C C C C C C C C C C C C C C C S20A NO_XOR S13A Sl K TEST JZ MOV MOV CALL JMP PUSH MOV MOV CALL SUB PUSH MOV PUSH CALL STOSB ADO DEC LOOP POP POP POP MOV MOV MOV CALL PUSH P...

Page 281: ...3 5004 5005 5006 5007 5008 5009 5010 5011 5012 5013 5014 5015 5016 5017 5016 5019 5020 5021 5022 5023 5024 5025 5026 5027 5028 5029 5030 5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 MOVE INTENSIT...

Page 282: ...O REGEN BUFFER FOR BYTE OF INTEREST AH MASK TO STR I P OFF THE BITS OF INTEREST CL BITS TO SHIFT TO RIGHT JUSTIFY THE MASK IN AH OH BITS I N RESULT i PROC NE R PUSH BX SAVE BX DURING OPERATION PUSH AX...

Page 283: ...4 8A E8 5226 C MOV CH AL SAVE COLOR lC26 f6 C5 80 5227 C TEST CH 080H SEE If XOR lC29 74 OA 5228 C JZ WD A NO XOR lC2B B4 03 5229 C MOV AH G_DATA_ROT DO XOR lC2D BO 18 5230 C MOV AL 018H XOR fUNCT I O...

Page 284: ...ds absO es noth i n9 dx es Ob800h OX Ob800h es DX dx R3 AL ES SI AL AH AL CL CL DH AL CL v ret ENDP crt_mode Ofh read_dot_2 mem det read_dot_2 PROC NEAR DS ABSO ES NOTH I NG RD S RD l S DL AH AH 1 DL...

Page 285: ...9 C CMP DH ROWS BOTTOM OF SCREEN 1077 75 E8 5470 C JNE u6 YES SCROLL THE SCREEN 1079 EB BB 5471 C JMP Ul NO JUST SET THE CURSOR 5472 C 5473 C BELL FOUND 5474 C lD7B 5475 C Ull 107B B3 02 5476 C MOV BL...

Page 286: ...C7 5603 MOV AL BH 1E24 E8 109C R 5604 CALL PAL SET lE27 E8 10B4 R 5605 CALL PAL ON 5606 lE2A OB EO 5607 or bp bp lE2C 74 05 5608 jz bm out lE2E 83 C7 11 5609 add d i 011h lE31 26 88 30 5610 es di bh...

Page 287: ...EC AL WH I CH PARAMETER lEE5 75 07 5738 C JNZ H7 MUST BE ONE lEE7 B7 OE 5739 C MOV BH 0140 BYTES PER CHARACTER lEE9 BD 0000 E 5740 C MOV BP OFFSET CGMN 8 X 14 TABLE OFfSET lEEC EB 05 5741 C JMP SHORT...

Page 288: ...RLN_LOC OUT_OX AL AH C_MAX_SCAN_LN OUT_OX AL ch sl cl al cl ah l 10h BL CRT_MODE AX 3500 BL l H11 brst det hll AX 200D POI HTS AX ROWS AL AL AH AH POINTS AX OX A lDR_6845 AH C_VRT_OSP_END OUT OX AL RQ...

Page 289: ...FORM 5981 C ASSUME DS ABSO 2068 3C 30 5982 C CMP AL 030H 206A 74 03 5983 C JE F6 206C 5984 C F5 206C E9 219B R 5985 C JMP V_RET 206F 5986 C F6 206F 8B OE 0485 R 5987 C MOV CX PO I NTS 2073 8A 16 0484...

Page 290: ...J8 JE CMP JE JMP ACT_l ACT_3 BL 020H ACT_2 V_RET SRLOAO OS O SUB OX OX MOV OS OX CLI ALTERNATE PRINT SCREEN I NVALI 0 CALL NEW PR I NT SCREEN MOV WORD PTR INT5_PTR OFFSET PRINT_SCREEN MOV WORD PTR I N...

Page 291: ...C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C ASSUME PR I NT SCREEN CS CODE OS ABSO PROC FAR STI MUST RUN WI TH I NTS ENABLED MUST...

Page 292: ...EH OHM ODBH OFFH OHH OC3H TH 02 DB OE7H OFFH 07EH OOOH OOOH OOOH BT_02 DB OOOH OOOH OOOH 06CH OFEH OFEH OFEH OFEH TH_03 DB 07CH 038H 010H OOOH OOOH OOOH BT_03 DB OOOH OOOH OOOH 010H 038H 07CH OFEH 07C...

Page 293: ...6CH 038H 076H ODCH TH_26 Ie ggg g g g g g g g g ggg OOOH OOOH OOOH OOOH OOOH OOOH OOOH OOOH BT 27 000H 000H 00CH 01BH 030H 030H 030H 030H TH 28 030H 018H 00CH 000H 000H 000H BT_28 000H 000H 030H 018H...

Page 294: ...060H TH_50 P 060H 060H OFOH OOOH OOOH OOOH BT_50 P 000H 000H 07CH OC6H OC6H OC6H OC6H OD6H TH_51 Q ODEH 07CH OOCH OOEH OOOH 000H BT_51 Q OOOH OOOH OFCH 066H 066H 066H 07CH 06CH TH_52 R 066H 066H OE6H...

Page 295: ...OH BT_77 L C W OOOH 000H OOOH OOOH OOOH OC6H 06CH 038H TH_78 L C X 038H 06CH OC6H OOOH OOOH OOOH BT_78 L C X 000H OOOH OOOH OOOH OOOH OC6H OC6H OC6H TH_79 L C Y OC6H 07EH 006H OOCH Of8H OOOH 8T_79 L C...

Page 296: ...000H BT_AO OODH 00CH 018H 030H 000H 038H 018H 018H TH_Al 018H 018H 03CH OOOH OOOH OOOH BT_Al OOOH 018H 030H 060H 000H 07CH OC6H OC6H TH_A2 OC6H OC6H 07CH 000H 000H 000H BT_A2 OOOH 018H 030H 060H OOOH...

Page 297: ...36H 036H BT_C9 036H 036H 036H 036H 036H OF7H OOOH OFFH TH_CA OOOH OOOH OOOH OOOH OOOH OOOH BT CA OOOH OOOH OOOH OOOH OOOH OFFH OOOH OF7H TH CB 036H 036H 036H 036H 036H 036H BT_CB 036H 036H 036H 036H 0...

Page 298: ...BTJ5 DB OOOH 000H 000H 018H 018H 000H 07EH 000H THJ6 DB 018H 018H 000H 000H 000H OOOH BT_F6 DB OOOH 000H 000H 000H 076H 00CH 000H 076H THJ7 DB ODCH OOOH OOOH OOOH OOOH OOOH BTJ7 DB OOOH 038H 06CH 06C...

Page 299: ...H 066H 066H OOOH 066H OOOH 0_13 66 00 47 OOAO 7F DB DB 7B 1B 1B 48 DB 07 FH ODBH ODBH 07BH 01 BH 0 1BH 01 BH OOOH 0_14 18 00 49 00A8 3E 63 38 6C 6C 38 50 DB 03EH 063H 038H OoCH 06CH 038H OCCH 078H 0_1...

Page 300: ...CH 060H 060H OFOH OOOH PO_50 FO 00 173 0268 78 CC CC CC DC 78 174 DB 076H OCCH OCCH OCCH OOCH 078H 01 CH OOOH Q 0_51 lC 00 175 0290 FC 66 66 7C 6C 66 176 DB OFCH 066H 066H 07CH 06CH 066H OE6H OOOH R 0...

Page 301: ...38 18 18 18 296 297 07CH OC6H 038H 018H 0 18H 0 18H 03CH OOOH 0_8C 3C 00 298 0468 EO 00 70 30 30 30 299 OEOH OOOH 070H 030H 030H 030H 078H OOOH 0_80 78 00 300 0470 C6 38 6C C6 FE C6 301 DB OC6H 038H...

Page 302: ...B OOOH OOOH 03 FH 030H 037H 036H 036H 036H D_C9 36 36 424 0650 36 36 F7 00 FF 00 425 DB 036H 036H OF7H OOOH OFFH OOOH DOOH OOOH D_CA 00 00 426 0658 00 00 FF 00 F7 36 427 DB OOOH OOOH OFFH OOOH OF7H 03...

Page 303: ...OOEH 01 BH 01BH 018H 018H 018H 018H 018H D_F4 16 16 513 07A8 16 18 18 16 16 06 514 DB 016H 016H 018H 018H 016H OD8H OD8H 070H DJ5 06 70 515 07BO 30 30 00 FC 00 30 516 DB 030H 030H OOOH OFCH OOOH 030H...

Page 304: ...164 IBM Enhanced Graphics Adapter...

Page 305: ...ister 53 color fnapping 10 Color Plane Enable Register 60 compatibility issues 74 configuration switches 80 CRT Controller descIiption 3 registers 24 CRT Controller Address Register 24 CRT Controller...

Page 306: ...zontal Total Register 25 Index 2 I Input Status Register One 15 Input Status Register Zero 14 Interface 76 feature connector 76 L Light Pen High Register 36 light pen interface 84 Light Pen Low Regist...

Page 307: ...ster 50 registers Attribute Controller 56 CRT Controller 24 external 12 Graphics Controller 45 Sequencer 18 Reset Register 18 s Sequencer description 3 registers 18 Sequencer Address Register 18 Set R...

Page 308: ...v Vertical Display Enable End Register 38 vertical inteJ fupt feature 72 Index 4 Vertical Retrace End Register 36 Vertical Retrace Start Register 36 Vertical Total Register 30...

Page 309: ..._ Extended Monochrome Graphics Adapter Personal Computer Hardware Reference Library...

Page 310: ...TNL SN20 9844 March 1987 to 75X0235 ii Extended Monochrome Graphics Adapter...

Page 311: ...ch 1987 to 75X0235 Contents Description 1 Introduction 1 Programming Interface 5 Programming Model 6 Addressing 8 Graphic Operation Commands 30 Graphic Operation Queue Load 60 Connector Specifications...

Page 312: ...TNL SN20 9844 March 1987 to 75X0235 iv Extended Monochrome Graphics Adapter...

Page 313: ...reclude the use of an Extended Monochrome Graphics Display Adapter in PC AT systems Advanced features include A fast graphic operation processor which can do bit block transfers line draw image copy m...

Page 314: ...eometric objects in the display buffer Transfer image information stored in I O channel memory Asynchronous Graphic Operation Queueing A graphic operation queue mechanism is implemented in hardware an...

Page 315: ...111111 Instruction ROM Processor Figure 1 Extended Monochrome Graphics Display Adapter Block Diagram The Extended Monochrome Graphics Display Adapter consists of 7 major components 1 The I O channel i...

Page 316: ...nchronously from the system In its simplest form the linked list of commands forms a FIFO buffer with the system loading commands at one end and the graphic processor executing them at the other end A...

Page 317: ...omatically Logical functions such as AND OR or XOR are also specified during the writing of selected bits Bit alignment masking and rotation barrel shifting are all performed by hardware within the ad...

Page 318: ...28K block of memory is addressable as a part of the I O channel memory map A contiguous 96K byte segment of this block is used as the adapter video frame buffer The remainder is hidden memory in the s...

Page 319: ...nted in the I O space as control registers The I O registers contain various control and status bits that allow the system to specify a variety of adapter operating modes While all memory implemented...

Page 320: ...te operations This area is called memory mapped memory Ten control registers are implemented within a 64 byte space called I O mapped memory These locations are accessed via I O channel read write ope...

Page 321: ...8 I I I I I I Figure 3 I O Channel DMA X BIT ADDRESS 4 BITS 15 I I I I Bits Bits Bits X WORD ADDRESS 10 BITS MODE REGISTER 00 01 03 04 07 08 11 12 15 ARRAY X Y ADDRESS HORIZONTAL ACCESS BIT RESERVED W...

Page 322: ...system as a conventional area of I O channel memory Orthogonal Access Masking Besides the 16 horizontal addressing modes the access direction may be specified horizontally or vertically The previous...

Page 323: ...097FFE 768 bits high HARDWARE ADDITIONAL CURSOR PATTERNS 848 896 1006 1007 1008 1009 CURSOR IMAGE AND I XOR START FONTS AND STACK AREA QUEUE LIST AREA HARDWARE RESERVED SCAN LINE AREA HARDWARE RESERVE...

Page 324: ...ion of the bit map start at X D80000 through X D97FFF 96K bytes Cursor Area The cursor is 48 X 64 bits and is built from two cursor patterns an AND pattern and an XOR pattern which are stored in the h...

Page 325: ...register is initialized to X OOOO with a POR or reset adapter command This register is loaded by the system to specify the X position in pels over which the hardware supported cursor is positioned Th...

Page 326: ...hen the Y cursor register equals 0 the bottom most scan line of the cursor is displayed on the first scan line on the screen scan line 0 When the Y cursor register equals 767 63 830 then the top most...

Page 327: ...unexecuted queue loads count The counter is normally incremented by the system after a new command sequence has been loaded and is ready for execution by the adapter It is decremented conditionally b...

Page 328: ...nd The next queued command word location is stored in this register and may be read or modified via an adapter memory read write channel operation During normal graphic operation processing this regis...

Page 329: ...Conversion DEVICE Y BIT X WORD DECODE ADDRESS ADDRESS 0 1 1 0 1 1 o 0 Bits 7 16 Bits 17 22 I O CHANNEL ADDRESS 0 Y BIT X WORD LEAST SIGNIFICANT ADDRESS ADDRESS 4 BITS OF X ADDRESS 10 BITS 6 BITS ARE...

Page 330: ...xamples of queue pointer values I O Channel Equivalent Address Queue Pointer Value Value D988AE C457 D9AOOO DOOO D9BFDO DFE8 D9COOO EOOO D9C02A E015 D9EOOO FOOO D9FOOO F800 D9F7FE FBFF D9FFFE FFFF 18...

Page 331: ...line pointer that will be serialized by the video output circuits The table below shows the scan line value in relation to the vertical cycle Scan Line Values Relative Vertical Period 000 767 Active...

Page 332: ...ATA FIELD 71 8 I I I I Figure 12 Mode Shadow Register Address X D9FSI2 The mode shadow register is updated each time the mode register is written see Mode Register on page 24 The programmer can read t...

Page 333: ...n point is stored in this register Care should be taken when writing to this register See graphic operation command queue for details Queue Mode Register DATA FIELD 15 Bits 00 14 reserved Bits 15 SELE...

Page 334: ...Counter X ODI6 Write Diagnostic Promlevel Check X ODI8 Write Reserved X ODIA Write Enable Video Data Output X ODIC Write Reserved X ODIE Write Reserved X OD20 Write Reset Adapter X OD22 Write Reset Fr...

Page 335: ...address signals that a pending interrupt was serviced and re enables the adapter interrupt request pulse generating circuit Reset Frame Sync Interrupt Register Address X OD22 This is a write only regi...

Page 336: ...he start bit displacement the start bit occurs The access is a string of 1 to 16 bits to the right of the start bit With the horizontal access bit in an inactive state the access is a string of 1 to 1...

Page 337: ...20 9844 March 1987 to 75X0235 Write Number Count of Bits Hex Written 0 16 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 A 10 B 11 C 12 D 13 E 14 F 15 Figure 17 Write Count Mask Extended Monochrome Graphics Adap...

Page 338: ...on 3 Reserved 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 I O data AND destination 9 Replace destination with I O data A I O data XOR destination 11 I O data OR destination 12 Reserved 13 Reserved 1...

Page 339: ...which enables processing interrupts and video All bits in this register are normally initialized at power on to the ofT or 0 state Frame Sync Int Enable bit 0 This bit when active places any frame syn...

Page 340: ...c bit 6 This bit is for diagnostics and indicates the horizontal cycle is working Increment Queue Counter Register Address X OD14 This is a write only register and the data is of no significance A wri...

Page 341: ...er register D9F804 0000 Scan line register D9F808 0000 Mode shadow register D9F812 8090 Mode register ODIO I O 8090 Control status register OD12 I O 0000 Graphic operation processing and command queue...

Page 342: ...Graphic Operation Command Queue Commands for the graphic operations processor are loaded into a command queue by the system and sequentially executed subject to branching types of commands by the adap...

Page 343: ...queue counter has incremented past 0 the graphic operation processor begins fetching command words from the queue starting at the address designated by the queue pointer register As each command is pr...

Page 344: ...queue list structure The graphic op interrupt flag bit if active sets the graphic operation interrupt latch at the completion of the graphic operation This action can be observed via the graphic oper...

Page 345: ...l zero s 5 Operand A and Operand B 6 Operand A and Operand B 7 Pass through Operand A 8 Operand A and Operand B 9 Pass through Operand B test A Operand A xor Operand B B Operand A or Operand B C Opera...

Page 346: ...ddress Y ADDRESS 10 bits X ADDRESS 10 bits I I I 1 0 1 0 1 0 1 0 I 16 Bits Branch Command Word Figure 23 Branch Command Word Address Field The other 6 low order bits of the branch command word form th...

Page 347: ...oad Graphic OP Processor Register 4 R4 0101 Load Graphic OP Processor Register 5 R5 0110 Load Graphic OP Processor Register 6 R6 0111 Load Graphic OP Processor Register 7 R7 1000 Load Graphic OP Proce...

Page 348: ...lower right corner point X Y exclusive and the size DX DY of the rectangular region Note The microcode register ending conditions are defined for graphic operation types X 2F 35 36 2C 2D and 2E only...

Page 349: ...l screen is shown below Note that a hex value of 000 represents a value of 1024 pels both for X and DX The same is true for Y and DY Queue Queue Action By Register Register Reg Address Data Queue Proc...

Page 350: ...ction bits as listed below Rectangular fill replace off Rectangular XOR destination Rectangular fill replace on LF 0 Set destination to LF 9 Msk destination Reverse video LF F Set destination to 1 ___...

Page 351: ...t map Only one subtype is specified via the LF bits as listed below Rectangular XOR Destination LF 9 Destination Result Destination __ R_EV_E_R_S_E_V_I_D_EO_C_H_A_RA_C_T_E_R_L_IN_E_ lOY 20 X Y LOWER R...

Page 352: ...nt XD YD The size DX DY of the rectangle must also be specified The queue load for these graphic operation types is up to seven 16 bit words as shown below The queue load below represents a rectangula...

Page 353: ...e 27 Copy Overlapped Character Line To achieve a rectangular copy the logical function subtype must be set to X 9 In consecutive repeated copy operations graphic operations type 30 to locations with a...

Page 354: ...ctangular Merge And Rectangular Merge And Rectangular Merge XOR Rectangular Merge OR Rectangular merge OR Rectangular merge OR LF 1 Source destination Result destination LF 2 Source destination Result...

Page 355: ...235 XD YD LOWER RIGHT CORNER exclusive I _ _ _ _S_O_U_R_C_E_T_E_X_T_W_I_N_D_O_W ____ DELTA Y 1 IDYl I XS YS LOWER RIGHT CORNER I exclusive DELTA X 1 oX Figure 29 And a Test Source Window to a Graphic...

Page 356: ...lar to the rectangular copy merge graphic operation The destination and source rectangular areas should not overlap DESTINATION SOURCE XD YD LOWER RIGHT CORNER exclusive DELTA Y 1 IDY XS YS LOWER RIGH...

Page 357: ...rectangular copy merge graphic operation The destination and source rectangular areas should not overlap DESTINATION SOURCE XD VD LOWER RIGHT CORNER exclusive DELTA V 1 mv XS VS LOWER RIGHT CORNER L r...

Page 358: ...py merge graphic operation The destination and source rectangular areas should not overlap DESTINATION XD YD LOWER RIGHT CORNER exclusive L _ _ _ _ _ _ S_O_U_R_C_E_____ 11 DELTA Y 1 IDYl XS YS LOWER R...

Page 359: ...e graphic operation The destination and source rectangular areas should not overlap DESTINATION XD YO LOWER RIGHT CORNER exclusive I _ _ _ _ _ _ S_O_U_R_CE ______ JI DELTA Y 1 IDYl 1 _ _ _ _ _ _ _ _ _...

Page 360: ...ad X to R5 X2 16 o 1023 Que Ptr 3 X 6200 LOAD Y to R6 Y2 512 o 1023 Que Ptr 8 X D35F Execute Line Draw Set line on No decrement At the completion of the line draw the X Y to coordinate is saved in the...

Page 361: ...null graphic operation allows the user to specify the next vector to be drawn as a delta or increment from the last end point specified and end with a null point Logic functions are the same as type X...

Page 362: ...tive draw R5 Xl DX R6 YI DY Draw vector from XI YI to Xl DX YI DY Relative Move to X 2E The relative move to graphic operation allows the user to add a delta or increment to the last start point coord...

Page 363: ...ch image array width line that are within the height of the desired rectangle but do not contain data within the width of the desired rectangle and thus are skipped in the DMA transfer process The Ski...

Page 364: ...e starting word Array width X OSO bytes Lower right corner exclusive Lower right corner exclusive Number of pels in width Number of pels in height Note The registers used by the DMA graphic operations...

Page 365: ...MDA IMAGE STRUCTURE o 1 1 o 001014 001094 001114 TNL SN20 9844 March 1987 to 75X0235 MSB DO LSB D15 DX2 19 DX 1 31 BITS 41 001016 001096 001116 x MSB LSB DO xx DY xx 1 3 xx I 12 1L _ 14 y Figure 34 TD...

Page 366: ...t Register RA A23 A17 Source high X AOOO Upper left start word address RB A16 A9 Source mid X B008 Upper left start word address R4 A8 Al Source low X 4009 Upper left start word address R3 Bit offset...

Page 367: ...g Function Value of Comment Register RA A23 A17 Source high X AOOO Upper left start word address RB A16 A9 Source mid X B008 Upper left start word address R4 A8 A1 Source low X 4009 Upper left start w...

Page 368: ...omment Register RA A23 A17 Source high X AOOO Upper left start word address RB A16 A9 Source mid X BOOS Upper left start word address R4 AS AI Source low X 4009 Upper left start word address R3 Bit of...

Page 369: ...eration Queue Queue Action By Address Data Queue Processing X FOOO X AOEO Load RA with 8 high order bits of branch target queue pointer value X EFFF X B015 Load RA with 8 low order bits of branch targ...

Page 370: ...restore queue processing operation Example Scan Line Sync stop queue processing until the scan line counter reaches a value of X IF5 Queue Queue Action By Address Data Queue Processing Calculate SLC 1...

Page 371: ...map area is not displayed on the monitor The monitor instead produces the background screen type either an all white screen or an all black screen depending on the current setting of the black on whi...

Page 372: ...dec Q flag on 15 GRAPHIC OP EXECUTE COMMAND WORD FOR THIS EXAMPLE 11011011101011111 I I I I I I I I I I I I I I X DB5F I I I I II Bits 00 03 EXECUTE DECODE 1 1 0 1 Bit 04 DECREMENT QUEUE COUNTER FLAG...

Page 373: ...the upper left corner point of a rectangle X2 Y2 represent the end point coordinates of a line or the lower right corner point of a rectangle DX DY represent X2 Xl and Y2 Yl respectively Type Graphic...

Page 374: ...Execute command 2F RECTANGULAR FILL HOR VER OPTIMIZED Data Reg Parameter 7xxx R7 XD Ire 6xxx R6 YD Ire 9xxx R9 DX 1 8xxx R8 DY 1 D2Fs Execute command 30 RECTANGULAR COPY MERGE Data Reg Parameter 5xxx...

Page 375: ...Y 1 D31s Execute command 32 RECTANGULAR COPY MERGE 90 DEGREE ROTATE Data Reg Parameter 4xxx R4 Xsource Ire 5xxx R5 Ysource Ire 7xxx R7 Xdest Ire Axxx RA Ydest Ire Oxxx RO DX 1 9xxx R9 DY 1 D32s Execut...

Page 376: ...x R4 Xsource Ire 5xxx R5 Ysource Ire Axxx RA Xdest DX 1 1 Ire 7xxx R7 Ydest Ire Oxxx RO DX 1 9xxx R9 DY 1 D34s Execute command 35 VECTOR DRAW Data Reg Parameter 1xxx Rl Xl Oxxx RO Y1 5xxx R5 X2 6xxx R...

Page 377: ...LYLINE DRAW WITH ENDING NULL 36 CONNECTED CONTINUATION Data Reg Parameter 5xxx R5 X2 6xxx R6 Y2 D36s Execute command 37 TDDMA CUT PASTE FROM SYSTEM MEMORY Data Reg Parameter AOxx RA DMA addr HI O 6 BO...

Page 378: ...t offset 2xxx R2 Skip amount 7xxx R7 Xdest Ire 6xxx R6 Xdest DX I I Ire 5xxx R5 DX I Oxxx RO 2 s comp of DX 1 D38s Execute command 39 TDDMA CUT PASTE FROM SYSTEM MEMORY 45 DEGREES DIAGONAL FLIP Data R...

Page 379: ...xxx R3 Bit offset 2xxx R2 Skip amount 7xxx R7 Xdest Ire 6xxx R6 Ydest DY 1 1 Ire 5xxx R5 DX 1 Oxxx RO 2 s Comp of DY 1 D3As Execute command 3B BRANCH AND LINK QUEUE one level deep Data Reg Parameter A...

Page 380: ...9844 March 1987 to 75X0235 Type Graphic Operation Name and Queue Load Data Example 3E SET VIDEO ON Data D3EO Execute command 3F SET VIDEO OFF Data D3FO Execute command 68 Extended Monochrome Graphics...

Page 381: ...5 RESERVED 6 GND VIDEO 7 VIDEO 8 EXTENDED M ONOCHROME ONOCHROME EXTENDED M GRAPHICS S ADAPTER DISPLAY GRAPHIC 9 I GND VIDEO VIDEO GND VIDEO VIDEO GND VIDEO VIDEO GND HSync HSync 1 3 5 7 9 11 13 15 2 4...

Page 382: ...TNL SN20 9844 March 1987 to 75X0235 70 Extended Monochrome Graphics Adapter...

Page 383: ..._ 512 KB Memory Expansion Option Personal Computer Hardware Reference Library...

Page 384: ...ii...

Page 385: ...Contents Description 1 Memory Cycles 1 Memory Address Switches 1 110 Channel Check 3 Specifications 3 Voltage Tolerances 3 Power Dissipation 3 Temperature Variation 3 Logic Diagrams 4 iii...

Page 386: ...Notes iv...

Page 387: ...kable interrupt to the system Memory Address Switches There are two banks of memory address switches on each memory adapter These switches are set to values for the first second third etc memory adapt...

Page 388: ...G G G G Q Q 000 00 0 H Switch Bank 1 1st512KB Memory Expansion Adapter 2nd 512KB Memory Expansion Adapter 3rd 512KB Memory Expansion Adapter 4th 512KB Memory Expansion Adapter 5th 512KB Memory Expans...

Page 389: ...riting to the failing card will clear the status bit Specifications Voltage Tolerances The maximum variation of the 5 Vdc is 5 at the adapter pins Power Dissipation The 5 Vdc power used by the adapter...

Page 390: ...Notes 4 512KB Memory Expansion Option...

Page 391: ...7L L 3 44 02 Q21 1 7 RAS CSI SHT2 1 I T i S R2 R I ni IOKn IZ hz FZO _ __ _u I lU11 131 0 I II IIf S b 0 Q I r LSbB2 AI 2 In I qUI3 jr l 1 RAS S2 SHT2 SI NOTE1 UI2 3 9 h SW9 _ ILj 1Q 0I1PARATOR I G E...

Page 392: ...10 100 7 q Ulb RNZ FOB b 11 FlO ALS04 I 12 q 100 B 0 b 2 Ulb RNZ RAS 0 SHT 5 RAS I SHT 5 AS OL SHT 5 0 SHT7 0 UIO 11 FlO ALS04 U18 IZ I OO 1 q B RNZ UIO 0 FlO 4 U18 2 11 4 1 RNZ AS OH SHT 5 CAS IL SH...

Page 393: ...6 SHT 8 I B B8 18 SHT 4 5 6 TlR SHT7 Iq G Al S2 t IUS IlIIV ACVR SHT7 81 Moe SHT 4 5 6 SHT7 IV B2 12 MDq SHT 4 5 6 SHT7 A3 83 13 1 1010 SHT 4 5 6 SHT7 Ub B t 14 f l 11 SHT 4 5 6 SHT7 A as I 1 1012 SHT...

Page 394: ...CHECK 8 A 9 B EVEN 10 C MOP IN 0 SHT 5 6 II 0 U7 12 E 11 F I G Z H I B l FZBO PARITY CHECK 8 A 9 B EVEN IilP IN I SHT 5 6 10 C 0 US IZ E 11 F I G 2 H I A wi I I 11 F7 12 U2 10 II U2 8 120 PR Q q I U2...

Page 395: ...SHT81 SHIel SAl SAl6 Of 4 ________4 ________ B ________4 2 4 2 II 1A I 2 0 L _lS L r L li 1 l SHT2 RASl 1 L I 1 t4 1 141 14 OCtJTUIj8 i l 1 1 OIN DOUr r M D P OUT o SHT4 6 1 THIS CARD PROVIDES A CHOIC...

Page 396: ...HAt I At _ _ _ _ l9 A1 _ B MW SHT 5 8MA 0 ISHT 5 8MAI ISHT 5 9MA2 SHT5 BHAl SHT 5 8HA4 ISHT 5 8MA ISHT 5 8MA6 ISHT 5 8MA1 ISHT2 2q WE __ RAS 2 4_ me I C A S IL____ d rn ISHT2 RAS 2 ISHT2 CAS IL ISHT2...

Page 397: ...21 H HEHW SHT2 J H L A I 8 SHTI J H L A I 7 SHTI L f l AI YIf S _ _ _ _ BHEHR SHT3 4 L A2 Y2 16 BHEHW SHT 4 5 SHT81 5 A O f 1 6 A l n 4 SAO SHT2 3 5 SHT 8 REFRESH ylt l BREFRESH SHT 1 5 047uF CER H1 7...

Page 398: ...T7 A30 SAI SHT5 Al9 SA2 SHT5 Al8 SA3 SHT5 Al7 SA4 SHT5 A2b SAe SHT5 A2e SAb SHT5 A24 SA7 SHT5 Al3 SA8 SHT5 A22 SA9 SHT5 All SAIO SHT5 AlO SAII SHT5 AI9 SAI2 SHT5 AI8 SAI3 SHT5 AI7 e B29 Alb SAI4 SHT5...

Page 399: ..._ Monochrome Display and Printer Adapter Personal Computer Hardware Reference Library...

Page 400: ...ii...

Page 401: ...tion 1 Monochrome Display Adapter Function 1 Description 1 Programming Considerations 5 Specifications 9 Printer Adapter Function 11 Description 11 Programming Considerations 13 Specifications 17 Logi...

Page 402: ...iv...

Page 403: ...tem unit s microprocessor has direct access No parity is provided on the display buffer Two bytes are fetched from the display buffer in 553 ns providing a data rate of 1 8M bytes second The adapter s...

Page 404: ...the adapter are Supports 80 character by 25 line screen Has direct drive output Supports 9 PEL by 14 PEL character box Supports 7 PEL by 9 PEL character Has 18 kHz monitor Has character attributes 2...

Page 405: ...s 1 Multiplexer Data Bus Gating BOO 7 J 8 MA MC6845 CRTC r 10 2K Memory Character Code 8 row 8 row Character Clock Octal t 1_ Latch RA Character 4 Generator DOTCLK Shift Register Serial Dots HSYNC VSY...

Page 406: ...4 Monochrome Adapter...

Page 407: ...Maximum Scan Line Scan Line D Address R10 Cursor Start Scan Line B R11 Cursor End Scan Line C R12 Start Address H _ _ 00 R13 Start Address L 00 R14 Cursor H 00 R15 Cursor L 00 R16 Reserved R17 Reserve...

Page 408: ...ntensity bits may be combined with the foreground and background bits to further enhance the character attribute functions listed below Background Foreground R G B R G B Function 0 0 0 0 0 0 Non Displ...

Page 409: ...he I O address decode is from hex 3BO through hex 3BF The bit assignment for each I O address follows I O Register Address Function 380 Not Used 381 Not Used 382 Not Used 383 Not Used 384 6845 Index R...

Page 410: ...e 1 Not Used 2 Not Used 3 Video Enable 4 Not Use d 5 Enable Blink 6 7 Not Used 6845 CRT Control Port 1 Hex 3B8 Bit Number Function 0 Horizontal Drive 1 Reserved 2 Reserved 3 Black White Video 6845 CRT...

Page 411: ...ed Display Intensity Video Horizontal Vertical 9 Pin Monochrome Display connector o 1f l6 sl0J 9 o 1 2 3 4 IBM Monochrome 5 Display and 6 Printer Adapter 7 8 9 Note Signal voltages are 0 0 to 0 6 Vdc...

Page 412: ...10 Monochrome Adapter...

Page 413: ...rcuit is also ORed with a program output point allowing a device to receive a power on reset when the system unit s microprocessor is reset The input output signals are made available at the back of t...

Page 414: ...nnector Bus BUffe r8 1 1 Data Latc h_ e 8 4 Enable Clock Trans 1oIIII 8 ____ ceiver rDIR Reset DIR Read Data Write Data O C Drivers Command I J Decoder Write Control Read Status Read Control Bus Contr...

Page 415: ...on the connector A description of each instruction follows IBM Monochrome Display Printer Adapter Output to address hex 3BC Bit 7 Bit 6 Bit 5 Bit4 Pin 9 Pin 8 Pin 7 Pin 6 The instruction captures data...

Page 416: ...rocessor with data present on the pins associated with the output to hex 3BC This should normally reflect the exact value that was last written to hex 3BC If an external device should be driving data...

Page 417: ...a last written to hex 3BE in the same bit positions Notice that data bits 0 2 are not included If external drivers are dotted to these pins that data will be ORed with data applied to the pins by the...

Page 418: ...16 Monochrome Adapter...

Page 419: ...Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Acknowledge Busy P End out of paper Select Auto Feed Error Initialize Printer Select Input Ground Connector Specifications Adapter Pin Number 1 2 3 4 5 6 7...

Page 420: ...18 Monochrome Adapter...

Page 421: ...AI5 AI4 AI3 AI2 A7 8HT2 4 A8 8HT2 4 A9 8HT2 4 JQ AID 8HT2 All 8HT2 AI5 8HT 4 AI6 8HT4 a A17 SHT4 AI8 SHT4 AI9 8HT4 rI1 All AEN 8HT4 6 OECOUPLING CAPACITORS 1 1 B30 B03 B03 B29 B29 BOI I 0 047 F BID B3...

Page 422: ...__ I I 4 1 I I 3 18 IY f4 RMA8 I I O CC7 i 2A 2Y fl RMA9 I I I H f 11 UI6 I _H f I l J I 3Y 74LSI39 I ____ __________I J 3 4Bl G4 lL 2 I jvl1 4 I r _______ _ H t H 1HT Jf IS 1 lG UTm I AO _ 3 IB I 7 A...

Page 423: ...r7 4L SO 74LS74 10 p LK 01 9 _ TEST OSC 19 lYf 7 i ____ 2 U 3 h 2 OCLK 0 5 r_ 2q 1 LR U4 __lalt_ _ __ ___ ___ 7 _ l i 1 8 C3 12 74LSOO I I 5V 1 CLR U4 l I I 3 7418125 SHT7 HRES A U24 131 U25 11 4 PR 0...

Page 424: ...YNC OLY SHT 7 LVIOEO r E SHT3 j 1 9 6845E SHT2 r I ll LK Q 1274LSOO r _ _ _ _ _ _ _ _ _ _ _ 1113 U5 3rl I GRPOCO SHT8 5 U4V l6 _ 6845CS SHT2 r6 4LS04 L J GI 1 5_ _ _ _ _ _ _ _ _ _ _ _ 5 6 6845CS SHT3...

Page 425: ...1 SDoTS ISHT31 Q5 3 Q Q f Q e D ISHT71 SERDATA ISHT 31 JUMPER C ISHT 21 RA3 RA2 CS RAI 1 D ISHT 2 RAo 7 6 AT2X 7 8 9 AT3X 8 9 13 U31 12 AT4X 13 14 15 AT5X 14 U30 17 16 AT6X 17 18 19 AT7X 18 19 1 ClR I...

Page 426: ...3 t7 807 rd2 3 2 L lrr 800 SUI B02 B03 14 15 B04 1 I 16 805 18 19 B06 I Ift K B07 18 74L 44 2 tr 800 L 801 12 8 802 9 11 803 7 13 B04 1 15 805 3 17 806 IG B07 I 3 14lliL4 2 J ti 800 L BOI 802 B03 14 1...

Page 427: ...2 PR U45 1 _ 3 l DClK 5 4 74lS08 I PIN 3 PIN 4 PIN 5 HIGHLIGHT PIN6 4 PIN I 1 l PIN2 I lClR 0 U3 6 74lS244 C3 i_ 120pF _______1 5 _ VIDEO PIN7 ______ 13 l I I 7 _ _ _ _ _ _ _ _ _ HORIZ DRIVE PIN 8 I I...

Page 428: ...CAPACITORS PROVIDED ON OUTPUTS FOR FILTERING NOT USED ON PRESENT CARD ASSEMBLY RPI I Cx Monochrome Display Adapter Sheet 8 of 10 RPI DD22JJI DATA 0 DATA I ATA2 DATA 3 0 DATA 5 DATA 7 STROBE AUTO FDXT...

Page 429: ...SN20 9844 March 1987 to 75X0232 M o o 0 Q Q r I I h 1nI jj 1111 r I Q c ca C ca Q t C 01 1 NI I I I I c coacc c ccc I b f 11 N B N I01 1 1 I a a a a 0 CI Go i I I I I I a iii z H 8 Q E o r CJ o c o E...

Page 430: ...minal Ready Request to Send Ring Indicate External No Connection Device Receive Data Data Set Ready Clear to Send Data Carrier Signal Ground 28 Monochrome Adapter 1 2 3 4 5 6 7 8 ___ 9 10 4 Port Async...

Page 431: ..._ Serial Parallel Adapter Personal Computer Hardware Reference Library...

Page 432: ...ii...

Page 433: ...ontents IBM Personal Computer AT Serial Parallel Adapter 1 Serial Portion of the Adapter 1 Programmable Baud Rate Generator 17 Parallel Portion of the Adapter 19 Specifications 24 Logic Diagrams 26 ii...

Page 434: ...Notes iv...

Page 435: ...rate generator allows operation from 50 baud to 9600 baud Five six seven and eight bit characters with 1 1 5 or 2 stop bits are supported A prioritized interrupt system controls transmit receive error...

Page 436: ...bits to or from a serial data stream Provides full double buffering which eliminates the need for precise synchronization Provides a programmable baud rate generator Provides modem controls CTS RTS DS...

Page 437: ...irst bit to be sent or received The controller automatically inserts the start bit the correct parity bit if programmed to do so and the stop bit 1 1 5 or 2 depending on the command in the line contro...

Page 438: ...1 DDSR of the modem status register indicates if the I DSR I input has changed since the previous reading Note Whenever the DSR bit of the modem status register changes state an interrupt is generate...

Page 439: ...gnal is set inactive upon a master reset operation Request to Send RTS Pin 32 When active informs the modem or data set that the controller is ready to send data The I _ RTS I output signal can be set...

Page 440: ...read XF8 Divisor Latch LSB 1 XF9 Divisor Latch MSB 1 XF9 Interrupt Enable Register 0 XFA Interrupt Identification Register XFB Line Control Register XFC Modem Control Register XFD Line Status Registe...

Page 441: ...LSD Hex XF8 Divisor Latch leISt Slgnlflclnt Bit blx XF81 Bit 7 6 543210 mtO Bit 1 Bit 2 Bit3 Bit4 Bit 5 Bit6 Bit 7 Divisor Latch Least Significant Bit Information about this register may be found unde...

Page 442: ...I and the active I INTRPT I output from the chip All other system functions operate normally including the setting of the line status and modem status registers Interrupt Enlble Register hex XF91 Bit...

Page 443: ...stops the pending interrupt with the highest priority and no other interrupts are acknowledged until the processor services that particular interrupt Interrupt Identlflcltlon Register Ihex XFA Bit 7...

Page 444: ...f source of in Holding Register terrupt or writing Register Empty into the THR Empty 0 0 0 Fourth Modem Clear to Send Reading the Modem Status or Status Register Data Set Ready or Ring Indicator or Re...

Page 445: ...l 0 one stop bit is generated or checked in the data sent or received If bit 2 is logical 1 when a 5 bit word length is selected through bits 0 and 1 1 1 2 stop bits are generated or checked If bit 2...

Page 446: ...r activity The set break is disabled by setting bit 6 to logical O This feature enables the microprocessor to select a specific terminal in a computer communications system Bit 7 This bit is the divis...

Page 447: ...bit 4 is set to logical 1 the following occur the transmitter serial output SOUT is set to the active state the receiver serial input SIN is disconnected the output of the transmitter shift register...

Page 448: ...Ihex XFDI Bit 7 6 5 4 3 2 1 0 o m Y Overrun Error Parity Error Framing Error Break Interrupt Transmitter Holding Register Empty Tx Shift Register Empty 0 Line Status Register Bit 0 This bit is the re...

Page 449: ...rt bit data bits parity stop bits Note Bits 1 through 4 are error conditions that produce a receiver line status interrupt whenever any of the corresponding conditions are detected Bit 5 This bit is t...

Page 450: ...ect Modem Status Register Bit 0 This bit is the delta c1ear to send DCTS indicator It indicates the I CTS I input to the chip has changed state since the last time it was read by the processor Bit 1 T...

Page 451: ...rrier detect DCD input If bit 4 of the MCR is set to a logical 1 this bit is equivalent to OUT 2 of the MCR Programmable Baud Rate Generator The controller has a programmable baud rate generator that...

Page 452: ...for the serial port in a communications environment External Device Carrier Detect Receive Data Transmit Data Data Terminal Ready Signal Ground Data Set Ready Request To Send Clear To Send Ring Indica...

Page 453: ...evices that accept eight bits of parallel data at standard TTL levels The rear of the adapter has a 25 pin D shell connector This port may be addressed as either parallel port 1 or 2 The port address...

Page 454: ...the adapter to connect to a parallel printer Hexidecimal addresses in this section begin with an X which is replaced with a 3 to indicate port 1 or a 2 to indicate port 2 Data Latch Hex X78 X7C Writi...

Page 455: ...e Printer Status Address X79 X7D Printer status is stored at this address to be read by the microprocessor The following are bit definitions for this byte Bit 7 BUSY When this signal is active the pri...

Page 456: ...Bit 4 SLCT A 1 means the printer is selected Bit 3 Error A 0 means the printer has encountered an error condition Bit 2 Unused Bit 1 Unused Bit 0 Unused 22 Serial Parallel Adapter...

Page 457: ...heir pin assignments Typical printer input signals also are shown Elt rna Device I Strobe Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 ACK 8USY PE SLCT AUTO...

Page 458: ...t voltage 0 4 Vdc Max Parallel Control Sink current 24 rnA Max Source current 15 rnA Max High level output voltage 2 0 Vdc Min Low level output voltage 0 5 Vdc Max Parallel Processor Interface except...

Page 459: ...F b IS 7 g UI4 1 1 3 0 14 1 14 01 II IBI OZ I Ib 17 J I B IO NO M P Hel NC4 W N C NCZ NC N C LS Z4 ABII I I DZ I gH UI7 07 8 A B 12 UI b LS04 i Ulb b LSQ4 1 Z J4 TO T CB TCo CIO 7UF I v 047uF 047uF Se...

Page 460: ...20 2Q g i I IA3 In I BOZ 7 70 7Q II 3 14 I ZA3 ZB B03 r i O Q 12 7 10 OATA II 2AI ZVI 9 BO V I D I Q 12 g i i 13 ZAZ ZVZ 7 BO V BOI 730 3Q I I II IA2 IYZ II BOI B07 4D Q 9 B q DATA 7 B lA4 IY IZ B07...

Page 461: ...HIe 20 DTR 11 Hie Hie Hie U2 7 o V ml12 W U2 SHT1 BIeR DlSTR m SOOTI I A2 26 SHT 1 ENABLE SER 0 V 11 eSI U2 12 eso Rl on 14 m Hie XTAL 2 C Vo II U2 tr Hie RECE VE DATA Serial Printer Adapter Sheet 3 o...

Page 462: ...Notes 28 Serial Parallel Adapter...

Page 463: ...HNICAL NEWSLETTER for the IBM RT PC Hardware Technical Reference Copyright International Business Machines Corporation 1986 SN20 9844 75X1073 June 1987 Copyright IBM Corp 1987 OVER 84X0875 Printed in...

Page 464: ...L pages 6 17 through 6 20 8 Replace pages 6 47 through 6 62 with new TNL pages 6 48 through 6 64 9 Replace Section 7 System IPL ROM with new TNL Section 7 System IPL ROM 10 Replace Section 8 System Co...

Page 465: ...of the Monochrome Display and Printer Adapter in Volume II with new TNL pages 27 and 28 New divider tabs are provided for Volumes II and III You may want to organize the information using these divid...

Page 466: ...Machines Corporation 1987 All Rights Reserved Printed in the United States of America References in this publication to IBM products or services do not imply that IBM intends to make them available o...

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