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IBM PowerPC 604, User Manual

The IBM PowerPC 604 is a high-performance processor designed for advanced computing tasks. For detailed instructions on how to maximize its capabilities, download the free user manual from manualshive.com. This comprehensive manual offers in-depth guidance on utilizing the PowerPC 604 to its full potential.

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Summary of Contents for PowerPC 604

Page 1: ......

Page 2: ...Bus Interface Unit Operation Exceptions Memory Management Instruction Timing Signal Descriptions System Interface Operation Performance Monitor PowerPC Instruction Set Listings Invalid Instruction Fo...

Page 3: ...e and Bus Interface Unit Operation Exceptions Memory Management Instruction Timing Signal Descriptions System Interface Operation Performance Monitor PowerPC Instruction Set Listings B Invalid Instruc...

Page 4: ...MPR604UMU 01 MPC604UM AD 11 94 PowerPC 604 RISC Microprocessor User s Manual IBM Microelectronics...

Page 5: ...or Obligation for damages ol any kind arising out ol the application or use ol these materials Any warranty or other Obligations as to the products described herein shall be undertaken solelyby Iha ma...

Page 6: ...PowerPC 604 Microprocessor Features 1 2 PowerPC 604 Microprocessor Hardware Implementation 1 7 Instruction Flow 1 8 Fetch Unit 1 8 Decode Dispatch Unit 1 9 Branch Processing Unit BPU 1 9 Completion Un...

Page 7: ...5 Calculating Effective Addresses 1 27 Exception Model 1 28 Instruction Timing 1 33 Power Management Nap Mode 1 35 Performance Monitor 1 35 Chapter 2 PowerPC 604 Processor Programming Model The PowerP...

Page 8: ...al Instructions 2 28 Integer Rotate and Shift Instructions 2 29 Floating Point Instructions 2 30 Floating Point Arithmetic Instructions 2 30 Floating Point Multiply Add Instructions 2 31 Floating Poin...

Page 9: ...r 3 Cache and Bus Interface Unit Operation 3 1 Data Cache Organization 3 3 3 2 Instruction Cache Organization 3 4 3 3 MMUs Bus Interface Unit 3 5 3 4 Memory Coherency Actions 3 8 3 4 1 604 Initiated L...

Page 10: ...5 2 4 5 2 1 4 5 2 2 4 5 3 4 5 4 4 5 5 4 5 6 4 5 7 4 5 8 4 5 9 4 5 10 4 5 11 4 5 12 Contents Chapter 4 Exceptions PowerPC 604 Microprocessor Exceptions 4 2 Exception Recognition and Priorities 4 5 Exce...

Page 11: ...ress Translation Selection 5 14 Selection of Page Address Translation 5 16 Selection of Direct Store Interface Address Translation 5 16 MMU Exceptions Summary 5 16 MMU Instructions and Register Summar...

Page 12: ...Memory Operations 6 15 Write Back Mode 6 15 Write Through Mode 6 16 Cache Inhibited Mode 6 16 Timing Considerations 6 17 General Instruction Flow 6 17 Instruction Fetch Timing 6 18 Cache Hit Timing Ex...

Page 13: ...iptions 7 3 Address Bus Arbitration Signals 7 3 Bus Request BR Output 7 4 Bus Grant BG lnput 7 4 Address Bus Busy ABB 7 5 Address Bus Busy ABB Output 7 5 Address Bus Busy ABB Input 7 5 Address Transfe...

Page 14: ...l Output 7 15 Address Transfer Termination Signals 7 16 Address Acknowledge AACK Input 7 16 Address Retry ARTRY 7 16 Address Retry ARTRY Output 7 16 Address Retry ARTRY lnput 7 17 Shared SHD 7 17 Shar...

Page 15: ...System Clock SYSCLK lnput 7 30 Test Clock CLK_OUT Output 7 31 Analog VDD AVDD lnput 7 31 PLL Configuration PLL_CFGO PLL_CFG3 Input 7 31 Chapter 8 System Interface Operation PowerPC 604 Microprocessor...

Page 16: ...on Protocol Details 8 42 Packet 0 8 43 Packet 1 8 44 1 0 Reply Operations 8 44 Direct Store Operation Timing 8 46 Optional Bus Configuration 8 48 Fast L2 Data Streaming Mode 8 48 Fast L2 Data Streamin...

Page 17: ...ervention 9 10 Warnings 9 11 Nonthreshold Events 9 11 Appendix A PowerPC Instruction Set Listings A 1 Instructions Sorted by Mnemonic A 1 A 2 Instructions Sorted by Opcode A 10 A 3 Instructions Groupe...

Page 18: ...WIM 001 3 14 Machine Status Save Restore Register 0 4 6 Machine Status Save Restore Register 1 4 6 Machine State Register MSR 4 7 MMU Conceptual Block Diagram 32 Bit Implementations 5 6 PowerPC 604 Mi...

Page 19: ...sor Bus for a Single Beat Transfer 8 6 Address Bus Arbitration 8 10 Address Bus Arbitration Showing Bus Parking 8 11 Address Bus Transfer 8 12 Snooped Address Cycle with ARTRY 8 19 Data Bus Arbitratio...

Page 20: ...tructions 2 26 Integer Compare Instructions 2 28 Integer Logical Instructions 2 28 Integer Rotate Instructions 2 29 Integer Shift Instructions 2 30 Floating Point Arithmetic Instructions 2 30 Floating...

Page 21: ...onse to Bus Transactions 3 20 3 5 604 Bus Operations Initiated by Cache Control Instructions 3 23 3 6 Cache Actions 3 24 4 1 Exception Classifications 4 3 4 2 Exceptions and Conditions Overview 4 3 4...

Page 22: ...9 4 PMC2 Events MMCRO 26 31 Select Encoding 9 5 MMCRO Bit Settings 9 7 Complete Instruction List Sorted by Mnemonic A 1 Complete Instruction List Sorted by Opcode A 10 Integer Arithmetic Instructions...

Page 23: ...structions A 27 A 31 I Form A 28 A 32 B Form A 28 A 33 SC Form A 28 A 34 D Form A 28 A 35 DS Form A 30 A 36 X Form A 30 A 37 XL Form A 34 A 38 XFX Form A 35 A 39 XFL Form A 35 A 40 XS Form A 36 A 41 X...

Page 24: ...User s Manual summarizes features of the 604 that are not defined by the architecture This document and The Programming Environments Manual distinguishes between the three levels or programming envir...

Page 25: ...ch chapters may include informationfrom multiple levels ofthe architecture For example the discussion of the cache model uses information from both the VEA and theOEA The information in this book is s...

Page 26: ...form Appendix B Invalid Instruction Forms describes how invalid instructions are treated by the 604 This manual also includes a glossary and an index In this document the terms PowerPC 604 Microproces...

Page 27: ...en they are low and negated when they are high Signals that are not active low such as APO AP3 address bus parity signals and TTO TT4 transfer type signals are referred to as asserted when they are hi...

Page 28: ...dress space register BAT Block address translation BIST Buitt in seH test BIU Bus interface unit BHT Branch history table BPU Branch processing unit BTAC Branch target address cache BUID Bus unit ID C...

Page 29: ...oup L2 Secondary cache LR Unk register LAU Least recently used LSB Least slgnHlcant byte lsb Least signHlcant bit LSU Loadlstore unit MCIU Multiple cycle Integer unit MESI ModHied exclusive sharedlinv...

Page 30: ...anslation SIA Sampled instruction address register SIMM Signed immediate value SLB Segment look aside buffer SPR Special purpose register SPRGn Registers available for general purposes SR Segment regi...

Page 31: ...ddress Physical address Relocation Translation Storage locations Memory Storage the act of Access For a detailed discussion ol how the terms interrupt and exception are used in this document see the i...

Page 32: ...briefly how those units interact The 604 is an implementation of the PowerPCTM family ofreduced instruction set computer RISC microprocessors The 604 implements the PowerPC ArchitectureTM as it is sp...

Page 33: ...variable sized block translation The TLBs and the cache use least recently used LRU replacement algorithms The 604 has a 64 bitexternal data bus and a 32 bit address bus The 604 interface protocol al...

Page 34: ...er Fetcher Instruction Queue 8 word INSTRUCTION UNIT 64Bit 128Bit Dispatch Unit I BHT I FPR File 128Bit IMMU ISR 11 IBAT I I1TLB I Array 128Bit 32Bit B II 64Bit DMMU Tags 16 Kbyte I Cache Store Queue...

Page 35: ...ute in the MCIU take multiple cycles to execute Each SCIU has a two entry reservation station to minimize stalls The MCIU has a two entry reservation station and provides early exit three cycles for 1...

Page 36: ...struction and data caches Harvard architecture 16 Kbyte four way set associative instruction and data caches LRU replacement algorithm 32 byte eight word cache block size Physically indexed physical t...

Page 37: ...ions Multiprocessing support features include the following Hardware enforced four state cache coherency protocol MESI for data cache Bits are provided in the instructioncache to indicate only whether...

Page 38: ...tribute to the improved efficiency in instruction execution and more clearly indicating the relationships between execution units and their associated register files Branch Corraction Fetch Unit Dispa...

Page 39: ...instruction queue by accessing the on chip instruction cache Typically the fetch unit continues fetching sequentially as many as four instructions at a time The address ofthe next instruction to be fe...

Page 40: ...ion unit A reorder buffer ROB entry is allocated for each instruction and dependency checking is done between the instructions in the dispatch queue The rename buffers are searched for the operands as...

Page 41: ...ervation station execution can begin The completion unit does not transfer instruction results from the rename registers to the registers lintil any speculative branch conditions preceding it in the c...

Page 42: ...are written to the floating point rename buffers and to the reservation stations and are made available to subsequent instructions Instructions are executed from each reservation station in dispatch...

Page 43: ...data structure that defines the mapping between virtual page numbers and physical page numbers The page table size is a power of 2 and its starting address is a multiple of its size Address translati...

Page 44: ...cycle the data cache provides double word access to the LSU The data cache tags are dual ported so the process of snooping does not affect other transactions on the systeminterface Ifa snoop hit occu...

Page 45: ...ace Unit BIU The 604 provides a versatile bus interface that allows a wide variety of system design options The interface includes a 72 bit data bus 64 bits of data and 8 bits of parity a 36 bit addre...

Page 46: ...n the line are fetched later The critical double word as well as other words in the cache block are forwarded to the fetcher or to the LSU before they are written to the cache Memory accesses canoccur...

Page 47: ...ts in one bus clock cycle Data transfers occur in either single beat transactions or four beat burst transactions Asingle beat transaction transfers as much as 64 bits Single beat transactions are cau...

Page 48: ...gnals These signals are used to interrupt and under various conditions to reset the processor Processor state signals These two signals are used to set the reservation coherency bit and set the size o...

Page 49: ...STATUS 1PROCESSOR JCONFIGURATION c s __ JTAGICOP J INTERFACE Figure 1 5 PowerPC 604 Microprocessor Signal Groups 1 2 6 Clocking The 604 has a phase locked loop PLL that generates the internal processo...

Page 50: ...e base user level instruction set user level registers data types memory conventions and the memory and programming models seen by application programmers Note that the PowerPC architecture refers to...

Page 51: ...o register operations for most computational insttuctions Source operands for these insttuctions are accessed from the registers or are provided as immediate values embedded in the insttuction opcode...

Page 52: ...T2U DBAT2L DBAT3U DBAT3L SPR536 SPR537 SPR538 SPR539 SPR540 SPR541 SPR542 SPR543 Performance Monitor Segment Registers SRO SRI i SR15 SDR1 SDR1 ISPR25 Monitor Sampled Data Counters1 Monitor Control1 I...

Page 53: ...provide a way to buffer data intended for the GPRs reducing stalls when the results ofone instruction are required by a subsequent instruction The use of rename buffers is not defined by the PowerPC a...

Page 54: ...status configuring the processor and performing special operations Some SPRs are accessed implicitly as part of executing certain instructions All SPRs can be accessed by using the move to from SPR i...

Page 55: ...gister Theregisters are implemented as a64 bitcounter with the least significantbitbeing the most frequently incremented The PowerPC architecture defines that the time base frequency be provided as a...

Page 56: ...types permitting efficient decoding to occur in parallel with operand accesses This fixed instruction length and consistent format greatly simplifies instruction pipelining 1 3 3 1 1 Instruction Set T...

Page 57: ...ns trap instructions and other instructions that affect the instruction flow Branch and trap instructions System call and rfi instructions Condition register logical instructions Synchronization instr...

Page 58: ...et of 32 GPRs It also provides for word and double word operand loads and stores between memory and a set of 32 FPRs Computational instructions do not modify memory To use a memory operand in a comput...

Page 59: ...a particular PowerPC processor may recognize exception conditions out of order exceptions are handled strictly in order When an instruction caused exception is recognized any unexecuted instructions t...

Page 60: ...and any exceptions associated with those instructions complete execution These exceptions are maskable by setting MSR EE Asynchronous nonrnaskable There are two nonrnaskable asynchronous exceptions t...

Page 61: ...using Conditions Type hex Reserved 00000 System reset 00100 Asystem reset is caused by the assertion of either the soft reset or hard reset signal Machine check 00200 A machine check exception is sign...

Page 62: ...ess cannot be translated That is there is a page fault for this portion of the translation so an ISi exception must be taken to retrieve the translation from a storage device such as a hard disk drive...

Page 63: ...rap A trap type program exception is generated when any of the conditions specified in a trap instruction is met Floating point 00800 Afloating point unavailable exception Is caused by an attempt to e...

Page 64: ...de intem1pt which is described in Section 1 4 Power Management Nap Mode Reserved 01500 02FFF Reserved implementation specHic exceptions These are not implemented in the604 1 3 5 Instruction Timing As...

Page 65: ...the results into the appropriate rename bufferentry andnotifies the completionstage thatthe instruction has finished execution The execution unit reports any internal exceptions to the completion sta...

Page 66: ...nal to be negated Nap mode is exited clocks resume and MSR POW cleared when any asynchronous interrupt is detected 1 5 Performance Monitor The 604 incorporates a performance monitor facility that syst...

Page 67: ...2 PowerPC Register Set in The Programming Environments Manual Note that registers are defined at all three levels of the PowerPC architecture user instruction set architecture VISA virtual environment...

Page 68: ...t of the execution of an instruction Some registers are accessed both explicitly and implicitly The number to the right of the special purpose registers SPRs indicates the number that is used in the s...

Page 69: ...40 DBAT2L SPR541 DBAT3U SPR542 DBAT3L SPR543 Segment Registers SRO SR1 I SR15 SDR1 SDR1 lsPR25 Performance Monitor Performance Monitor Mode Control Sampled Data Monitor Counters1 Register 01 Instructi...

Page 70: ...Environments Manual Implementation Note The PowerPC architecture indicates that in some implementations the Move to ConditionRegister Fields mtcrt instructionmay performmore slowly when only aportion...

Page 71: ...Aintroduces the time base facility TB a 64 bit structure that maintains and operates an interval timer The TB consists oftwo 32 bitregisters time baseupper TBU and time base lower TBL Note that the ti...

Page 72: ...and IBATOL IBAT3L and four pairs of data BATs DBATOU DBAT3U and DBATOL DBAT3L See Figure 2 1 for a list of the SPR numbers for the BAT registers For more information see BAT Registers in Chapter 2 Po...

Page 73: ...time base registers can be accessed by bothuser and supervisor level instructions See T IDle BaseFacility TB OEA in Chapter 2 PowerPC Register Set of The Programming Environments Manual for more infor...

Page 74: ...ter 0 MMCRO This is used for enabling various performance monitoring interrupt conditions and establishes the function of the cpunters Sampled instruction address and sampled data address registers SI...

Page 75: ...instruction address breakpoint exception is executed before the exception handler is invoked For more information about the IABR exception see Section 4 5 14 Instruction Address Breakpoint Exception O...

Page 76: ...or does not cause a machine check exception 1 Enables the entry Into a machine check exception based on the detection of an address parity error Note that the machine check exception is further affect...

Page 77: ...time Accesses to the cache from the bus are signaled as a miss while the invafidate all operation is in progress The bit is deared when the invalidation operation begins usually the cyde immediately f...

Page 78: ...rs can be changed by hardware 1 If MSR PM is cleared the PMCn counters are net changed by hardware 5 ENINT Enable performance monitoring interrupt signaling 0 Interrupt signaling is disabled 1 Interru...

Page 79: ...m for counting after a certain condition occurs or after a preset time has elapsed It can be used to support getting the count associated with a specific event 19 25 PMC1SELECT PMC1 input selector 128...

Page 80: ...eady for execution 000 1001 Number of load deache misses that exceeded the threshold value with lateral L2 intervention 000 1010 Number of store deache misses that exceeded the threshold value with la...

Page 81: ...0000 Instructions dispatched to the branch unit 01 0001 Instructions dispatched to the SCIUO 01 0010 Number cl loads completed 01 0011 Instructions dispatched to the MCIU 01 0100 Number cl snoop hit o...

Page 82: ...The SDA can be read by using the mfspr instruction and written to by using the mtspr instruction SPR 959 2 2 Operand Conventions This section describes the operand conventions as they are represented...

Page 83: ...length is implicit for each instruction 2 2 3 Alignment and Misaligned Accesses The operand of a single register memory access instruction has a natural alignment boundary equal to the operand length...

Page 84: ...malized Single denormalized Normalize B and C ZeroBandC Double denormalized Double denormalized Single denormalized Normalized or zero Single denormalized Normalize A and C Zero A and C Double denorma...

Page 85: ...nt location and alignment of operands in memory may affect the relative performance ofmemory accesses The best performance is guaranteed if memory operands are aligned on natural boundaries To obtain...

Page 86: ...ptional External Control Instructions Note that this grouping of instructions does not necessarily indicate the execution unit that processes a particular instruction or group ofinstructions This info...

Page 87: ...bits in reserved fields the results on execution can be said to be boundedly undefined If a user level program executes the incorrectly codedinstruction the resulting undefined results are bounded in...

Page 88: ...ns Sorted by Opcode and Section 2 3 1 4 Reserved Instruction Class Notice that extended opcodes for instructions defined only for 64 bit implementations are illegal in 32 bit implementations and vice...

Page 89: ...lating effective addresses as defined by the PowerPC architecture for 32 bit implementations For more detailed information see Conventions in Chapter 4 Addressing Modes and Instruction Set Summary of...

Page 90: ...it 0 is ignored Load and store operations have three categories of effective address generation Register indirect with immediate index mode Register indirect with index mode Register indirect mode Ref...

Page 91: ...invoked Exceptions can be caused directly by the execution of an insuuction as follows An attempt to execute an illegal insuuction causes the illegal insuuction program exception handler to be invoke...

Page 92: ...ser level cache control synchronization and time base instructions user level registers programming model data types and addressing modes This section discusses the instructions defined in the UISA 2...

Page 93: ...vwuo dlvwuo rD rA rB Although there is no Subtract Immediate instruction its effect can be achieved by using an addi instruction with the immediate operand negated Simplified mnemonics are provided th...

Page 94: ...ber For information on simplified mnemonics for the integer compare instructions see Appendix F Simplified Mnemonics in The Programming Environments Manual 2 3 4 1 3 Integer Logical Instructions The l...

Page 95: ...egister The result ofthe rotation is either inserted into the target register under control ofa mask ifa mask bit is 1 the associated bit of the rotated data is placed into the target register and if...

Page 96: ...ns See Section 2 3 4 3 Load and Store Instructions for information about floating point loads and stores The PowerPC architecture supports a floating point system as defined in the IEEE 754 standard b...

Page 97: ...multiply add instructions are summarized in Table 2 15 Table 2 15 Floatlng Polnt Multlply Add Instructions Name Mnemonic Operand Syntax Floating Multiply Add Double Precision fmadd lmadd frD frA lrC f...

Page 98: ...Re bit set can cause an illegal instruction program exception or produce a boundedly undefinedresult In the 604 crfD should be treated as undefined 2 3 4 2 5 Floating Point Status and Control Register...

Page 99: ...g Integer load instructions Integer store instructions Integer load and store with byte reverse instructions Integer load and store multiple instructions Floating point load instructions Floating poin...

Page 100: ...lue The floating point load and store indexed instructions lfsx lfsux lfdx lfdux stfsx stfsux stfdx stfdux are also invalid when the Re bit is one In the 604 executing one of these invalid instruction...

Page 101: ...n Notes The following notes describe the 604 implementation of integer load instructions In the PowerPC architecture the Re bit must be zero for almost all load and store instructions Ifthe Re bit is...

Page 102: ...r integer store instructions the contents of rS are stored into the byte half word word or double word in memory addressed by the EA effective address Many store instructions have an update form in wh...

Page 103: ...d value For the store with update instructions stbu stbux sthu sthux stwu stwux stfsu stfsux stfdu stfdux when rA 0 the instruction form is considered invalid In this case the 604 sets GPRO to an unde...

Page 104: ...oss a page boundary However a OSI exception may occur when the boundary is crossed for example if a protection violation occurs on the new page Executing an lmw instruction in which rA is in the range...

Page 105: ...ons In other PowerPC implementations operating with little endian byte order execution of a load or string instruction causes the system alignment error handler to be invoked see Section 3 2 2 Byte Or...

Page 106: ...operation is not word aligned The 604 executes store string operations to cacheable memory at arate of one cycle per word if they are word aligned Cacheable store string operations that are not word...

Page 107: ...th Update lfdu frD d rA Load Floating Point Double with Update Indexed lfdux frD rA rB 2 3 4 3 9 Floating Point Store Instructions This section describes floating point store instructions There are th...

Page 108: ...e 2 27 shows the conversions made by the LSU when performing a Store Floating Point Single instruction Table 2 27 Store Floatlng Polnt Slngle Behavior FPR Precision Data Type Action Single Normalized...

Page 109: ...on the value to be stored Because of how floating point numbers are implemented in the 604 there is also a case when execution of a store floating point double stfd stfdu stfdx stfdux instruction can...

Page 110: ...e of bits in the CR Whenever the CR bits resolve the branch direction is either marked as correct or mispredicted Correcting a mispredicted branch requires that the 604 flush speculatively executed in...

Page 111: ...Register OR with Complement crorc crbD crbA crbB Move Condition Register Field mcrf crfD crfS Note that if the LR update option is enabled for any of these instructions the PowerPC architecture define...

Page 112: ...g to the condition register Table 2 33 Move to from Condition Register Instructions Name Mnemonic Operand Syntax Move to Condition Register Fields mtcrf CRM rS Move to Condition Register from XER mcrx...

Page 113: ...Purpose Register mtspr SPR rS Move from Special Purpose Register mfspr rD SPR 2 3 4 7 Memory Synchronization lnstructions UISA Memory synchronization instructions control the order in which memory ope...

Page 114: ...ructions Ifthe Re bit is one the instruction form is invalid These include the sync and lwarx instructions In the 604 executing one ofthese invalid instructionforms causes CRO to be set to anundefined...

Page 115: ...is enabled by assertion of the timebase enable TBE input signal 2 3 5 2 Memory Synchronization Instructions VEA Memory synchronization instructions control the order in which memory operations are com...

Page 116: ...management instructions defined by the VEA See 2 3 6 3 Memory Control Instructions OEA for information about supervisor level cache segment register manipulation and translation lookaside buffer mana...

Page 117: ...es of the block that may reside in their cache this Is the kiU operation on the bus After it has exclusive access the 604 writes all zeros Into the cache block If the 604 already has exclusive access...

Page 118: ...rS rA rB The eciwx and ecowx instructions cause an aligmnent exception if they are not word aligned 2 3 6 PowerPC OEA Instructions The PowerPC operating environment architecture OEA includes the struc...

Page 119: ...000 MMCRO 953 11101 11001 PMC1 954 11101 11010 PMC2 955 11101 11011 SIA 959 11101 11111 SDA 1010 11111 10010 IABR 1023 11111 11111 PIR 1Note that the order of the two 5 bit halves of the SPR number Is...

Page 120: ...4 Cache Management Supervisor Level Instruction Name Mnemonic Operand Syntax Implementation Notes Data debI rA rB The EA is computed translated and checked for protection Cache violations as defined i...

Page 121: ...ns Name Mnemonic Operand Syntax Move to Segment Register mtsr SR rS Move to Segment Register Indirect mtsrln rS rB Move from Segment Register mfsr rD SR Move from Segment Register Indirect mfsrln rD r...

Page 122: ...essors on the bus accept the operation AFffFIV is not asserted Once accepted the TLB invalidation is performed unless the processor is executing a multiple string instruction in which case the TLB inv...

Page 123: ...ding asetofalternative mnemonics is providedfor some frequently usedoperations suchas no op loadimmediate loadaddress moveregister and complementregister Programs written to be portable across the var...

Page 124: ...oherency at the page and block level as defined by the PowerPC architecture The caches use a least recently used LRU replacement policy The 604 cache implementation has the following characteristics S...

Page 125: ...the cache Writes of cache blocks by the 604 for a copy back operation always present the first address of the block and transfer data beginning at the start ofthe block However this does not preclude...

Page 126: ...s PA 0 19 PA 0 31 Cache Tags MMU Bus Interface Unit BIU Figure 3 2 cache Integration 3 1 Data Cache Organization Load Store Unit LSU Data 0 63 Data Cache 16 Kbyte Four Way SetAssociative Data 0 63 As...

Page 127: ...ysically indexed The organization of the instruction cache shown in Figure 3 1 is identical to that of the data cache Each cache block contains eight contiguous words from memory that are loaded from...

Page 128: ...re they are written to the cache The bus can be run at lx 2 3x l 2x or l 3x the speed of the processor The programmable on chip phase locked loop PLL generates the necessary processor clocks from the...

Page 129: ...For a line fill operation the line fill address from either the instruction or data cache is kept in the memory address queue until the address can be sent out in an address tenure After the address...

Page 130: ...ata is kept in the write bufferuntil bothcan be sent out in a write transaction Similarly for copy back operations the address is kept in the copy back address queue and the data is kept in the copy b...

Page 131: ...ovide an overview of the behavior of the 604 with respect to load and store operations Table 3 1 does not include noncacheable cases The first three cases load when the cache block is marked I also in...

Page 132: ...resolved before memory accesses that miss in the cache are forwarded onto the memory queue for arbitration onto the bus In addition although subsequentmemory accesses can address the cache full cohere...

Page 133: ...if multiple processors are performing these types of memory operations to the same addresses without properly synchronizing one another through the use of the lwarx stwcx instructions the results of...

Page 134: ...n the cache and in at least one other cache This blockis always consistent with system memory That is the shared state Is shared unmodilled there is no shared modilled state Invalid I This state Indic...

Page 135: ...th the snooping operation The instructionprocessing is affectedonly when the snoop conttol logic detects a situation where a snoop push of modified data is required to maintain memory coherency M E 3...

Page 136: ...defines two of the possible eight decodings of these bits to be unsupported WIM 110 or 111 Note that software must exercise care with respect to the use of these bits if coherent memory support is des...

Page 137: ...e following coherency paradoxes can be encountered within a single processor Load or store operations to a page with WIM ObOll and a cache hit occurs Caching was supposed to be inhibited for this page...

Page 138: ...These are described as follows Bit 1 Enable cache parity checking Enables a machine check exception based on the detection of a cache parity error If this bit is cleared cache parity errors are ignor...

Page 139: ...he write to the register Any accesses to e cache from the bus are signaled as a miss during the time that the invalidate all operation is in progress The HIDO register can be accessed with the mtspr a...

Page 140: ...execution of the debt instruction affects the state of the TLB and cache LRU bits as defined by the LRU algorithm 3 8 4 Data Cache Block Set to Zero dcbz As defined in the VEA when the debz instructi...

Page 141: ...9 Basic Cache Operations This section describes operations that can occur to the cache and how these operations are implemented in the 604 3 9 1 Cache Reloads A cache block is reloaded after a read m...

Page 142: ...the write on the system interface or the lwarx stwcx instructions The 604 drives two snoop status signals ARTRY and SHD in response to a qualified snoop request that hits These signals provide infonn...

Page 143: ...issued by a processor after executing a dcbl instruction a dcbz instruction to a location marked I or S or a write operation to a block marked S If a kill blocktransaction appears on the bus and the...

Page 144: ...date operation Is detected For more information on the tlble Instruction see Section 2 3 6 3 3 Translation Lookaside Buffer Management lnstructions OEA VO reply The 110 reply operation is part al the...

Page 145: ...tanding on the bus and another pipelined bus operation hits against a modified block the 604 provides a high priority push operation This transaction can be enveloped within the address and data tenur...

Page 146: ...e 3 5 does not include noncacheable or write through cases nor does it completely describe the mechanisms for the operations described For more information see Section 3 10 Cache Actions Chapter 3 Add...

Page 147: ...k S 001 I Load Read 001 01010 nla XRTRVor Release the bus 7 RTRV Hl retry the operation 001 ME Load None n a n a nla n a Load from cache s 011 ESI Load Single 01M 01010 nla None or Load from main memo...

Page 148: ...ead 000 11010 Set ii Load the block of data into cache atomic by set reservation this op load from cache mark cache block S 000 I lwanc Read 000 11010 Va AlmNor Release the bus atomic Am RV m retry th...

Page 149: ...from main memory 011 M lwanc Single 01M 11010 nla ARTF Vor Paradox cache should be I 010 beat read ARTFIV m release the bus atomic retry the operation 100 I lwanc nla nla nla nla nla Alwanc to a page...

Page 150: ...None or Store to main memory 010 flush 11M SRn 110 111 011 I Store Write with 01M 00010 n a Am RVor Release the bus 010 flush 11M XR fRV m retry the operation 110 111 011 ES Store Write with 01M 00010...

Page 151: ...AD retry the oP ration 000 s stwcx Kill 000 01100 Yes None or Wait forthe kill to be successfully and SAD presented reset release reservation i pdate condition register store to cache mark cache block...

Page 152: ...ondition register 010 011 I stwcx Write with 01M 10010 Yes None or Release reservation 010 flush and mm update condition register atomic reset store to main memory 011 I stwcx Write with 01M 10010 Yes...

Page 153: ...10 n a None Load the block of data into cache mark the cache E 001 I debt Read 001 01010 nla m Load the block of data into cache mark the cache S 001 I debt Read 001 01010 nla 1J ITRYor Release the bu...

Page 154: ...a Load the block of data into cache mark the cache S 000 I debtst Read 000 01010 Va or Release the bus retry the operation 000 s debtst None n a n a Va n a No op 000 ME debtst None 000 n a Va n a No o...

Page 155: ...dcbz Kill 000 01100 n a None or Establish the block in data cache SRl5 without fetching the block from main memory clear all bytes mark cache block M 000 SI dcbz Kill 000 01100 n a AATRVor Release th...

Page 156: ...rk cache block E 000 M dcbst Write with 100 00110 nla JJITFIVor Release the bus kill JJITFIV retry the operation 001 ESI debst Clean 001 00000 nla None or No op 001 ESI debst Clean 001 00000 nla ARTRY...

Page 157: ...m retry the operation 000 I dcbf Flush 000 00100 n a None or No op SRI 000 I dcbf Flush 000 00100 n a ARTRY or Release the bus Am RV SR15 retry the operation 000 ES dcbf Flush 000 00100 nla None or Ma...

Page 158: ...00 I debt Flush 100 00100 Va None or No op II 100 ES debt Flush 100 00100 Va None or Mark cache block I II 100 ESI debt Flush 100 00100 Va Am1fli or Release the bus Am1fli mti retry the operation 100...

Page 159: ...the operation 001 EM debI Kill 001 01100 Va None or Mark cache block I m 001 EM debI Kill 001 01100 Va ARTRYor Release the bus AR TRV m retry the operation 011 I debI Kill W1M 01100 Va None or No op...

Page 160: ...the operation 001 VAL lcbl ICBI 001 01101 nla None or Mark icache block INV fl 011 INV lcbl ICBI 01M 01101 nla None or No op 010 11M fl 110 111 011 INV lcbl ICBI 01M 01101 nla ARTRYor Release the bus...

Page 161: ...rage invalidate mm instructions Wait for the completion of any outstanding storage instructions Invalidate the requested TLB entry Note This table does not thoroughly characterize the tlble instructio...

Page 162: ...atomic E Snoop xx1 11010 wa Mark cache bbck S read atomic M Snoop xx1 11010 wa AJ tTRV Attempt to write cache block read backto main memory if atomic successful mark cache block S I Snoop xx1 01110 N...

Page 163: ...write cache block RWITM and backto main memory atomic reset if successful markcache block I release reservation I Snoop xx1 00100 None None No op flush I Snoop xx1 00100 Yes None No op flush SE Snoop...

Page 164: ...adox no one else should be write with and writing if this cache ls M flush reset Attempt to write cache block backto main memory if successful markcache block I release reservation I Snoop xx1 00110 N...

Page 165: ...None Paradox no one else should be write with writing if this cache is E flush Mark cache block I atomic E Snoop xx1 10010 Yes None Paradox no one else should be write with and writing if this cache...

Page 166: ...0 n a J FITRV Ha TLB invalidate Is pending SYNC respond with retry n a Snoop xx1 01001 n a None Hno TLB invalidates are TLBSYNC pending no op n a Snoop xx1 01001 n a J FITRV Ha TLB invalidate is pendi...

Page 167: ...t and noncacheable direct store therefore the 604 does not maintain coherency for these operations and the cache is bypassed completely Memory forced direct store operations These operations are consi...

Page 168: ...loating point status and control register FPSCR Additionally certain exception conditions can be explicitly enabled or disabled by software The PowerPC architecture requires that exceptions be taken i...

Page 169: ...rmed by the software linked to the appropriate vector offset Exception handling is begun in supervisor level referredto as privilegedstate in the architecture specification Note that the PowerPC archi...

Page 170: ...tion of a qualHied TEAindication on the 604 bus or the machine check input signal If the MSR ME is deared the processor enters the checkstop state when one of these signals is asserted Note that MSR M...

Page 171: ...d exception condition is generated when either MSR FEO or MSR FE1 and FPSCR FEX are set The settings of FEO and FE1 are descrl ed in Table4 4 FPSCR FEX is set by the execution ol a floating point inst...

Page 172: ...Reserved 01000 012FF Reserved for implementation specific exceptions not implemented on the 604 Instruction 01300 An instruction address breakpoint exception occurs when the address bits 0 to address...

Page 173: ...where instruction execution should resume after the exception is handled When an exception occurs the address saved in machine status save restore register 0 SRRO is used to help calculate where inst...

Page 174: ...rved bits are not saved Table 4 3 MSR Bit Settings Blt s Name Description 0 Reserved FuH Function 1 4 Reserved Partial function S 9 Reserved FuU function 10 12 Reserved Partial function 13 POW Power m...

Page 175: ...branch instruction 23 FE1 IEEE floating point exception mode 1 See Table 4 4 24 Reserved This bit corresponds to the Al bit of the POWER architecture 25 IP Exception prefix The setting of this bit spe...

Page 176: ...Bits FED FE1 Mode 0 0 Floating point exceptions disabled 0 1 Floating point imprecise nonrecoverable 1 0 Floatlng point Imprecise recoverable In the 604 this bit setting causes the 604 to operate in f...

Page 177: ...reserved bits may not be copied 4 The MSR is set as describedin Table 4 3 The new values take effectbeginning with the fetching of the first instruction of the exception handler routine located at th...

Page 178: ...er which they were issued The rfi instruction copies SRRl bits back into the MSR The instructions following this instruction execute in the context established by this instruction For a complete descr...

Page 179: ...0 0 0 0 0 0 0 ILE Program 0 0 0 0 0 0 0 0 0 0 0 ILE Floating 0 0 0 0 0 0 0 0 0 0 0 ILE point unavaDable Decrementer 0 0 0 0 0 0 0 0 0 0 0 ILE System call 0 0 0 0 0 0 0 0 0 0 0 ILE Trace 0 0 0 0 0 0 0...

Page 180: ...mot resume reliably the MSR RQ bit SRR1 30 is deared MSR POW 0 BE 0 ILE FE1 0 EE 0 IP PR 0 IA 0 FP 0 DR 0 ME RI 0 FEO 0 LE Set to value of ILE SE 0 The SRESET input provides a warm reset capability Th...

Page 181: ...e bus operation If the MSR ME bit and the appropriate bits in HIDO are set the exception is recognized and handled otherwise the processor generates an internal checkstop condition When a processor is...

Page 182: ...cution cannot resume in the same context that existed before the exception If the condition that caused the machine check does not otherwise prevent continued execution MSR ME is set to allow the proc...

Page 183: ...and an attempt to fetch the next instruction fails This exception is implemented as it is defined by the PowerPC architecture OEA In addition an instruction fetch from a no execute segment results in...

Page 184: ...olving double precision values aligned on a double word boundary require two accesses which are translated separately Ifeither translation creates a OSI exception condition that exception is signaled...

Page 185: ...ode a floating point instruction that causes a floating point exception brings the machine to a precise state In doing so the 604 sequencer unit can detect floating point exception conditions and take...

Page 186: ...e Programming Environments Manual When a system call exception is taken instruction execution resumes at offset OxOOCOO from the physical base address indicated by MSR IP 4 5 11 Trace Exception OxOODO...

Page 187: ...in the MMCRO register As with other PowerPC interrupts the performance monitoring interrupt follows the normal PowerPC exception model with a defined exception vector offset OxOOFOO The priority of t...

Page 188: ...serting the HALTED output regardless whether the clock is stopped Nap mode must be entered by using the following code sequence naploop sync mtmsr GPR modify the POW bit QD JJl at this point the EE bi...

Page 189: ...the assertion of INT SRESET MCP or SMI when a decrementer interrupt occurs or when a hard reset is sensed For more information about the RUN and HALTED signals refer to Section 7 2 10 4 Run RUN lnput...

Page 190: ...ed by PowerPC processors to locate the effective to physical address mapping for instruction and data accesses The segment information translates the effective address to an interim virtual address an...

Page 191: ...56 Mbytes from the 32 bit effective address space into the physical memory space This canbe used for translating large address ranges whose mappings do not change frequently Direct store segments If t...

Page 192: ...Mbyte sizes translation Implemented with IBAT and DBAT registers in BAT array Memory protection Architecturally defined Segments selectable as no execute Pages selectable as user supervisor and read o...

Page 193: ...Bs with the following characteristics 128 entries two way set associative 64 x 2 LRU replacement Data TLB supports the DMMU instruction TLB supports the IMMU Hardware TLB update Hardware update of mem...

Page 194: ...nd to enforce the protection hierarchy programmed by the operating system Section 4 3 Exception Processing describes the MSR which controls some of the critical functionality of the MMUs The figures s...

Page 195: ...Data Instruction Accesses Accesses OI OI I 0 ifi ifi A20 A31 PAG PA31 Figure 5 1 MMU Conceptual Block Dlagram 32 Blt Implementations 5 6 PowerPC 604 RISC Microprocessor User s Manual...

Page 196: ...Instruction Unit 1 PAO PA31 128 Sets l _a_ch_ _ 0 TAGS Select A20 A26 3 TAGS TAGS TAGS 0 19 Compare I Cache Hit Miss Figure 5 2 PowerPC 604 Microprocessor IMMU Block Diagram Chapter 5 Memory Manageme...

Page 197: ...8 PAO PA31 128 Sets o _a_chre 0 TAGS Select A20 A26 3 0 TAGS TAGS TAGS 19 Compare DCache Hit Miss Figure 5 3 PowerPC 604 Microprocessor DMMU Block Diagram PowerPC 604 RISC Microprocessor Uaer s Manua...

Page 198: ...the implementation invokes an elaborate hardware protocol for communication with these devices The direct store interface protocol is not optimized for performance and therefore its use is discourage...

Page 199: ...aining information in the segment descriptor is interpreted as identifier information that is used with the remaining effective address bits to generate the packets used in a direct store interface ac...

Page 200: ...no execute option is provided in the segment descriptor Each of the remaining options is enforced based on a combination of information in the segment descriptor and the page table entry Thus the supe...

Page 201: ...ed bit or the changed bit is not set the hardware automatically sets both bits in the translation table In addition during the address translation portion of a store operation that hits in the TLB the...

Page 202: ...n Real Addressing Mode and Block Note that if the BAT array search results in a hit the access is qualified with the appropriate protection bits If the access violates the protection mechanism an exce...

Page 203: ...in Figure 5 6 In addition Figure 5 6 also shows the way in which the no execute protection is enforced if the N bit in the segment descriptor is set and the access is an instruction fetch the access...

Page 204: ...are Virtual Address with TLB Entries L J TLB Miss TLB Hit _ See Figure 5 8 Perform Page Table Search Operation See Figure 5 9 PTENot Found PTE Found r _I_ Access Permitted Translate Address Continue A...

Page 205: ...criptor has the T bit set the access is considered a direct store interface access and the direct store interface protocol of the external interface is used to perform the access to direct store space...

Page 206: ...mory either matching xBAT G 1 or no matching BAT SRR1 3 1 entry and PTE G 1 In addition to the translation exceptions there are other MMU related conditions some of them defined as implementation spec...

Page 207: ...ruction attempted while MSR LE 1 little endian mode Operand misalignment Translation enabled and operand is Alignment exception some misaligned as descrbed in Chapter 4 of these cases are Exceptions i...

Page 208: ...PC 604 Processor Programming Model Table 5 6 PowerPC 604 Microprocessor MMU Registers Register Description Segment registers The sixteen 32 bit segment registers are present only in 32 bit Implementat...

Page 209: ...hat is not subject to normal virtual memory handling paging such as a memory mapped display buffer or an extremely large array ofnumerical data Block address translation in the 604 is described in Cha...

Page 210: ...f the page based on this access Table 5 7 Table Search Operations to Update History Blts TLB Hit case RandCbHs Processor Action lnTLB Entry 00 Combination doesn t occur 01 Combination doesn t occur 10...

Page 211: ...of the PTE loaded into the TLB if a TLB is implemented as in the 604 Whenever a data store instruction is executed successfully if the TLB search for page address translation results in a hit the chan...

Page 212: ...table load operations include those generated by load instructions by the eciwx instruction andby the cache managementinstructions that are treated as a load with respect to address translation Simila...

Page 213: ...nt registers for the MMU the 604 maintains two identical sets of segment registers one for the IMMU and one for the DMMU when a segment register instruction executes the 604 automatically updates both...

Page 214: ...e matching PTE is found in memory it is loaded into a particular TLB entry selected by the least recently used LRU replacement algorithm and the translation process begins again this time with a TLB h...

Page 215: ...lidates four entries both the ITLB entries indexed by EA14 EA19 and both the indexed entries of the DTLB Execution of the tlbie instruction causes all entries in the congruence class corresponding to...

Page 216: ...can be used to invalidate a particular index of the TLB based on EA 14 19 With that concept in mind a sequence of 64 tlbie instructions followed by a single tlbsync instruction would cause all the 604...

Page 217: ...ception Check Page Memory Protection Violation Conditions see The Programming Environments Manualj Access Penniltad Access Prohibited see The Programming EnVlronmfltlts Manual PTE CJ 0 otherwise Page...

Page 218: ...the following must be true PTE H 0 PTE V 1 PTE VSID VA 0 23 PTE API VA 24 29 4 If a match is not found step 3 is repeated for each of the other seven PTEs in the primary PTEG If a match is found the...

Page 219: ...ip cache Figure 5 9 and Figure 5 10 show how the conceptual model for the primary and secondary page table search operations described in The Programming Environments Manual are realized in the 604 Fi...

Page 220: ...E intoTLB otherwise Check Memory Protection VIOiation Conditions Aocess Permitted ocess Prohibited dcbz Instruction withWor1 1 R_ otherwlse PTE R 1 Update PTE R mMemory otherwl oreoperation with PTE C...

Page 221: ...operation begins Once the matching PTE is found in memory it is loaded into the appropriate TLB entry depending on the LRU bit setting and translation continues The LSU initiates out of order accesse...

Page 222: ...a PI E Deleting a PI E PI Es must be locked on multiprocessor systems Access to PI Es must be appropriately synchronized by software locking of that is guaranteeing exclusive access to PI Es or PI EG...

Page 223: ...ring any higher level synchronization However extreme care must be taken to ensure that no store overwrites one of these bytes accidentally Processors write referenced and changed bits with unsynchron...

Page 224: ...m these accesses involves the transfer ofaddress and data information in packets however the PowerPC OEA does not define the exact hardware protocol used for direct store interface accesses Some instr...

Page 225: ...cbi 5 5 5 Direct Store Segment Translation Summary Flow Figure 5 11 shows the flow used by the MMU when direct store segment address translation is selected This figure expands the direct store segmen...

Page 226: ...or stwcx instruction otherwise r L DSISR S 1 otherwise dcbtst dcbf dcbl dcbst L J dcbz or lcbl OSI Exception or Boundedly Undefined Results Perform Direct Store Interface Access _ C No Op Optional to...

Page 227: ...e is forced to stall in its cycle In some cases an instruction may also occupy more than one stage simultaneously for example instructions may complete and write back their results in the same cycle A...

Page 228: ...ions on the mispredictedpath are purged from the instructionpipeline and arereplaced with the instructions from the nonpredicted path Program order The original order in which program instructions are...

Page 229: ...Overview The 604 has been designed to maximize instruction throughput and minimize average instruction execution latency For many ofthe instructions in the 604 this can be simplified to include only t...

Page 230: ...ne instruction per clock cycle can be realized by the many performance features in the 604 including multiple execution units that operate independently and in parallel pipelining superscalar instruct...

Page 231: ...uctions per cycle are completed in program order In the write back stage results are returned to the register file Instructions are fetched and executed concurrently with the execution and write back...

Page 232: ...e pipelines The division of instructions into branch integer load store and ftoating poirit instructions indicates the execution unit in which the instructions execute For example mtspr instructions w...

Page 233: ...ages Figure 6 4 PowerPC 604 Microprocessor Pipeline Stages Table 6 1 lists the latencies and throughputs for general groups of instructions Table 6 1 Execution Latencies and Throughputs Instruction La...

Page 234: ...ation by the decode stage The instruction fetching logic is shown in Figure 6 5 BTAC Decode Buffer Decode Prediction Dispatch Buffer Dispatch Prediction Pending Branch Queue Target 1 Seq 1 BPU Reserva...

Page 235: ...gic may indicate based on the BHT or an unconditional branch decode that an earlier BTAC prediction was incorrect The BPU can indicate that a previous branch prediction either from the BTAC or the dec...

Page 236: ...e flushed and fetching resumes at the correct address If an instruction causes an exception the execution unit reports the exception to the complete stage and continues executing instructions regardl...

Page 237: ...hose restrictions necessary to support a precise exception model the 604 imposes the following restrictions per each cycle Completion stops before a store since store data is read directly from GPRs o...

Page 238: ...ck any information from the rename buffers that was not written back by the complete stage As mentioned in Section 6 2 1 1 5 Complete Stage each of the rename buffers has two read ports for write back...

Page 239: ...4 Memory Operations briefly describes how these modes may affect instruction timing 6 3 1 MMU Overview The 604 implements separate 128 entry two way set associative TLBs one each for instruction and d...

Page 240: ...without having to wait for the actual store operation to take place either in the cache or in system memory When the cache is not busy one completed store can be written to the cache per cycle In the...

Page 241: ...as many as three outstanding pipelined operations The BIU can complete one or more write transactions between the address and data tenures of a read transaction The BIU provides critical double word f...

Page 242: ...memory for example video memory or when there is shared global data that may be used frequently or when allocation of a cache block on a cache miss is undesirable Cached data is not automatically writ...

Page 243: ...e operand becomes available The 604 contains the following execution units that operate independently and in parallel Branch processing unit BPU Two 32 bit single cycle integer units SCIU One 32 bit m...

Page 244: ...the instruction being asked for is in the on chip cache cache hit or whether a memory transaction is required to bring the data into the cache cache miss 6 4 2 1 Cache Hit Timing Example Assuming tha...

Page 245: ...cycle 1 the last two instructions in the cache block addc and subfc are fetched while instructions 0 3 pass into the decode stage 2 In cycle 2 the two integer add instructions 0 and 1 are dispatched o...

Page 246: ...structions were ready for dispatch Note that because ofin order dispatch the integer instructions 8 and 9 are also held in the dispatch stage behind the fmsub instruction The final pair of floating po...

Page 247: ...ions move into execute stage along with the previous fsubs instruction which is in the first stage of execute The fmadd instruction completes and writes back and the subsequent floating point instruct...

Page 248: ...hat this example asswnes a best case scenario 0 I I Io add I 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I I I I I I I I Address I t 5add I I 1 l61subl h I I l7addl lllll l C J Fetch Execute llmlllllllllll 1...

Page 249: ...bus and access has been granted for the data bus 6 In cycle 6 fadd 1 completes and writes back allowing the add 2 instruction to complete and write back The fadd 3 instruction is in the final execute...

Page 250: ...be taken The 64 entry BTAC is fully associative to provide a high hit percentage Ifa fetch address is in the BTAC the target address is used in the next cycle to fetch the instructions from the predic...

Page 251: ...xamples use the following code sequence and ld add be or cmp ld mulli 6 4 4 1 1 Timing Example Branch Timing for a BTAC Hit Figure 6 9 shows the timing for a branch instruction that had a BTAC hit 0 0...

Page 252: ...br instruction also completes Because the branch is taken the or 4 instruction which could otherwise write back in this cycle stays in the complete stage and completes and writes backinthe nextcycle T...

Page 253: ...execute stage of the LSU pipeline Instructions 2 and 3 wait in the complete stage Instructions 4 7 enter the dispatch stage 3 In cycle 5 the Id 1 instruction is able to write back allowing the follow...

Page 254: ...1 Execute IIIIIII1 Complete Write Back 4 5 6 7 8 I I I I I I I I I 1111 Figure 6 11 Instruction Timing Branch with BTAC Miss Dispatch Correction 6 4 4 1 4 Timing Example Branch with BTAC Miss Execute...

Page 255: ...To record the predicted state the 604 uses many of the same resources primarily the rename buffers and completion buffer and logic as the mechanism used to maintain a precise exception model as is co...

Page 256: ...h have two entry in order reservation stations These stations allow instructions to clear the dispatch stage even though operands may not yetbe available for execution to occur The BPU FPU and LSU ins...

Page 257: ...name registers are provided for the GPRs eight for the FPRs and eight for the condition register A GPR rename buffer entry is allocated when an instruction that modifies a GPR is dispatched This entry...

Page 258: ...GPR has not yet executed In this case the instruction is dispatched with the rename buffer entry identifier inplace ofthe operand which will be supplied by the reservation station when the result is p...

Page 259: ...to that unit to fill the remaining pipeline stages 6 4 7 Instruction Serialization Some instructions such as mfspr and most mtspr instructions extended arithmetic instructions that require the carry...

Page 260: ...until the completion block informs the execution unit to execute the instruction This means it is guaranteed to wait at least one cycle before it can execute Instructions causing execution serializat...

Page 261: ...nch Unit Instruction Timings The 604 can have two unresolved branches in the branch reservation station and two resolved branches that have not yet completed The branch unit serves to validate branch...

Page 262: ...ervation Station I Rotate Shift i Adder Logic I CTLZ Comparator ics j_ 3 1 MUX I j Figure 14 SCIU Block Diagram The MCIU which handles all integer multiple cycle integer insttuctions consists of a 32...

Page 263: ...are not execution serialized 6 5 3 Floating Point Unit Instruction Timings The floating point unit on the 604 executes all floating point instructions Execution of most floating point instructions is...

Page 264: ...zed data types Instructions are obtained from the instruction dispatcher and placed in the reservation station queue The operand sources are the FPR the floating point rename buffers and the result bu...

Page 265: ...of order execution are resolved by the LSU The se dependencies arise when in the instruction stream a store is followed by a load from the same address If the load instruction is speculatively execute...

Page 266: ...cuted until all of the instruction operands are valid The address calculation block includes a 32 bit adder that computes the effective address for all operations The data alignment blocks manage the...

Page 267: ...branch unit instructions as specified by the PowerPC architecture but they do not actually execute in the BPU in the same sense that other branch instructions do The completion unit treats the rfi and...

Page 268: ...MCIU executes all integer multiply divide and move to from instructions exceptmtcrfinstructions thatupdate only one field which areexecutedin either of the SCIUs The load store unit executes load stor...

Page 269: ...in the execute andcomplete stages The dispatchstalls onthe first instruction after the fourth branchuntil the first branch completes An instruction cannot be dispatched until all destination register...

Page 270: ...hen the option exists Forexample an integer register copy can be performed in a single cycle using a number of different instructions However using an ori instruction with an immediate operandofzero u...

Page 271: ...ching nevertheless changing control flow in aprogram is relatively expensive in that fullest advantage cannot be taken ofresources that can improve throughput such as superscalar instruction dispatch...

Page 272: ...eline Integer multiplies other than those that can exit early described in the previous bullet stall for one cycle in the first stage ofthe pipeline Integerdivide instructions iterate in stage two oft...

Page 273: ...cntlzw SCIU 1 crand BPU 1 Execute crandc BPU 1 Execute creqv BPU 1 Execute crnand BPU 1 Execute crnor BPU 1 Execute cror BPU 1 Execute crorc BPU 1 Execute crxor BPU 1 Execute dcbf LSU Execute dcbl LSU...

Page 274: ...ctlwz FPU 3 fdlv FPU 32 FPeq ty1 tdlvs FPU 18 FPeq ty1 tmadd FPU 3 tmadds FPU 3 tmr FPU 3 tmsub FPU 3 tmsubs FPU 3 tmul FPU 3 tmuls FPU 3 tnabs FPU 3 tneg FPU 3 tnmadd FPU 3 tnmadds FPU 3 tnmaub FPU 3...

Page 275: ...LSU 3 lfsu LSU 3 lfsux LSU 3 lfsx LSU 3 Iha LSU 2 lhau LSU 2 lhaux LSU 2 lhax LSU 2 lhbrx LSU 2 lhz LSU 2 lhzu LSU 2 lhzux LSU 2 lhzx LSU 2 lmw LSU regs 2 String multiple lswl LSU 2 regs 2 String mult...

Page 276: ...MCIU 1 DispatclVExecute mtcrf single bit SCIU 1 mtfsbO FPU 3 mtfsb1 FPU 3 mtfsf FPU 3 mtfsfl FPU 3 mtmsr MCIU 1 Execute mtspr LR CTR MCIU 1 Dispatch mtspr XER MCIU 1 Complete 2 mtspr others MCIU 1 Ex...

Page 277: ...dux LSU 3 Execute stfdx LSU 3 Execute stflwx LSU 3 Execute SUS LSU 3 Execute stfsu LSU 3 Execute stfsux LSU 3 Execute stfsx LSU 3 Execute sth LSU 3 Execute sthbrx LSU 3 Execute sthu LSU 3 Execute sthu...

Page 278: ...U tlbl LSU Execute tlbaync LSU tw SCIU 1 twl SCIU 1 xor SCIU 1 xorl SCIU 1 xorl SCIU 1 1 These Instructions ara not pJpeOned They cannol be executed untl the pnwlous lnstrucllon In the FPU completes s...

Page 279: ...ss transfer start signals These signals indicate that a bus master has begun a transaction on the address bus Address transfer signals These signals which consist of the address bus address parity and...

Page 280: ...rupt and under various conditions to reset the processor JTAG COP interface signals The JTAG IEEE 1149 1 interface and common on chip processor COP unit provides a serial interface to the system for p...

Page 281: ...OP INTERFACE Figure 7 1 PowerPC 604 NJlcroprocessor Signal Groups 7 2 Signal Descriptions This section describes individual 604 signals grouped according to Figure 7 1 Note that the following sections...

Page 282: ...aster that assertedARTRY due to the need to perform a cache line push 7 2 1 2 Bus Grant lm lnput The bus grant BG signal is an input signal on the 604 Following are the state meaning and timing commen...

Page 283: ...cycle following a qualified bus grant the 604 did not accept mastership even if BR was asserted High Impedance Occurs one half bus cycle two thirds bus cycle when using 3 1 clock mode and one third b...

Page 284: ...s Assertion Coincides with the assertion ofABB Negation Occurs one bus clock cycle after TS is asserted High Impedance Occurs one bus clock cycle after TS is negated 7 2 2 1 2 Transfer Start TS lnput...

Page 285: ...ls 7 2 3 1 1 Address Bus AO A31 0utput Memory Operations Following are the state meaning and timing comments for the AO A31 output signals State Meaning Asserted Negated Represents the physical addres...

Page 286: ...timing comments for input direct store operations on the 604 State Meaning Asserted Negated When the 604 is not the master it snoops and checks address parity onthe first address beatonly ofall direct...

Page 287: ...r deassertion of the APE signal Following are the state meaning and timing comments for the APE signal on the 604 For more information see Section 8 3 2 1 Address Bus Parity State Meaning Asserted Ind...

Page 288: ...sfer in progress see Table 7 1 For direct store operations the TTO TT3 signals form part of the XATC and are snooped by the 604 ifXATS is asserted Timing Comments Assertion Negation The same as AO A31...

Page 289: ...beat Caching inhibited read or burst load 0 1 1 1 0 Read with Intent Burst Load miss or store to modify miss 1 0 0 1 0 Write with flush Single beat stwcx atomic write 1 0 1 1 0 Reserved NIA NIA 1 1 0...

Page 290: ...nd ecowx TSIZO TSIZ2 are used to output bits 29 31 of the external access register EAR which are used to form the resource ID TBSTllTSIZO TSIZ2 Timing Comments Assertion Negation The same as AO A31 Hi...

Page 291: ...eaning Asserted Negated For the 1 0 transfer protocol this signal forms part ofthe 1 0 transfer code see Section 7 2 4 1 TransferType TTO TT4 Timing Comments Assertion Negation The same as AO A31 7 2...

Page 292: ...ordinary and atomic read and read with intent to modify operations 2 ICBI operation is distinguished from kiU block by assertion of TT4 bit 3 W write through bit from translation The value shown in t...

Page 293: ...is not global Timing Comments Assertion Negation The same as AO A31 High Impedance The same as AO A31 7 2 4 7 2 Global GBL lnput Following are the state meaning and timing comments for the GBL input s...

Page 294: ...for slow devices For example if an implementation supports slow snooping devices an external arbiter can postpone the assertion ofAACK Negation Must occur one bus clock cycle after the assertion of AA...

Page 295: ...bus master to allow an opportunity for a copy back operation to main memory Note that the subsequent address presented on the address bus may not be the same one associated with the assertion of the A...

Page 296: ...tailed information about using DBWO see Section 8 11 Using Data Bus Write Only 7 2 6 1 Data Bus Grant DBG lnput The data bus grant DBG signal is an input signal input only on the 604 Following are the...

Page 297: ...DBB output signal State Meaning Asserted Indicates that the 604 is the data bus master The 604 always assumes data bus mastership if it needs the data bus and is given a qualified data bus grant see D...

Page 298: ...is there are no 64 bit 1 0 transfers Timing Comments The data bus is driven once for noncached transactions and four times for cache transactions bursts Table 7 4 Data Bus Lane Assignments Data Bus Si...

Page 299: ...ts are listed in Table 7 5 Timing Comments Assertion Negation The same as DLO DL31 High Impedance The same as DLO DL31 Table 7 5 DPO DP7 Slgnal Assignments Signal Name Signal A slgnments DPO DHO DH7 D...

Page 300: ...tate Meaning Asserted Indicates for a write transaction that the 604 must release data bus and the data bus parity to high impedance during the following cycle The data tenure will remain active DBB w...

Page 301: ...or fast L2 mode must not be asserted earlier than the first cycle of avalid ARTRY window otherwise assertion may occur at any time during the assertion ofDBB The system can withhold assertion of TAto...

Page 302: ...e MSR ME 0 Assertion terminates the current transaction that is assertion ofTA and DRTRY are ignored The assertion ofTEAcauses the negation high impedance ofDBB in the next clock cycle However data en...

Page 303: ...d and negated synchronously with the SYSCLK signal 7 2 9 2 System Management Interrupt SMl lnput The system management interrupt SMI signal is input only Following are the state meaning and timing com...

Page 304: ...llowing are the state meaning and timing comments for the CKSTP_IN signal State Meaning Asserted Indicates that the 604 must terminate operation by internally gating off all clocks and release all out...

Page 305: ...ing Comments Assertion May occur at any time and may be asserted asynchronously to the 604 input clock must be held asserted for a minimum of 255 clock cycles Negation May occur any time after the min...

Page 306: ...ng Comments Assertion Negation May occur on any cycle 7 2 10 2 Reservation RSRV Output The reservation RSRV signal is output only on the 604 Following are the state meaning and timing comments for the...

Page 307: ...e to the 604 entering nap mode or a JTAG COP request Negated Indicates that internal clocks are running Timing Comments Assertion Negation Occurs synchronously with internal processor clock For additi...

Page 308: ...bus interface Internally the 604 uses a phase lock loop PLL circuit to generate a master clock for all of the CPU circuitry including the bus interface circuitry which is phase lockedto the SYSCLK inp...

Page 309: ...ion 7 2 12 4 PLL Configuration PLL_CFGO PLL_CFG3 lnput The PLL phase lock loop is configured by the PLL_CFGO PLL_CFG3_pins For a given SYSCLK bus frequency the PLL configuration pins set the internal...

Page 310: ...04 hardware specifications for tlmilg comments PLL frequencies shown In parenthesis In the table above should not fall below 100 MHz and should not exceed 200 MHz 2 In PLL bypass mode the SVSCLK i11 u...

Page 311: ...tions are automatically fetched from the memory system into the instruction unit where they are dispatched to the execution units at apeakrate offour instructions per clock Conversely load and store i...

Page 312: ...ough memory read and write operations Additionally there can be address only operations variants of the burst and single beat operations global memory operations that are sno9ped and atomic memory ope...

Page 313: ...NIT 16 Entry Reorder Buffer 32Bit Fetcher Instruction Queue 8 word GPRFile Rename Buffers 12 rn 128Bit DMMU 64Bit Store Queue Finish Load I Ilo ATI IDTLB I array i 1_ _ 1 Queue 32Bit 32 BIT ADDRESS BU...

Page 314: ...is flexible allowing the 604 to be integrated into systems that implement various fairness and bus parking procedures to avoid arbitration overhead Typically memory accesses are weakly ordered sequen...

Page 315: ...ing Diagram Legend 8 1 3 Direct Store Accesses Memory and direct store accesses use the 604 signals differently The 604 defines separate memory and 1 0 address spaces or segments distinguished by the...

Page 316: ...that the address and data tenures are distinct from one another and that both consist of three phases arbitration transfer and tennination Address and data tenures are independent indicated in Figure...

Page 317: ...ly the 604 s retry capability provides an efficient snooping protocol for systems with multiple memory systems including caches that must remain coherenL 8 2 1 Arbitration Signals Arbitration for both...

Page 318: ...Dim data bus busy Assertion by the 604 indicates that the 604 is the data bus master The 604 always assumes data bus mastership if it needs the data bus and is given a qualified data bus grant see DBG...

Page 319: ...astership of the address bus to the next requesting master before the current data bus tenure has completed Three address tenures can occur before the current data bus tenure completes The 604 can pip...

Page 320: ...e previous cycle the 604 has what is referred to as a qualified bus grant The 604 assumes address bus mastership by asserting ABB when it receives a qualified bus grant Logical Bus Clock ne8d_bus 1 Im...

Page 321: ...sserting ABB and negating the BR output signal Meanwhile the 604 drives the address for the requested access onto the address bus and asserts TS to indicate the start of a new transaction When designi...

Page 322: ...e T TT4 transfer code TCO TC2 transfer size TSIZO TSIZ2 transfer burst TBST cache inhibit Cl write through WT global GBL and cache set element CSEO CSEl Figure 8 6 shows that the timing for all of the...

Page 323: ...r Attribute Signals The transfer attribute signals include several encoded signals such as the transfer type TTO TT4 signals transfer burst TBST signal transfer size TSIZO TSIZ2 signals and transfer c...

Page 324: ...e cache in order Burst write transfers are always performed zero double word first butsince burst reads are performedcritical double word first a burst read transfermay not start with the first double...

Page 325: ...nerate burst memory operations if they miss the 604 interface supports misaligned transfers within a word 32 bit aligned boundary as shown in Table 8 5 Note that the four byte transfer in Table 8 5 is...

Page 326: ...th a size of fewer than four bytes For the first bus operation bits A29 A31 equals bits 29 31 of the data which will be OblOl ObllO or Oblll The size associated with the first bus operation will be 3...

Page 327: ...can be used with the WT TTO TI4 and TBST signals to further define the current transaction When asserted the transfer codes have the following meanings TCO Read cycle indicates code fetch Write cycle...

Page 328: ...ress transfer until the AACK address acknowledge input is asserted therefore the system can extend the address transfer phase by delaying the assertion of AACK to the 604 AACK can be asserted as early...

Page 329: ...le following the first or only assertion of TA for the data tenure the 604 ignores the first data beat and if it is a load operation does not forward data internally to the cache and execution units I...

Page 330: ...re 8 7 H the data bus is needed the arbiter grants data bus mastership by asserting the DBG input to the 604 As with the address bus arbitration phase the 604 must qualify the DBG input with a number...

Page 331: ...e cycles before the beginning of the snoop window in fast L2 data streaming then data is transferred too early to be cancelled by ARTRY Therefore systems in which ARTRY can be asserted must not attemp...

Page 332: ...a previously requested read data tenure Following the ARTRY assertion the qualified DBG assertion to the 604 in cycle 7 will be accepted for the read data tenure 2 3 4 s I 6 I 7 8 9 10 System Clock TS...

Page 333: ...ddress tenures were performed The 604 however also supports a limited out of order capability with the data bus write only DBWO input The DBWO capability exists to alleviate deadlock conditions that a...

Page 334: ...all other burst operations however the Cil he line write operations are transferred beginning with the oct word aligned data and burst reads begin on double word boundaries The 604 does not directly s...

Page 335: ...ses the data tenure to be tenninated immediately ifthe AR IRY is for the address tenure associated with the data tenure in operation the data tenure may not be tenninated due to address pipelining If...

Page 336: ...ure 8 12 The bus clock cycles in which TA is asserted need not be consecutive thus allowing pacing of the data transfer beats For read bursts to terminate successfully TEAand DRlRY must remain negated...

Page 337: ...in Figure 8 13 DBB cannot be asserted until bus clock cycle 5 This is true for both read and write operations even though DRTRY does not extend bus mastership for write operations 2 3 mm I M Jt data I...

Page 338: ...g the TEA so that the bus operations associated with a machine check exception can proceed Due to bus pipelining in the 604 all outstanding bus operations including all queued requests are completed i...

Page 339: ...t result in the generation of machine check exceptions Note that TEA generates a machine check exception depending on the ME bit in the MSR Clearing the machine check exception enable control bit lead...

Page 340: ...01 Note that write hits to clean lines ofnonglobal pages do not generate invalidate broadcasts There are several types of bus transactions that involve the movement of data that can no longer access t...

Page 341: ...Intent to Modify SHR Snoop Hit on a Read SHW Snoop Hit on a Write or D Cache Block Fill Read with Intent to Modify Figure 8 15 MESI Cache Coherency Protocol State Diagram WIM 001 Table 8 7 shows the...

Page 342: ...e stated between bus tenures 8 32 1112 31415 6 I 7 I a I 9 I 10 11 12 BR l _ W I _ _ __ __ I 1 m A 1 b A 1 1 TPn I t 1 1 l DD I i ____ i ___ J T I I I I I AO A311 I l _ c_ru_A c Pu_A 1 acru jj AA l l...

Page 343: ...1 I 1 I 2 a I 4 I s I 6 7 I s I 9 I 10 11 I 12 BR _ _ _ _ _ _ _ _ ____ 1__ _ _ _ _ ___ mi lffi lffi Mlf W ABB I I r I 1 ___ I 1 r _ I I TS I I I AO A31 1 f CPiiA I I _ _ I TIO TI4 I sew sew sew I I I...

Page 344: ...three stated between bus tenures 1112 31415 6 I 7 I s 9 I 10 I 11 I 12 I 13 I 14 I BR1 I I UG i t w s t m i l t w f i __ _1 J 4 At F mu ABBI I I I_ I I I I 1 1 j I 1 1 i TS I I I I A0 A31 I 4 CPU A J...

Page 345: ...2 m __ __ r I _ T r 1 zj h 1 4 xim I TS I _ ___ __ rt ___ I I I I AO A31 1 1 r cFiii A l __ CPU A J l I I I I I I TTO TT4 I I saw saw H r siBiawN t 4 ll I I I I I I I I I I i i i i i i i i i i i i i H...

Page 346: ...sfer is delayed until the first transfer completes I 1 I 2 I a I4 Is I s I 1 I s I 9 110111 112 11a 11411s 11s 11111s 119 120 I AO A31 I TTO TT4 8 36 I TBSTI I I I q I XRTRV l 1 I t5DCI f5 b j j j i A...

Page 347: ...I 9 11011q1211a 11411s 11s 11r 1 tmt I l J I I I I I I I Em r I tJ I I BF r T r r I I I I I I ABS I I I __ _ I I I TS1 I I I I I AO A31 bF lTA 1 r CPITA _ ___ TIO TI4 TBSTI I I I I I I I Gm t t I h H...

Page 348: ...segment accesses The direct store protocol for the 604 allows for the transfer of 1 to 128 bytes of data between the 604 and the bus unit controller BUC for each single load or store request issued b...

Page 349: ...ng 604 transactions effectively indicating to the 604 that the BUC is in a queue full condition and cannot accept new data In addition to the extensions noted above there are fundamental differences b...

Page 350: ...wo or more direct store operations for loads from the 604 and one reply operation from the addressed BUC Table 8 8 Direct Store Bus Operations Operation Address Only Direction XATC Encoding Load start...

Page 351: ...re reply operation no store immediate operation is involved in the transfer as shown in the following sequence STORE LAST from 604 STORE REPLY from BUC However ifmore data is involved in the direct st...

Page 352: ...ee of the seven defined operations are address only transactions and do not use the data bus However unlike the memory transfer protocol these transactions are not broadcast from one master to all sno...

Page 353: ...ent operating context user or supervisor Note thatuser and supervisor level refer to problem and privileged state respectively in the architecture specification Segment register Address bits 3 27 corr...

Page 354: ...egister bits 28 31 II effective address bits 4 31 While the 604 provides the address of the transaction to the BUC the BUC must maintain a valid address pointer for the reply 8 6 3 1 0 Reply Operation...

Page 355: ...he bus and on reply operations compares this field to bits 28 31 of the PIO register to determine HIt should recognize this VO reply The second beat of the address bus is reserved the XATC and address...

Page 356: ...y as 128 bytes ofdata in one load or store instruction requiring more than 33 immediate operations in the case ofmisaligned operands In Figure 8 26 XATS is asserted with the same timing relationship a...

Page 357: ...direct store operation indicates that an unrecoverable error has occurred If the TEA signal is asserted during a direct store operation the TEA action will be delayed and following direct store trans...

Page 358: ...han in the normal bus protocol The PowerPC bus protocol specifies that during load operations the memory system normally has the capability to cancel data that was read by the master on the bus cycle...

Page 359: ...he basic and extended transfer bus protocols described in this chapter 8 7 1 1 Fast L2 Data Streaming Mode Design Considerations It is recommended that use of fast L2 data streaming mode be accompanie...

Page 360: ...ted AR1RY signal invalidates the data that was transferred the previous cycle in the same way DRTRY cancels data from the previous cycle In fast L2 data streaming mode the data buffering that allows l...

Page 361: ...oft reset The soft reset input provides warmreset capability This input can be used to avoid forcing the 604 to complete the cold start sequence When either reset input is negated the processor attemp...

Page 362: ...ant implementation of the IEEE 1149 1 standard This section describes the 604 IEEE 1149 l JTAG interface 8 10 1 IEEE 1149 1 Interface Description The 604 has five dedicated JTAG signals which are desc...

Page 363: ...een performed because of address pipelining The DBWO does not change the order of write tenures with respect to other write tenures from the same 604 It only allows that a write tenure be performed ah...

Page 364: ...DBWO Any number of bus transactions by other bus masters can be attempted between any of these steps Note the following regarding DBWO The DBWO signal can be asserted ifno data bus read is pending but...

Page 365: ...ot easily be characterized by a benchmark or trace To help system developers bring up and debug their systems The perfonnance monitoruses the following 604 specific special purpose registers SPRs Perf...

Page 366: ...ed instruction address SIA register and the sampled data address SDA register respectively For more infonnation see Section 9 1 2 2 Threshold Events For all other programmable events that cause a PMI...

Page 367: ...sing the mfspr and mtspr instructions Software is expected to use the mtspr instruction to explicitly set the PMC register to nonnegative values If software sets a negative value an erroneous interrup...

Page 368: ...store data cache misses that exceeded the threshold value with lateral L2 cache intervention 0001011 Number of mtspr instructions dispatched 0001100 Number of sync instructions completed 000 1101 Num...

Page 369: ...completed every cycle 00 None 01 Illegal value 10 One 11 Two 001001 Number of reservations successfully obtained 001010 Number of mfspr instructions dispatched speculative 00 1011 Number of lcbl inst...

Page 370: ...processor signals the performance monitor interrupt condition In this case the SDA is not meant to have any connection with the value in the SIA If the performance monitor interrupt was triggered by a...

Page 371: ...can be changed by hardware 1 HMSR PM is set the PMCn counters are not changed by hardware 4 OMA Disable counting while MSR PMJ is zero 0 The PMCn counters can be changed by hardware 1 nMSR PM is clear...

Page 372: ...r interrupt is signaled 0 Enable PMC2 counting 1 Disable PMC2 counting until PMC1 bit OIs set or unto aperformance monitor interrupt is signaled This signal can be used to trigger counting of PMC2 aft...

Page 373: ...instruction The 32 bit registers can count up to Ox7FFFFFFF 2 147 483 648 in decimal before becoming negative The most significant bit bit 0 of both registers is used to determine if an interrupt cond...

Page 374: ...struction of a load miss distribution chart When a load or store miss arrives in the load store queue the threshold control logic begins decrementing For each cycle that passes the threshold value in...

Page 375: ...provide this functionality the events that use this signal PMCl events 9 and 10 become obsolete 9 1 2 3 Nonthreshold Events Nonthreshold events are all events except for PMCl events 9 10 23 or 24 Any...

Page 376: ...n lowercase For more information refer to Chapter 8 Instruction Set in The Programming Environments Manual A 1 Instructions Sorted by Mnemonic Table A 1 lists the instructions implemented in the 604 i...

Page 377: ...9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 s A UIMM s A UIMM LI BO Bl BO BO Bl 528 LK BO Bl 16 LK crfD if L A B 0 crfD L A SIMM crfD if L A B 32 crfD ML A UIMM 26 crbD crbA c...

Page 378: ...63 D A B c 29 Re fmaddsx 59 D A B c 29 Re fmrx 63 D B 72 Re fmsubx 63 D A B c 28 Re fmsubsx 59 D A B c 28 Re fmulx 63 D A c 25 Re fmulsx 59 D A c 25 Re fnabsx 63 D B 136 Re fnegx 63 Re D 40 B fnmaddx...

Page 379: ...8 49 31 31 42 43 31 31 31 40 41 31 31 46 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 d D A d D A d D A d D A B 631 tf j D A B 599 i i i D A d D A d D A B 567 I D A B 535...

Page 380: ...f mtfsbOx mtfsb1x mtfsfx mtfsflx mtmsr 1 mtspr 2 mtsr 1 31 D A NB 31 D A B 32 D A 33 D A 31 D A B 31 D A B 19 63 31 31 63 31 31 D spr 31 D SR 31 Q j d tl ii B D 31 D tbr 31 63 63 63 63 31 31 S spr 31...

Page 381: ...mullwx 31 D A B 235 Re nandx 31 s A B 476 Re negx 31 D A rn RR 104 Re norx 31 s A B 124 Re orx 31 s A B 444 Re orcx 31 s A B 412 Re Ori 24 s A UIMM orls 25 S A UIMM rlwlmlx 20 s A SH MB ME Re rlwlnmx...

Page 382: ...d slfsu 53 s A d stfsux 31 s A B 695 slfsx 31 s A B 663 sth 44 s A d sthbrx 31 s A B 918 t sthu 45 s A d sthux 31 s A B 439 Jt sthx 31 s A B 407 w stmw 3 47 s A d stswl 3 31 s A NB 725 stswx 3 31 s A...

Page 383: ...08 D A 8 twl 03 TO xorx 31 s xort 26 s xorls 27 s 1 Supervisor level instruction 2Supervisor and user level instrudion 3Load and store siring or multiple instrudion 464 bit instrudion 5Optional instru...

Page 384: ...A SIMM subtle 001000 D A SIMM cmpll 001010 A UIMM cmpl 001011 A SIMM addle 001100 D A SIMM addle 001101 D A SIMM addl 001110 D A SIMM addls 001111 D A SIMM bcx 010000 SC 010001 bx 010010 mcrf 010011 0...

Page 385: ...100 andls 011101 cmpl 011111 subfx 011111 A 10 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 BO s s s s s s s s s crlD i L D Bl A A A A A A A A A A A SH SH B B B 1000010000 M...

Page 386: ...0 1 0 1 1 1 negx 0 1 1 1 1 1 D A r i 000 1 1 0 1 000 Re lbzux 0 1 1 1 1 1 D A B 000 1 1 1 0 1 1 1 norx 0 1 1 1 1 1 s A B 000 1 1 1 1 1 00 Re subfex 0 1 1 1 1 1 D A B 00 1 000 1 000 Re addex 0 1 1 1 1...

Page 387: ...1 iii addx 011111 D A B 0100001010 Re debt 011111 A B 01000101 1 0 lii lhzx 011111 D A B 01000101 1 1 iM eqvx 011111 s A B 010001 1 100 Re eclwx 011111 B 01001101 1 0 lhzux 011111 D A B 01001 101 1 1...

Page 388: ...10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 D D D s D D D D D D s s s s s s s D s s s s s A A A A A SR A A A t t A _ _ rr r A A A A A A A A A A A A A A B 1000010101 B 1000010110...

Page 389: ...d stbu 100111 s A d lhz 101000 D A d lhzu 101001 D A d Iha 101010 D A d lhau 101011 D A d sth 101100 s A d sthu 101101 s A d lmw 3 101110 D A d stmw 3 101111 s A d Ifs 110000 D A d lfsu 110001 D A d...

Page 390: ...0000001100 Re fctlwx 111111 D B 0000001110 fctlwzx 111111 D B 0000001111 Re fdlvx 111111 fsubx 111111 faddx 111111 fselx 5 111111 D A B C 1 0 1 1 1 Re fmulx 111111 lrsqrtex 5 111111 fmsubx 111111 D A...

Page 391: ...sx 111111 D fabsx mffsx 111111 111111 D A 16 1 Supervisor level instruction 2 Supervisor and user level instruction 3 Load and store string or multiple instruction 4 64 blt Instruction 5 Optional inst...

Page 392: ...e 604 Table A 3 Integer Arithmetic Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addx 31 D A B 266 Re addex 31 D A B 10 Re addex 31 D A B 138 Re addI...

Page 393: ...L A UIMM Table A 5 Integer Logical Instructions Name o 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 andx 31 s A B 28 Re andcx 31 s A B 60 Re andI 28 s A UIMM andls 29 s...

Page 394: ...ame o 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Table A 8 Floating Point Arithmetic Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 2...

Page 395: ...30 31 D A B c 29 Re D A B c 29 Re D A B c 28 Re D A B c 28 Re D A B c 31 Re D A B c 31 Re D A B c 30 Re D A B c 30 Re Table A 10 Floating Point Rounding and Conversion Instructions Name o 5 6 7 8 9 10...

Page 396: ...38 R mtfsfx 31 711 Re mtfsflx 63 134 Re Table A 13 Integer Load Instructions Name o 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lbz lbzu lbzux 34 35 31 D A D A D A lha...

Page 397: ...stwux 31 s A stwx 31 s A Table A 15 Integer Load and Store with Byte Reverse Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lhbrx 31 D A B 790 1 lwbrx...

Page 398: ...28 29 30 31 Table A 19 Floatlng Polnt Load Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lfd 50 D A d lfdu 51 D A d lldux 31 D A B 631 I lfdx 31 D A...

Page 399: ...tructions Name o 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bx bcx bcctrx bclrx Name crand crandc creqv crnand cmor cror crorc crxor mcrf A 24 0 18 LI 16 BO Bl BO 19 B...

Page 400: ...ions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 31 512 mcrxr mfcr 31 D 19 mfmsr 1 31 D 83 mfspr 2 31 D 339 mftb 31 D 371 mtcrf 31 s 144 1 k mtmsr 1 31 s 146 I m...

Page 401: ...uctions Name o 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Table A 30 External Control Instructions Name o 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26...

Page 402: ...30 31 bxl 18 LI MLKI Table A 32 B Form OPCO BO Bl BO l viLKI Specific Instruction Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bcxl 16 BO Bl BO MLKI Table A 33 S...

Page 403: ...46 32 33 7 24 25 38 39 54 55 52 53 44 45 47 Specific Instructions 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 D A SIMM D A SIMM D A SIMM D A SIMM s A UIMM s A UIMM crtD...

Page 404: ...ls 27 s A UIMM Table A 35 OS Form OPCD D A ds I XO I OPCD s A ds XO Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Table A 36 X Form OPCD D A...

Page 405: ...4 25 26 27 28 29 30 31 andx 31 s A B 28 Re andcx 31 s A B 60 Re cmp 31 crfD A B 0 lll dcbf 31 A B 86 1 debI 1 31 A B 470 il debst 31 A B 54 ill debt 31 A B 278 t l dcbtst 31 A B 246 llill dcbz 31 A B...

Page 406: ...t B 136 Re fnegx 63 D Mm B 40 Re frspx 63 D Ji i MF t B 12 Re lebl 31 r g MMI ir A B 982 if lbzux 31 D A B 119 lbzx 31 D A B 87 lfdux 31 D A B 631 lfdx 31 D A B 599 1 lfsux 31 D A B 567 lfsx 31 D A B...

Page 407: ...3 mcrfs 63 64 mcrxr 31 512 mfcr 31 19 mffsx 63 583 Re mfmsr 1 31 83 mfsr 1 31 595 mfsrln 1 31 659 oo mtfsbOx 63 70 Re mtfsb1x 63 38 Re ClfD o ij f f_p_ _ _ _ _ _ _ _ mtfsflx 63 134 Re mtmsr 1 31 146 m...

Page 408: ...3 31 s A NB 725 M stswx 3 31 s A B 661 1 stwbrx 31 s A B 662 m stwcx 31 s A B 150 stwux 31 s A B 183 stwx 31 s A B 151 sync 31 598 tlbsync 1 5 31 li i i il ii J f g g gi 566 iii 1 1 1F 1F I tw 31 TO...

Page 409: ...c 19 150 mcrf 19 0 rft 1 19 50 Table A 38 XFX Fom OPCD D spr XO if OPCD D ll CRM I XO 1 OPCD s spr XO I OPCD D tbr XO Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2...

Page 410: ...A XO Re OPCD D A XO Re Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addx 31 D A B addcx 31 D A B addex 31 D A B addmex 31 D A af l o o negx...

Page 411: ...faddx 63 D A 21 Re faddsx 59 D A 21 Re fdlvx 63 D A 18 Re tdlvsx 59 D A 18 Re fmaddx 63 D A B C 29 Re fmaddsx 59 D A B C 29 Re fmsubx 63 D A B C 28 Re fmsubsx 59 D A B C 28 Re fmulx 63 D A 25 Re fmul...

Page 412: ...sh me XO Specific Instructions Name o 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Table A 45 MDS Fonn OPCD s A B mb XO OPCD s A B me XO Specific Instructions Name o 5 6...

Page 413: ...the 604 A 38 addx addex addex addI addle addle addls addmex addzex andx andex andI andls bx bcx bcctrx bclrx cmp cmpl cmpl cmpll cntlzwx crand erandc UISA Key m Instruction not implemented in the 604...

Page 414: ...Bit Optional Form ereqv XL ernand XL emor XL eror XL erore XL erxor XL debI x debI x debst x debt x debtst x dcbz x dlvwx XO dlvwux XO eclwx x ecowx x elelo x eqvx x extsbx x extshx x Appendix A Power...

Page 415: ...tnegx fnmaddx fnmaddsx tnmsubx fnmsubsx A 40 fresx frspx frsqrtex fselx fsubx fsubsx lcbl lsync lbz lbzu lbzux lbzx UISA VEA OEA Supervisor Level 64 Bit Optional Form A A A A x A A A A x x A A A A A...

Page 416: ...D lfdu D lfdux x lfdx x Ifs D lfsu D lfsux x lfsx x Iha D lhau D lhaux x lhax x lhbrx x lhz D lhzu D lhzux x lhzx x lmw 2 D lswl 2 x lswx 2 x lwbrx x lwz D 1 lwzu D lwzux x lwzx x mcrf XL mcrfs x mcr...

Page 417: ...mlfsx x mlmsr x mlspr 1 XFX mlsr x mlsrln x mltb XFX mtcrl XFX mtlsbOx x mtlsb1x x mtlslx XFL mtlsllx x mtmsr x mtspr 1 XFX mtsr x mtsrln x mum D mullwx XO nandx x negx XO norx x orx x orcx x Ori D o...

Page 418: ...mx SC srwx stb stbu stbux stbx stfd sttdu stfdux stfdx stflwx stfs UISA VEA OEA v v v v v v v v v v v Appendix A PowerPC Instruction Set Listings Supervisor Level 64 Bit Optional Form M M M SC x D D x...

Page 419: ...twcx stwu stwux stwx subfx subfcx subfex subtle subfmex A 44 subfzex sync tw twl UISA VEA OEA Supervisor Level 64 Bit Optional Form v D v x v x v D v x v D v x v x v D v x v x v D v x v x v D v x v x...

Page 420: ...A VEA OEA Supervisor Level 64 Blt Optional Form 11 l l 1 I I II I 1 Supervisor and user level instruction 2 Load and store string or multiple instruction Appendix A PowerPC Instruction Set Listings A...

Page 421: ...ion forms of the PowerPC architecture that are not a result of a nonzero reserved field in the instruction encoding Table B 1 Invalid Fonns Excluding Reserved Flelds rA O rAln rAorrB SPRNot Mnemonic 8...

Page 422: ...ng This table takes into consideration all reserved fields in an instruction that must be zero excluding only those instructions that would become invalid if only bit 31 were set Note that any combina...

Page 423: ...0 15 20 29 10 15 15 20 20 20 25 bcctr x bcctrl x SC x x mcrf x x x sync x addme o J x subfme o x addze o J x subfze o J x neg o J x mulhw u J x cmpl x x cmp x cmpll x x cmpl x extsb x extsh x cntlzw x...

Page 424: ...0 29 10 15 15 20 20 20 25 fmuls x fdlv x fdlvs x frsp x fctlw x fctlwz x fcmpu x x fcmpuo x x mffs x mcrfs x x x mtfsfl x x mtfsf x x mtfsbO x mtfsb1 x lcbl x x lsync x x debt x x dcbtst x x dcbz x x...

Page 425: ...0 20 20 25 mfsrln x x tlble x x mttb x x mttbu x x tlbsync x B 3 Invalid Form with Only Bit 31 Set The following instructions generate invalid instruction forms if only bit 31 is set in the instructio...

Page 426: ...cla heir bclrl bcctr and bcctrl Specifying a conditional branch instruction with one of these fields results in a invalid instruction form Note that entries with the y bit represent two possible instr...

Page 427: ...ased exponent s range non negative Big endian A byte ordering method in memory where the address n of a word corresponds to the most significant byte In an addressed memory word the bytes are ordered...

Page 428: ...icit or implicit leading significand bit is zero E Exception A condition encountered by the processor that requires special Glossary 2 processing Exception handler A software routine that executes whe...

Page 429: ...nes operations of binary floating point arithmetic and representations of binary floating point numbers Interrupt An asynchronous exception K Kill An operation that causes a cache block to be invalida...

Page 430: ...Q s Glossary 4 Pipelining A technique that breaks instruction execution into distinct steps so that multiple steps can be performed at the same time Precise exceptions The pipeline can be stopped so t...

Page 431: ...metic operations when the result cannot be represented accurately in the destination register For example underflow can happen if two floating point fractions are multiplied and the result is a single...

Page 432: ...al 7 4 8 7 Bits used to configure cache 3 15 Block address translation BAT register initialization 5 13 block address translation flow 5 12 selection of block address translation 5 9 Boundeclly undefi...

Page 433: ...e 6 11 completion unit 1 9 definition 6 3 Context synchronization 2 24 COP scan interface 7 29 lndex 2 INDEX CR condition register CR logical instructions 2 45 CR description 2 4 CS El signals 7 15 8...

Page 434: ...6 FP assist exception 4 19 FP unavailable exception 4 4 4 18 instmction address breakpoint exception 4 5 4 20 Index instmction related exceptions 2 25 ISi exception 4 4 machine check 4 3 machine check...

Page 435: ...h address calculation 2 44 branch instructions A 25 cache management A 26 classes 2 21 condition register logical 2 45 A 25 defined instructions 2 21 eieio 2 49 external control instructions 2 52 A 27...

Page 436: ...ion instructions A 24 string instructions 2 39 A 24 Index INDEX Load store wiit execution timing 6 39 overview 1 11 Logical addresses translation into physical addresses 5 1 lwarx stwcx M general info...

Page 437: ...e back stage 6 12 lndex 6 PIR processor identification register 2 8 2 9 PLL configuration 7 31 PMCl and PMC2 registers 2 8 2 13 9 1 9 3 Postdispatch seriali7 ation mode 6 34 Power management nap mode...

Page 438: ...ister 2 6 Segment registers Index INDEX SR description 2 6 SR manipulation instructions 2 55 A 27 Tbit 8 38 Segmented memory model see Memory management unit SHD signal 7 17 SIA and SDA registers 2 8...

Page 439: ...ansfers with data delays 8 36 direct store interface load access 8 47 direct store intelface store access 8 48 single beat reads 8 32 single beat reads with data delays 8 34 single beat writes 8 33 si...

Page 440: ...45 TS signal 7 6 8 12 TSIZO TSIZ2 signals 7 11 8 13 1TO TT4 signals 7 10 8 13 u UISA definition 1 19 registers 2 2 Use ofIBA timing 8 37 User instruction set architecture see UISA Using DBWO timing 8...

Page 441: ...9 TIME TusUn Time Electronics 1 600 789 TIME West Hiiis Newark 818 888 3718 Woodland Hiiis Hamilton Hallmark 818 594 0404 Richardson Electronics 615 594 5600 COLORADO Colorado Springs Newark 719 592 9...

Page 442: ...609 424 0100 Fairfield Newark 201 882 0300 Marlton Arrr JN ScJ r NrbJr Electronics 609 596 8000 Future Electronics 609 596 4080 Plnebrook Arrr JN ScJ r NrbJr Electronics 201 227 7880 Wyle Laboratories...

Page 443: ...Electronics 1 8111 789 TIME Wyle Laboratories 801 974 9953 WASHINGTON Bellewe Almac Electronics Corp 206 643 41992 Newark 206 641 Q800 Richardson Electronics 206 646 7224 Bothell Future Electronics 2...

Page 444: ...604 293 7650 ONTARIO Toronto 416 497 8181 ONTARIO Ottawa 613 226 3491 QUEBEC Montreal 514 333 3300 INTERNATIONAL AUSTRALIA Melbourne 61 3 887 0711 AUSTRALIA Sydney 61 2 906 3855 BRAZIL Sao Paulo 55 11...

Page 445: ...Nortec S 46 87051BOO Avnet Nortec OK 45 42 842 000 Avnet Nortec N 47 6684 21o ITT MultikomponentAB 46 8830 020 SINGAPORE Alexan Commercial 63 2 405 e52 GEIC 65 298 7633 P T Ometraco 62 22 63M05 Shapi...

Page 446: ...9 Fax 800 769 3732 Suite 101 Tel 619 278 4950 Richardson TX 75080 Fax 619 278 0649 131 D Gaither Drive Tel 214 234 8438 Mt Laurel NJ 08054 Fax 214 437 0897 23901 Calabasas Road Tel 609 866 1234 8240 M...

Page 447: ...875 8219 Dayton Military Tel 602 966 3600 Hartford NW Maryland 446 Windsor Park Drive Fax 602 967 6584 1064 East Main Street Baltimore Mid Atlantic Dayton OH 45459 California Meriden CT 06450 8945 Gu...

Page 448: ...24 Suite 1024 Tel 414 547 8879 Sacramento Altamonte Springs FL32701 Fax 414 547 6547 Texas 3039 Kilgore Avenue Tel 407 767 8585 100 North Central Expressway Rancho Cordova CA95670 Ste502 Tel 916 635 9...

Page 449: ...ng Island Austin Toronto Maryland 95 Oser Avenue 8504 Cross Park Drive 4Paget Road Maryland Haupanuge NY 11788 Austin TX 78754 Units 10and 11 2221 Broadbirch Drive Tel 516 273 2695 Tel 512 837 1991 Bu...

Page 450: ...icroelectronics Department 1045 224 Boulevard J F Kennedy 91105 Corbeil Essonnes CEDEX France Tel 33 HiO 88 5167 Fax 33 1 60 88 4920 Germany ITI Distribution Poslfach 1246 Bahnhofstrasse44 D 71693 Mog...

Page 451: ...and Bus Interface Unit Operation Exceptions Memory Management Instruction Timing Signal Descriptions System Interface Operation Performance Monitor PowerPC Instruction Set Listings Invalid Instructio...

Page 452: ...on Exceptions Memory Management Instruction Timing Signal Descriptions System Interface Operation Performance Monitor PowerPC Instruction Set Listing Invalid Instruction Forms Glossary of Terms and Ab...

Page 453: ...ue revisions to your PowerPC microprocessor documents L _________________ _ ear Here__________________ _J IBM Document Card Company Name_______________________ Your Name_______________________ Title _...

Page 454: ...NTHE UNITED STATES I II11I11I1I1lI11111II11II11I1I11I1I1111ll1l11I1I1I11I I L ________________ _ _________ _J II BUSINESS REPLY MAIL FIRST CLASS MAIL PERMIT NO 40 ARMONK NY POSTAGE WILL BE PAID BY ADD...

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