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Summary of Contents for PowerPC 405GP

Page 1: ......

Page 2: ...y PowerPC 405GP Embedded Processor User s Manual Preliminary Volume 1 GK10 3118 03...

Page 3: ...ramming or services that are not announced in your country Such references or information must not be construed to mean that IBM intends to announce such IBM products programming or services in your c...

Page 4: ...license to these patents You can send license inquiries in writing to the IBM Director of Licensing IBM Corporation North Castle Drive Armonk NY 10504 United States of America The following terms are...

Page 5: ...Preliminary...

Page 6: ...8 Debug Modes 1 9 Processor Core Interfaces 1 9 Processor Local Bus 1 9 Device Control Register Bus 1 9 Clock and Power Management 1 9 JTAG 1 9 Interrupts 1 9 On Chip Memory 1 9 Processor Core Progra...

Page 7: ...3 15 Machine State Register MSR 3 15 Device Control Registers 3 16 Directly Accessed DCRs 3 17 Indirectly Accessed DCRs 3 19 Indirect Access of SDRAM Controller DCRs 3 19 Indirect Access of External...

Page 8: ...Storage Synchronization 3 46 Instruction Set 3 47 Instructions Specific to IBM PowerPC Embedded Processors 3 48 Storage Reference Instructions 3 48 Arithmetic Instructions 3 49 Logical Instructions 3...

Page 9: ...B Accesses 6 6 Shadow Data TLB 6 7 DTLB Accesses 6 7 Shadow TLB Consistency 6 8 TLB Related Interrupts 6 9 Data Storage Interrupt 6 9 Instruction Storage Interrupt 6 1 Data TLB Miss Interrupt 6 10 Ins...

Page 10: ...Register Contents after Reset 8 3 Contents of Special Purpose Registers after Reset 8 4 OCR Contents after Reset 8 4 MMIO Register Contents After Reset 8 8 PPC405GP Chip Initialization 8 12 OCM Initi...

Page 11: ...5 Data Machine Check Handling 10 36 Data Storage Interrupt 10 36 Instruction Storage Interrupt 10 38 External Interrupt 10 38 External Interrupt Handling 10 39 Alignment Interrupt 10 39 Program Interr...

Page 12: ...Imprecise Debug Event 12 23 Chapter 13 Clock and Power Management 13 1 CPM Registers 13 1 CPM Enable Register CPCO_ER 13 3 CPM Force Register CPCO_FR 13 3 CPM Status Register CPCO_SR 13 3 Chapter 14 D...

Page 13: ...15 21 Chapter 16 External Bus Controller 16 1 Interface Signals 16 1 Interfacing to Byte Halfword and Word Devices 16 3 Multiplexed II0s 16 4 Driver Enables 16 4 Non Burst Peripheral Bus Transactions...

Page 14: ...rs 17 19 PCI Bridge Register Summary 17 19 PCI Bridge Local Configuration Registers 17 21 PMM Local Address Register PCILO_PMMOLA 17 21 PMM Mask Attribute Register PCILO_PMMOMA 17 22 PMM PCI Low Addre...

Page 15: ...Identifier PCICO_CAPID 17 49 Next Item Pointer PCICO_NEXTIPTR 17 49 Power Management Capabilities PCICO_PMC 17 50 Power Management Control Status Register PCICO_PMCSR 17 50 PMCSR PCI to PCI Bridge Su...

Page 16: ...AO_SGO DMAO_SG3 18 12 DMA Scatter Gather Command Register DMAO_SGC 18 13 Channel Priorities 18 13 Data Parity During DMA Peripheral Transfers 18 14 Errors 18 14 Address Alignment Error 18 14 PLB Timeo...

Page 17: ...ister EMACO_ISR 19 30 Interrupt Status Enable Register EMACO_ISER 19 33 Individual Address High EMACO_IAHR 19 35 Individual Address Low EMACO_IALR 19 36 VLAN TPID Register EMACO_VTPID 19 36 VLAN TCI R...

Page 18: ...th for Receive 20 13 Descriptor Buffer Status Control Fields 20 13 Information from a Software Device Driver Directed To MAL and COMMAC 20 13 Information from MAL and COMMAC Directed to Software 20 14...

Page 19: ...egisters UARTx_MSR 21 13 Scratchpad Registers UARTx_SCR 21 13 Divisor Latch LSB and MSB Registers UARTx_DLL UARTx_DLM 21 14 FIFO Operation 21 15 Interrupt Mode 21 15 Receiver 21 15 Transmitter 21 16 P...

Page 20: ...ster GPIOO_TCR 23 5 GPIO Open Drain Register GPIOO_ODR 23 6 GPIO Input Register GPIOO_IR 23 6 Part V Reference V 1 Chapter 24 Instruction Set 24 1 Instruction Set Portability 24 1 Instruction Formats...

Page 21: ...68 isync 24 70 Ibz 24 71 Ibzu 24 72 Ibzux 24 73 Ibzx 24 74 Iha 24 75 Ihau 24 76 Ihaux 24 77 Ihax 24 78 Ihbrx 24 79 1hz 24 80 Ihzu 24 81 Ihzux 24 82 Ihzx 24 83 Imw 24 84 Iswi 24 85 Iswx 24 87 Iwarx 24...

Page 22: ...24 127 mullhwu 24 128 mulli 24 129 mullw 24 130 nand 24 131 neg 24 132 nmacchw 24 133 nmacchws 24 134 nmachhw 24 135 nmachhws 24 136 nmaclhw 24 137 nmaclhws 24 138 nor 24 139 or 24 140 orc 24 141 ori...

Page 23: ...ral Purpose Registers 25 1 Machine State Register and Condition Register 25 1 Special Purpose Registers 25 1 Time Base Registers 25 3 Device Control Registers 25 4 Directly Accessed DCRs 25 4 Indirect...

Page 24: ...5 58 DMAO_DAQ DMAO_DA3 25 59 DMAO_POL 25 60 DMAO_SAQ DMAO_SA3 25 62 DMAO_SGQ DMAO_SG3 25 63 DMAO_SGC 25 64 DMAO_SLP 25 65 DMAO_SR 25 66 DVCR1 DVCR2 25 67 EBCO_BEAR 25 68 EBCO_BESRO 25 69 EBCO_BESR1 25...

Page 25: ...123 MALO_RXCASR 25 124 MALO_RXCTPxR 25 125 MALO_RXDEIR 25 126 MALO_RXEOBISR 25 127 MALO_TXCARR 25 128 MALO_TXCASR 25 129 MALO_TXCTPxR 25 130 MALO_TXDEIR 25 131 MALO_TXEOBISR 25 132 MSR 25 133 OCMO_DSA...

Page 26: ...ICO_VENDID 25 181 PCILO_PMMOLA 25 182 PCILO_PMMOMA 25 183 PCILO_PMMOPCIHA 25 184 PCILO_PMMOPCILA 25 185 PCILO_PMM1 LA 25 186 PCILO_PMM1MA 25 187 PCILO_PMM1PCIHA 25 188 PCILO_PMM1PCILA 25 189 PCILO_PMM...

Page 27: ...247 UARTx_MSR 25 248 UARTx_RBR 25 249 UARTx_SCR 25 250 UARTx_THR 25 251 UICO_CR 25 252 UICO_ER 25 255 UICO_MSR 25 258 UICO_PR 25 261 UICO_SR 25 264 UICO_TR 25 267 UICO_VCR 25 270 UICO_VR 25 271 USPRGO...

Page 28: ...ol Instructions B 41 Interrupt Control Instructions B 42 Processor Management Instructions B 42 C Code Optimization and Instruction Timings C 1 Code Optimization Guidelines C 1 Condition Register Bits...

Page 29: ...xxviii PPC405GP User s Manual Preliminary...

Page 30: ...rd Load or Store Big Endian Storage Region 3 32 Figure 3 12 Byte Reverse Word Load or Store Little Endian Storage Region 3 32 Figure 3 13 Byte Reverse Word Load or Store Big Endian Storage Region 3 33...

Page 31: ...Connector Physical Layout Top View 12 2 Figure 12 2 JTAG ID Register CPCO_JTAGID 12 4 Figure 12 3 RISCTrace Header Top View 12 5 Figure 12 4 Debug Control Register 0 DBCRO 12 9 Figure 12 5 Debug Cont...

Page 32: ...Single Read Transfer 16 12 Figure 16 8 Device Paced Single Write Transfer 16 13 Figure 16 9 Device Paced Burst Read Transfer 16 14 Figure 16 10 Device Paced Burst Write Transfer 16 16 Figure 16 11 Sam...

Page 33: ...r Register PCICO_LATTIM 17 36 Figure 17 33 PCI Header Type Register PCICO_HDTYPE 17 37 Figure 17 34 PCI Built in Self Test Control Register PCICO_BIST 17 37 Figure 17 35 PCI PTM 1 BAR Register PCICO_P...

Page 34: ...igure 18 6 DMA Source Address Registers DMAO_SAQ DMAO_SA3 18 11 Figure 18 7 DMA Destination Address Registers DMAO_DAO DMAO_DA3 18 11 Figure 18 8 DMA Count Registers DMAO_CTO DMAO_CT3 18 12 Figure 18...

Page 35: ...gure 20 2 MAL Internal Structure 20 3 Figure 20 3 Transmit Operation 20 5 Figure 20 4 Receive Operation 20 6 Figure 20 5 Buffer Descriptor Structure 20 8 Figure 20 6 Packet Memory Structure 20 9 Figur...

Page 36: ...2 Figure 22 12 IICO Low Slave Address Register IICO_LSADR 22 14 Figure 22 13 IICO High Slave Address Register IICO_HSADR 22 15 Figure 22 14 IICO Clock Divide Register IICO_CLKDIV 22 15 Figure 22 15 II...

Page 37: ...66 Figure 25 36 Data Value Compare Registers DVC1 DVC2 25 67 Figure 25 37 Peripheral Bus Error Address Register EBCO_BEAR 25 68 Figure 25 38 Peripheral Bus Error Status Register EBCO_BESRO 25 69 Figur...

Page 38: ...Interrupt Register MALO_RXDEIR 25 126 Figure 25 85 RX End of Buffer Interrupt Status Register MALO_RXEOBISR 25 127 Figure 25 86 TX Channel_Active Reset Register MALO_TXCARR 25 128 Figure 25 87 TX Chan...

Page 39: ...5 175 Figure 25 130 PCI Revision ID Register PCICO_REVID 25 176 Figure 25 131 PCI Subsystem ID Register PCICO_SBSYSID 25 177 Figure 25 132 PCI Subsystem Vendor ID Register pCICO_SBSYSVID 25 178 Figure...

Page 40: ...r 1 SRR1 25 230 Figure 25 175 Save Restore Register 2 SRR2 25 231 Figure 25 176 Save Restore Register 3 SRR3 25 232 Figure 25 177 Storage User defined 0 Register SUOR 25 233 Figure 25 178 Time Base Lo...

Page 41: ...e 25 204 Zone Protection Register ZPR 25 274 Figure A 1 I Instruction Format A 44 Figure A 2 B Instruction Format A 44 Figure A 3 SC Instruction Format A 44 Figure A 4 D Instruction Format A 44 Figure...

Page 42: ...MMIO Registers 3 22 Table 3 14 PCI Configuration Address and Data Registers 3 25 Table 3 15 PCI Configuration Registers 3 25 Table 3 16 Alignment Exception Summary 3 28 Table 3 17 Bits of the BO Fiel...

Page 43: ...gister Settings during Critical Input Interrupts 10 35 Table 10 8 Register Settings during Machine Check Instruction Interrupts 10 36 Table 10 9 Register Settings during Machine Check Data Interrupts...

Page 44: ...Addresses 16 23 Table 16 6 External Bus Configuration and Status Registers 16 23 Table 17 1 PowerPC CoreConnect PLB and PCI Address Bit Naming Conventions 17 3 Table 17 2 PowerPC CoreConnect PLB and...

Page 45: ...ed Mnemonics for bcctr bcctrl 24 27 Table 24 9 Extended Mnemonics for bclr bclrl 24 30 Table 24 10 Extended Mnemonics for cmp 24 34 Table 24 11 Extended Mnemonics for cmpi 24 35 Table 24 12 Extended M...

Page 46: ...1 Alphabetical Signal List 26 1 Table 26 2 Signal Descriptions 26 5 Table A 1 PPC405GP Instruction Syntax Summary A 1 Table A 2 PPC405GP Instructions by Opcode A 33 Table B 1 PPC405GP Instruction Set...

Page 47: ...xlvi PPC405GP User s Manual Preliminary...

Page 48: ...should understand embedded processor design embedded system design operating systems RISC processing and design for testability How to Use This Book This book describes the PPC405GP device architectur...

Page 49: ...ruction Summary Appendix B Instructions by Category Appendix C Code Optimization and Instruction Timings To help readers find material in these chapters the book contains Contents on page v Figures on...

Page 50: ...n or register field A range of bits in a named instruction or register field A list of bits by number or name in a named instruction or register field A bit in a named register A range of bits in a na...

Page 51: ...next instruction to be executed In pseudocode a successful branch is indicated by assigning a value to NIA For instructions that do not branch the NIA is CIA 4 The number of bytes represented by n at...

Page 52: ...Part I Introducing the PPC405GP Embedded Processor Preliminary 1 1...

Page 53: ...1 2 PPC405GP User s Manual Preliminary...

Page 54: ...o serial ports Inter integrated circuit IIC interface General purpose input output GPIO In addition the PPC405GP supports CodePack a code compression scheme that can significantly reduce application c...

Page 55: ...aching one cycle per instruction On chip instruction and data caches reduce chip count and design complexity in systems and improve system throughput 1 1 1 Bus and Peripheral Features The PPG405GP mul...

Page 56: ...rty two 32 bit general purpose registers GPRs Static branch prediction Five stage pipeline with single cycle execution of most instructions including loads stores Unaligned load store support to cache...

Page 57: ...external time base clock input Debug Support Enhanced debug support with logical operators Four instruction address compares lACs Two data address compares DACs Two data value compares DVCs JTAG inst...

Page 58: ...ented in PowerPC processors such as the 6xxl7xx family The PPC405GP processor core also provides a number of optimizations and extensions to these layers of the PowerPC Architecture The full architect...

Page 59: ...reduced by forwarding the requested word to the CPU during the line fill Single queued flushes are non blocking When a flush operation is pending the DCU can continue to access the array to determine...

Page 60: ...side and 8 data side TLB entries are kept in shadow arrays The shadow arrays prevent TLB contention Hardware manages the replacement and invalidation of shadow TLB entries no system software action is...

Page 61: ...ed in the TCR The watchdog timer generates a periodic interrupt based on selected bits in the time base Users can select one of four time periods for the interval and the type of reset generated if th...

Page 62: ...of a debug tool such as the RISCWatch product from IBM Microelectronics Through the JTAG test access port a debug tool can single step the processor and interrogate internal processor state to facilit...

Page 63: ...e Registers The processor core contains 32 GPRs each register contains 32 bits The contents of the GPRs can be transferred from memory using load instructions and stored to memory using store instruct...

Page 64: ...e not architected are useq to control configure and hold status for various functional units that are not part of the processor core 1 5 4 Addressing Modes The processor core supports the following ad...

Page 65: ...1 12 PPC405GP User s Manual Preliminary...

Page 66: ...are available from your IBM representative and in the IBM Microelectronics technical library www chips ibm com describe the on chip bus architecture The CoreConnectrM Bus Architecture Processor Local...

Page 67: ...d Slaves PLB Agent PLB Master Slave Processor core ICU Master Processor core DCU Master External bus master interface Master Static memory peripherals Slaves PCI bridge PCI to PLB Master PCI bridge PL...

Page 68: ...que priorities can be DMAO_CR1 CP assigned to each DMA DMAO_CR2 CP channel DMAO_CR3 CP See PLB Arbiter Control Register PLBO_ACR on page 2 5 for information about programming the PLBO_ACR to control P...

Page 69: ...Address pipelining reduces overall bus latency on the PLB by enabling the latency associated with a new transfer request to be overlapped with an ongoing data transfer in the same direction PLB maste...

Page 70: ...B priority order PPM HBU Figure 2 2 PLB Arbiter Control Register PLBO_ACR 0 PPM PLB Priority Mode oFixed 1 Fair 1 3 PPO PLB Priority Order 000 Masters 0 1 2 3 4 5 001 Masters 1 2 3 4 5 0 010 Masters 2...

Page 71: ...PTE3 FLK3 PTE4 FLK4 PTE5 FLK5 Figure 2 4 PLB Error Status Register PLBO_BESR 0 PTEO Master 0 PLB Timeout Error Status Master 0 is the processor core ICU o No master 0 timeout error 1 Master 0 timeout...

Page 72: ...3 ReadIWrite Status Master 3 error operation was a write 1 Master 3 error operation was a read 14 FLK3 Master 3 PLBO_BESR Field Lock Master 3 PLBO_BESR field is unlocked 1 Master 3 PLBO_BESR field is...

Page 73: ...e address of a PLB to OPB transfer that results in an error The PLB to OPB bridge writes the error address in the POBO_BEAR unless the associated POBO_BESRm ALCKn field is set m is either aor 1 depend...

Page 74: ...address is locked 5 6 PTE1 PLB Timeout Error Status Master 1 Master 1 is the processor core DCU 00 No master 1 error occurred 01 Master 1 timeout error occurred 10 Master 1 slave error occurred 11 Res...

Page 75: ...Lock Master 3 Master 3 POBO_BESRO field is unlocked 1 Master 3 POBO_BESRO field is locked 19 ALK3 POBO_BEAR Address Lock Master 3 Master 3 POBO_BEAR address is unlocked 1 Master 3 POBO_BEAR address is...

Page 76: ...1 7 3 On Chip Peripheral Bus The OPB is used to attach peripherals that do not require the bandwidth of the PLB The OPB does not connect directly to the PPC405GP processor core which accesses peripher...

Page 77: ...Mnemonic Register Name Address Access OPBAO_CR OPB Arbiter Control Register OxEF600601 RIW OPBAO_PR OPB Arbiter Priority Register OxEF600600 RIW 2 1 10 1 OPB Arbiter Control Register OPBAO_CR Page 2...

Page 78: ...se the PPC405 provides two masters master IDs 1 and 3 are ignored At reset master ID 0 DMA has a higher priority than master 2 OPB to PLB bridge MIDO 1 Figure 2 9 OPB Arbiter Priority Register OPBAO_P...

Page 79: ...2 14 PPC405GP User s Manual Preliminary...

Page 80: ...Part II The PPC405GP RISC Processor Preliminary 11 1...

Page 81: ...11 2 PPC405GP User s Manual Preliminary...

Page 82: ...gisters comprise the privileged programming model In user mode certain registers and instructions are unavailable to programs This is also called the problem state Those registers and instructions tha...

Page 83: ...6MB PCI Local Configuration Registers OxEF400000 OxEF40003F 64B I Reserved OxEF400040 OxEF5FFFFF 2MB 64B Internal Peripherals Total OxEF600000 OxEFFFFFFF 10MB UARTO Registers OxEF600300 OxEF600307 8B...

Page 84: ...h Register DCWR Data Cache Cachability Register DCCR Instruction Cache Cachability Register ICCR Storage Guarded Register SGR Storage Little Endian Register SLER Storage User defined 0 Register SUOR E...

Page 85: ...m all subsequent writes to the register using a read modify write strategy read the register use logical instructions to alter defined fields leaving reserved fields unmodified and write the register...

Page 86: ...isters Exception Vector Prefix Register EVPR I SPR Ox3D5 Exception Syndrome Register ESR I SPR Ox3D4 Data Exception Address Register DEAR I SPR Ox3D5 Save Restore Registers SRRO SRR1 SRR2 SRR3 SPR Ox0...

Page 87: ...ons SPRs control the operation of debug facilities timers interrupts storage control attributes and other architected processor resources Table 25 2 Special Purpose Registers on page 25 2 shows the mn...

Page 88: ...RO SRR1 I Privileged 10 29 SRR2 SRR3 I Privileged 10 30 Processor Version PVR Privileged read only 3 12 DCCR Privileged 6 17 DCWR Privileged 6 17 ICCR Privileged 6 17 Storage Attribute Control SGR Pri...

Page 89: ...uction This allows branching to any address When the LR contents represent an instruction address LR30 31 are assumed to be 0 because all instructions must be word aligned However when LR is read usin...

Page 90: ...s the exclusive or of the carry in and the carry out is 1 The following instructions set XER OV differently The specific behavior is indicated in the instruction descriptions in Chapter 24 Instruction...

Page 91: ...xr or by arithmetic instructions that update the CA field 3 24 1 Reserved I 25 31 TBC Transfer Byte Count Used by Iswx and stswx written by mtspr Table 3 3 and Table 3 4 list the PPC405GP instructions...

Page 92: ...orage locations For example an interrupt handler might save the contents of a GPR to an SPRG and later restore the GPR from it This is faster than a save restore to a memory location These registers a...

Page 93: ...d in conditional branch instructions The CR can be modified in any of the following ways mtcrf sets specified CR fields by writing to the CR from a GPR under control of a mask specified as an instruct...

Page 94: ...o all 32 bits represent magnitude There is no sign bit As an example consider the comparison of 0 with OxFFFF FFFF In an arithmetic compare 0 is larger because OxFFFF FFFF represents 1 in a logical co...

Page 95: ...uch an arithmetic comparison to 0 although the result of such a logical operation is not actually an arithmetic result If an arithmetic overflow occurs the sign of an instruction result indicated in C...

Page 96: ...ead only 3 3 5 Machine State Register MSR The Machine State Register MSR controls processor core functions such as the enabling or disabling of interrupts and address translation The MSR is written fr...

Page 97: ...Reserved 26 IR Instruction Relocate o Instruction address translation is disabled 1 Instruction address translation is enabled 27 DR Data Relocate oData address translation is disabled 1 Data address...

Page 98: ...84 R Clear PLB Bus Error Status Register PLBO_BEAR Ox086 RIW PLB Bus Error Address Register PLBO_ACR Ox087 RIW PLB Arbiter Control Register POBO_BESRO OxOAO R Clear PLB to OPB Bus Error Status Registe...

Page 99: ...Ox11B RIW DMA Source Address Register 3 DMAO_SG3 Ox11C RIW DMA Scatter Gather Descriptor Address DMAO_SR Ox120 R Clear DMA Status Register DMAO_SGC Ox123 RIW DMA Scatter Gather Command Register DMAO_S...

Page 100: ...Memory Controller Data Register Table 3 8 Offsets for SDRAM Controller Registers Register Offset RIW Description SDRAMO_BESRO OxOO R Clear Bus Error Syndrome Register 0 SDRAMO_BESR1 Ox08 R Clear Bus E...

Page 101: ...IW Peripheral Bank 3 Configuration Register EBCO_B4CR Ox04 RIW Peripheral Bank 4 Configuration Register EBCO_B5CR Ox05 RIW Peripheral Bank 5 Configuration Register EBCO_B6CR Ox06 RIW Peripheral Bank 6...

Page 102: ...egister Offset RIW Description DCPO_ITORO OxOO RIW Index Table Origin Register 0 DCPO_ITOR1 Ox01 RIW Index Table Origin Register 1 DCPO_ITOR2 Ox02 RIW Index Table Origin Register 2 DCPO_ITOR3 Ox03 RIW...

Page 103: ...4 RIW PMM 1 Mask Attribute PCILO_PMM1 PCILA OxEF400018 RIW PMM 1 PCI Low Address PCILO_PMM1 PCIHA OxEF40001C RIW PMM 1 PCI High Address PCILO_PMM2LA OxEF400020 RIW PMM 2 Local Address PCILO_PMM2MA OxE...

Page 104: ...RT1_MCR OxEF600404 RIW UART 1 Modem Control Register UART1_LSR OxEF600405 RIW UART 1 Line Status Register UART1_MSR OxEF600406 RIW UART 1 Modem Status Register UARTLSCR OxEF600407 RIW UART 1 Scratch R...

Page 105: ...ress Low EMACO_VTPID OxEF600824 RIW VLAN TPID Register EMACO_VTCI OxEF600828 RIW VLAN TCI Register EMACO_PTR OxEF60082C RIW Pause Timer Register EMACO_IAHT1 OxEF600830 RIW Individual Address Hash Tabl...

Page 106: ...ription PCICO_VENDID Ox01 0xOO RIW R PCI Vendor ID PCICO_DEVID Ox03 0x02 RIW R PCI Device ID PCICO_CMD Ox05 0x04 RIW RIW PCI Command Register PCICO_STATUS Ox07 0x06 RIW RIW PCI Status Register PCICO_R...

Page 107: ...nused Data PCICO_BRDGOPT2 Ox63 0x60 R W RIW PCI Bridge Options 2 PCICO_PMSCRR Ox64 RIW RIW Power Management State Change Request Register 3 4 Data Types and Alignment The data types consist of bytes e...

Page 108: ...erence instruct ons and the dcread instruction depend on the particular instruction Table 3 16 Alignment Exception Summary on page 3 28 summarizes the instructions that cause alignment exceptions The...

Page 109: ...igh order eight bits of a scalar is the same as the address of any other byte of the scalar For the PowerPC Architecture as for most computer architectures currently implemented the smallest addressab...

Page 110: ...s natural boundary This alignment introduces padding of four bytes between a and b one byte between d and e and two bytes between e and f The same amount of padding is present in both big endian and l...

Page 111: ...is associated with the storage region of the reference The E attribute specifies whether that region is organized as big endian E 0 or little endian E 1 When address translation is enabled MSR IR 1 or...

Page 112: ...roper order when an instruction is transferred from the ICU to the decode stage of the pipeline If a storage region is reprogrammed from one endian format to the other the storage region must be reloa...

Page 113: ...nstructions move the more significant bytes of a register to and from the lower numbered memory addresses The load store with byte reverse instructions move the more significant bytes of the register...

Page 114: ...he byte reverse load store instructions so these instructions are ordinarily used only in device drivers written in hand coded assembler Compilers can however take full advantage of the endian storage...

Page 115: ...rocessing The PPC405GP which provides a variety of conditional and unconditional branching instructions uses the branch prediction techniques described in Branch Prediction on page 3 35 3 7 1 Uncondit...

Page 116: ...instruction specifies the conditions used to control branching and specifies how the branch affects the CTA Conditional branch instructions can test one bit in the CA This option is selected when 80...

Page 117: ...a branch is taken before all information necessary to determine the branch direction is available This decision is called a branch prediction The fetcher can then prefetch instructions starting at the...

Page 118: ...not allowed The PowerPC Architecture requires assemblers to provide a way to conveniently control branch prediction For any conditional branch mnemonic a suffix may be added to the mnemonic to contro...

Page 119: ...on is placed in PFBO or PFB1 If the fetched instruction is at the end of a cache line and if PFB1 is empty the fetcher requests the next cache line The instruction at the beginning of the cache line i...

Page 120: ...cognize the rfi as a break in the program flow and speculatively fetches the target of the bctr which is really the first instruction of a subroutine that has not been called Therefore the CTR might c...

Page 121: ...3 19 shows two address regions of the PPC405GP Suppose a system designer can map all liD devices and all ROM and SRAM devices into any location in either region The choices made by the designer can p...

Page 122: ...en it is safe to fetch down the target path 3 9 Privileged Mode Operation In the PowerPC Architecture several terms describe two operating modes that have different instruction execution privileges Wh...

Page 123: ...t CTR LR XER See Privileged SPRs on page 3 42 rfci rfi tibia tlbre tlbsx tlbsync tlbwe wrtee wrteei 3 9 3 Privileged SPRs All SPRs are privileged except for the LR the CTR the XER USPRGO and read acce...

Page 124: ...struction reverses the subfields resulting in the following SPRF field Ob11 01 000000 The most significant bit is 1 SRRO is privileged When an SPR number is considered as a hexadecimal number the seco...

Page 125: ...CRs are not considered as part of the processor context managed by a context synchronizing operation DCRs are not part of the processor core and are analogous to memory mapped registers Their context...

Page 126: ...mation Instruction cache state is part of context A context synchronization operation is required to guarantee instruction cache access ordering 3 Consider the following instruction sequence which is...

Page 127: ...e the new MSR value we have to insert a context synchronization operation such as isync Note that the PowerPC Architecture requires MSR EE the external interrupt bit to be in effect execution synchron...

Page 128: ...s of each instruction Appendix A Instruction Summary alphabetically lists each instruction and extended mnemonic and provides a short form description Appendix B Instructions by Category provides shor...

Page 129: ...e wrtee wrteei 3 11 2 Storage Reference Instructions Table 3 23 lists the PPG405GP storage reference instructions Load store instructions transfer data between memory and the GPRs These instructions o...

Page 130: ...ion word Most arithmetic instructions have versions that can update CR CRO and XER SO OV based on the result of the instruction Some arithmetic instructions also update XER CA implicitly See Condition...

Page 131: ...s 0 mullhwu machhwsu 0 machhwu 0 maclhw o maclhws o maclhwsu 0 maclhwu o 3 11 4 Logical Instructions Table 3 26 lists the PPC405GP logical instructions In the table the syntax indicates that the instr...

Page 132: ...n and a relative form in which the target address is formed by adding the immediate field to the address of the branch instruction Table 3 28 Branch Instructions Branch 3 11 6 1 CR Logical Instruction...

Page 133: ...instruction cache blocks Instructions are also provided to fill flush invalidate or zero data cache blocks where a block is defined as a 32 byte cache line Table 3 32 lists the PPC405GP cache manageme...

Page 134: ...e PPC405GP Table 3 35 Processor Management Instructions elelo mcrxr mtcrf Isync mfcr mtdcr sync mfdcr mtspr mfspr sc tw twl 3 11 10 Extended Mnemonics In addition to mnemonics for instructions support...

Page 135: ...ted hardware instruction mnemonics Appendix A Instruction Summary lists extended mnemonics alphabetically along with the hardware instruction mnemonics Table 8 5 in Appendix 8 Instructions by Category...

Page 136: ...as 4 or 8 words line or half line Bypass path for critical words Non blocking cache for hits during fills Flash invalidate one instruction invalidates entire cache Programmable allocation for fetch fi...

Page 137: ...structions Two way Set Way A Way 8 Way A Way 8 AO 21 Line 0 A AO 21 Line 0 B Line 0 A Line 0 B AO 21 Line 1 A AO 21 Line 1 B Line 1 A Line 1 B AO 21 Line 254 A AO 21 Line 254 B Line 254 A Line 254 B A...

Page 138: ...ed sequentially to the last word of the line The bypass path handles instructions in cache inhibited memory and improves performance during line fill operations If a request from the fetcher obtains a...

Page 139: ...configured for the required cachability 4 1 3 Instruction Cache Synonyms The following information applies only if instruction address translation is enabled MSR IR 1 and 1KB or 4KB page sizes are us...

Page 140: ...s for ICU synchronization when self modifying code is used or if a peripheral device updates memory containing instructions The following code example illustrates the necessary steps for self modifyin...

Page 141: ...e completed in one cycle For loads GPRs receive the requested byte halfword or word of data from the data cache array The DCU supports byte writeability to improve the performance of byte and halfword...

Page 142: ...using dcbf or dcbst instructions The write back strategy minimizes the amount of external bus activity and avoids unnecessary contention for the external bus between the ICU and the DCU The write back...

Page 143: ...a cachability is controlled by the Data Cache Cachability Register DCCR Each bit in the DCCR DCCR SO S31 controls the cachability of a 128MB region see Real mode Storage Attribute Control on page 6 17...

Page 144: ...bi icbt Instruction Cache Block Invalidate Invalidates a cache block Instruction Cache Block Touch Initiates a block fill enabling a program to begin a cache block fetch b efore the program needs an i...

Page 145: ...und in the cache and is not marked modified the line is marked invalid but is not flushed This operation is performed regardless of whether the address is marked cachable debi Data Cache Block Invalid...

Page 146: ...e Cache Control and Debugging Features on page 4 11 This is a privileged instruction 4 4 Cache Control and Debugging Features Registers and instructions are provided to control cache operation and hel...

Page 147: ...bles the UO exception 15 LOBE Load Debug Enable o Load data is invisible on data side on chip memory OCM 1 Load data is visible on data side OCM 16 19 Reserved 20 PFC ICU Prefetching for Cachable Regi...

Page 148: ...PP FWOA Turn off interrupts mfmsr RM addis RZ rO Ox0002 CE bit ori RZ RZ Ox8000 EE bit andc RZ RM RZ Turn off MSR CE EE mtmsr RZ sync sync Touch code sequence into i cache addis RX rO seq1 h ori RX RX...

Page 149: ...RM RZ Turn off MSR CE EE mtmsr RZ sync sync Alter CCRO bits mfspr RN CCRO Read CCRO andi ori RN RN OxXXXX Execute and or function to change any CCRO bits mtspr CCRO RN Update CCRO isync Refetch instru...

Page 150: ...m an icread instruction to arrive before attempting to use the contents the ICDBDR The following code sequence ensures proper results icread r5 r6 read cache information isync ensure completion of icr...

Page 151: ...DCU can immediately perform the requested cache operation no pipeline stall occurs In some cases however the DCU cannot immediately perform the requested cache operation and the pipeline stalls until...

Page 152: ...tion is complete The pipeline stalls when on chip memory OCM asserts a hold signal For loads or stores that are held the DCU can still accept one additional load or store command before stalling the p...

Page 153: ...it is requested and that the data is returned during the cycle after the load is accepted Similarly when a store to a non cachable storage region is followed by multiple stores to non cachable region...

Page 154: ...it ICU and data cache unit DCU as appropriate to ensure that no addresses to be programmed as OCM space are in the cache After programming the OCM address and control registers the OCM address space s...

Page 155: ...4KB SRAM Aliased addresses refer to the same physical memory locations Programming Note To avoid possible memory coherency problems when using aliased addresses align aliased addresses on 16KB bounda...

Page 156: ...lowest priority For example instructions fetched from OCM that contain several sequential data side loads accessing OCM can result in bubbles in the instruction pipeline The sequential data side load...

Page 157: ...or when address aliasing is used Table 5 1 Examples of Store Data Bypass Example Store Address Load Address 4KB Allased 16KB Allased Bypass Address Address 1 OxOOOO0100 OxOOOO0100 Same Same Yes 2 OxOO...

Page 158: ...ented with instruction fetch requests OCMO_ISARC ISAR is compared to the high order 6 bits of the requested instruction address providing a 64MB address space The address space can be shared with or d...

Page 159: ...complete in one cycle OCMO_ISCNTL ISTCM does not affect data side OCM operation ISEN 311 t ISTeM Figure 5 3 OCM Instruction Side Control Register OCMO_ISCNTL 0 ISEN Instruction Side OCM Enable o Instr...

Page 160: ...data loads and stores within the data side OCM address range defined by OCMO_DSARC DSAR At reset OCMO_DSCNTL DSEN 0 data side OCM is not enabled If data side OCM is to be accessed this field must be...

Page 161: ...5 8 PPC405GP User s Manual Preliminary...

Page 162: ...d restart the faulting instruction The MMU divides storage into pages A page represents the granularity of EA translation and protection controls Eight page sizes 1 KB 4KB 16KB 64KB 256KB 1MB 4MB 16MB...

Page 163: ...ully associative TLB in which any page entry TLB entry can be placed anywhere in the TLB TLB entries are maintained under program control System software determines the TLB entry replacement strategy...

Page 164: ...y describes a page that is enabled for translation and access controls Fields in the TLB entry fall into four categories Information required to identify the page to the hardware translation mechanism...

Page 165: ...ID 8 bits Loaded from the PID register during a tlbwe operation The TID value is compared with the PID value during a TLB access The TID provides a convenient way to associate a translation with one o...

Page 166: ...py of the data and the external memory location Contrast this with a write back strategy which updates memory only when a cache line is flushed In real mode the Data Cache Write through Register DCWR...

Page 167: ...n the associated page This storage attribute controls CodePack decompression for a page In real mode the Storage User defined 0 Register SUOR controls the setting of the UO storage attribute E endian...

Page 168: ...ves as the level 2 data side TLB The DTLB is used only by instructions in execute for storing data address translations Each DTLB entry contains the translation information for a page The processor us...

Page 169: ...Address Translation Enabled MSR DR 1 Translation Disabled MSR DR 0 I Side TLB Miss or D Side TLB Miss Exception Figure 6 3 ITLB DTLB UTLB Address Resolution 6 3 4 2 Shadow TLB Consistency The processo...

Page 170: ...ware to implement paged virtual memory and to enforce protection of specified memory pages When an interrupt occurs the processor clears MSR IR DR Therefore at the start of all interrupt handlers the...

Page 171: ...Protection on page 6 13 for a detailed discussion of zone protection See Instruction Storage Interrupt on page 10 38 for a detailed discussion of the instruction storage interru pt 6 4 3 Data TLB Mis...

Page 172: ...can be accessed for reading and writing by tlbre and tlbwe respectively Separate extended mnemonics are available for the TLBHI tag and TLBLO data portions of a TLB entry 6 5 3 TLB Invalidate Instruc...

Page 173: ...the page using the TLB entry after the entry is made valid causes a data storage interrupt because write access was turned off The TLB miss handler records the write to the page in a data structure f...

Page 174: ...6 7 1 3 Write Permissions If MSR DR 1 data loads and stores are subject to MMU translation and are afforded MMU access protection The existence of a TLB entry describing a memory page implies read acc...

Page 175: ...state MSR PR 0 00 No access 00 Access controlled by applicabl 01 Access controlled by applicable TLB_entry EX WR TLB_entry EX WR 01 Access controlled by applicable 10 Access controlled by applicable T...

Page 176: ...ch the cache control instructions can cause data storage interrupts Table 6 2 Protection Applied to Cache Control Instructions Possible Data Storage interrupt Instruction When ZPR Zn 00 When TLB_entry...

Page 177: ...tore was performed to update the cache and debf or debst only update main memory Therefore neither debf nor debst can cause data storage interrupts when TLB_entry WR O Because neither instruction is p...

Page 178: ...support for data coherency These SPRs called storage attribute control registers control the various storage attributes when address translation is disabled When address translation is enabled these...

Page 179: ...FFF 7 Ox3800 0000 Ox3FFF FFFF 23 OxB800 0000 OxBFFF FFFF 8 Ox4000 0000 Ox47FF FFFF 24 OxCOOO 0000 OxC7FF FFFF 9 Ox4800 0000 Ox4FFF FFFF 25 OxC800 0000 OxCFFF FFFF 10 Ox5000 0000 Ox57FF FFFF 26 OxDOOOO...

Page 180: ...he ICCR it is necessary to execute the iccci instruction This invalidates all congruence classes The ICCR can then be reconfigured and the ICU can begin normal operation 6 8 1 4 Storage Guarded Regist...

Page 181: ...6 20 PPC405GP User s Manual Preliminary...

Page 182: ...Part III PPC405GP System Operations Preliminary 111 1...

Page 183: ...111 2 PPC405GP User s Manual Preliminary...

Page 184: ...l in Chapter 26 Signal Summary Clock Generation Divides r CPU Clock PLL MemClkOutO 1 I PLB Clock SysClk ___I FBK DIV Tuning Bits UARTSerClk e TmrClk e Timersl _ _ _ _ _ _ _ _ _ _ _ _ _ _ J Figure 7 1...

Page 185: ...f 66 MHz and a minimum VCO frequency of 400MHz M decreases as the reference clock frequency increases 7 2 Input Reference Clock SysClk The input reference clock SysClk must be between 25 MHz and 66 MH...

Page 186: ...vide ratios 3 4 or 6 These ratios are the only acceptable ratios PLL Feedback Divide Ratio These bits indicate one of four valid PLL feedback divide ratios CPCO_PSR PFBD 1 2 3 or 4 00 Divide by 1 01 D...

Page 187: ...CGs with the PPC405GP visit the technical documents area of the IBM PowerPC web site Table 7 2 PLL Tuning Settings M Range Recommended Choice CPCO_PSR PT Value Equivalent TUNE 5 0 6 M 7 3 010 010011 7...

Page 188: ...400 100 100 4 1 4 16 533 133 133 4 2 2 16 533 133 66 4 2 3 24 800 200 100 4 3 1 12 400 100 33 4 3 2 24 800 200 66 4 4 1 16 533 133 33 6 1 2 12 400 66 66 6 1 3 18 600 100 100 6 1 4 24 800 133 133 6 2 1...

Page 189: ...2 2 16 400 100 50 4 2 3 24 600 150 75 4 2 4 32 800 200 100 4 3 2 24 600 150 50 4 4 1 16 400 100 25 4 4 2 32 800 200 50 6 1 3 18 450 75 75 6 1 4 24 600 100 100 6 2 2 24 600 100 50 6 3 1 18 450 75 25 6...

Page 190: ...ific part number 7 5 PCI Clocking The PPC405GP PCI interface can run synchronously or asynchronously relative to the on chip PLB The state at reset of the PCI Asynchronous Mode Enable PAME strapping p...

Page 191: ...I clock Select an appropriate PCI PLB ratio to maintain the relationship AsyncPC c ock 5 SyncPC c ock 5 2 x AsyncPC c ock 1MHz Table 7 6 lists supported and commonly used combinations of synchronous a...

Page 192: ...oblem The strapping pin selection needed to set an acceptable synchronous PCI clock for a 33 MHz asynchronous PCI clock differs from the strapping pin selection for a 66 MHz asynchronous PCI clock Ext...

Page 193: ...s 7 58 MHz 114 MHz 010 Forward divisor is 6 66 MHz 134 MHz 011 Forward divisor is 5 80 MHz 160 MHz 100 Forward divisor is 4 100 MHz 200 MHz 101 Forward divisor is 3 133 MHz 267 MHz 110 Forward divisor...

Page 194: ...requency Divisor 00 OPB PLB divisor is 1 01 OPB PLB divisor is 2 10 OPB PLB divisor is 3 11 OPB PLB divisor is 4 17 18 PPDV PCI PLB Frequency Divisor See PCI Clocks on page 7 8 for details 00 PCI PLB...

Page 195: ...PerCS5 as a chip select 1 Enable PerCS5 as GPI014 10 G15E GPIO 15 Enable o Enable PerCS6 as a chip select 1 Enable PerCS6 as GPI015 11 G16E GPIO 16 Enable o Enable PerCS7 as a chip select 1 Enable Per...

Page 196: ...selected 1 CTS is selected 20 RDS RTS DTR select oRTS is selected 1 DTR is selected 21 DTE DMA Transmit Enable for UARTO oDMA transmit channel is disabled 1 DMA transmit channel is enabled 22 DRE DMA...

Page 197: ...T serial 00001 Divide by 2 clock frequency For example if the CPU is 00010 Divide by 3 running at 200MHz a divider value of 20 sets the serial clock frequency to 10MHz Note The maximum serial clock fr...

Page 198: ...iven low for 8192 SysClk periods This enables the PPC405GP to reset itself and other devices attached to the same reset network The ExtReset signal is used by synchronous peripheral devices served by...

Page 199: ...tial instruction fetch During system reset the ExtReset signal is driven low to ensure the reset of synchronous devices that use the external bus clock signal PerClk 8 3 pel Power Management Initiated...

Page 200: ...recent watchdog reset 8 6 Processor Register Contents After Reset After a reset the contents of the SPRs control the initial processor state The initial register contents vary with the type of reset...

Page 201: ...truction cache disabled PVR 0 31 Processor version SGR GO G31 OxFFFFFFFF OxFFFFFFFF OxFFFFFFFF Storage is guarded SLER SO S31 OxOOOOOOOO OxOOOOOOOO OxOOOOOOOO Storage is big endian SUOR KO K31 OxOOOOO...

Page 202: ...OOO DCPO_ITOR3 0 31 OxOOOOOOOO DCPO_PLBBEAR 0 31 OxOOOOOOOO DCPO_RAMO 1KB Undefined DCPO_RAM3FF DCPO_VER 0 31 OxOOOO0200 Direct Memory Access DMA DMAO_CRO 0 31 OxOOOOOOOO DMAO_CR1 0 31 OxOOOOOOOO DMAO...

Page 203: ...CO_B1AP 0 31 OxOOOOOOOO EBCO_B1CR 0 31 OxOOOOOOOO EBCO_B2AP 0 31 OxOOOOOOOO EBCO_B2CR 0 31 OxOOOOOOOO EBCO_B3AP 0 31 OxOOOOOOOO EBCO_B3CR 0 31 OxOOOOOOOO EBCO_B4AP 0 31 OxOOOOOOOO EBCO_B4CR 0 31 OxOOO...

Page 204: ...OOOOOO MALO_TXCASR 0 31 OxOOOOOOOO MALO_TXCTPOR 0 31 Undefined MALO_TXCTP1 R 0 31 Undefined MALO_TXDEIR 0 31 OxOOOOOOOO MALO_TXEOBISR 0 31 OxOOOOOOOO On Chip Buses PLBO_ACR 0 31 OxOOOOOOOO PLBO_BEAR 0...

Page 205: ...UICO_MSR Undefined UICO_PR Undefined UICO_SR Undefined UICO_TR Undefined UICO_VCR Undefined UICO_VR Undefined 8 8 MMIO Register Contents After Reset MMIO registers are unaffected by core resets and a...

Page 206: ...00 EMACO_STACR 0 31 OxOOO08000 EMACO_TMRO 0 31 OxOOOOOOOO EMACO_TMR1 0 31 Ox380FOOOO EMACO_TRTR 0 31 OxOOOOOOOO EMACO_VTCI 0 31 OxOOOOOOOO EMACO_VTPID 0 31 OxOOO08808 General Purpose I O GPIO GPIOO_IR...

Page 207: ...PCICO_BROGOPT1 0 15 OxFF60 PCICO_BROGOPT2 0 15 Ox0100 PCICO_CACHELS 0 7 OxOO PCICO_CAP 0 7 OxOO PCICO_CAPIO 0 7 OxOO PCICO_CFGAOOR 0 31 OxOOOOOOOO PCICO_CFGOATA 0 31 OxOOOOOOOO PCICO_CLS 0 23 Ox060000...

Page 208: ...0 31 OxFFFEOOOO Value if strapped for PCI boot at reset PCILO_PMMOMA 0 31 OxFFFEOO01 Value if strapped for PCI boot at reset PCILO_PMMOPCIHA 0 31 OxOOOOOOOO Value if strapped for PCI boot at reset PC...

Page 209: ...LL 0 7 OxOOOOOOOO UART1_DLM 0 7 OxOOOOOOOO UART1_FCR 0 7 OxOOOOOOOO UARTCIER 0 7 OxOOOOOOOO UART1_IIR 0 7 OxOOOOOO01 UART1_LCR 0 7 OxOOOOOOOO UART1_LSR 0 7 Ox01100000 UART1_MCR 0 7 OxOOOOOOOO UART1_MS...

Page 210: ...e instruction cache array to ensure that no addresses to be programmed as OCM addresses are in the cache The ieeei instruction invalidates the instruction cache array 5 Modify the value in OCMO_ISARC...

Page 211: ...led by CPCO_CR020 After reset CPCO_CR019 or CPCO_CR020 must be changed to achieve a required typical pairing 8 10 PPC405GP Initial Processor Sequencing After any reset the processor core fetches the w...

Page 212: ...ntrol registers if necessary Initialize the SLER to configure storage byte ordering Initialize the SUOR to configure storage compression 2 Before executing instructions as cachable Invalidate the inst...

Page 213: ...ure endianness and compression 1 mtspr SLER endianness mtspr SUOR compression_attribute 1 Invalidate the instruction cache and enable cachability 1 iccci 1 invalidate i cache 1 1 1 1 mtspr lCCR Lcache...

Page 214: ...to catch possible ripple set time base low set desired PIT count Exceptions must be enabled immediately after timer facilities to avoid missing a timer exception 1 The MSR also controls privileged use...

Page 215: ...8 18 PPC405GP User s Manual Preliminary...

Page 216: ...ead to enable default initial conditions before PPC405GP start up The actual capture instant is the nearest SysClk clock edge before the deassertion of SysReset The state of the pins as read is stored...

Page 217: ...05GP visit the technical documents area of the IBM PowerPC web site 7 8 PDC PLB Divider from CPU 00 Divide By 1 01 Divide By 2 10 Divide By 3 11 Divide By 4 9 10 ODP OPB Divider from PLB 00 Divide By...

Page 218: ...alternate signal is in brackets Table 9 1 Multiplexed Pins Signal DCR Bit Description GPI01 TS1 E CPCO_CRO TRE Set of GPIO pins that can be reconfigured for use as GPI02 TS2E the CPU Trace interface G...

Page 219: ...for use by peripherals as a Write Byte Enable logical AND of the four PerWBEO 3 write byte enables PCIReqO Gnt CPCO_PSR PAE PCIReqO when internal arbiter is used or Gnt when external arbiter is used...

Page 220: ...are used to read and write the UIC registers An optional critical interrupt vector generator can reduce interrupt handling latency for critical interrupts Vector calculation is described in detail in...

Page 221: ...13 High Level MAL TX Descriptor Error TXDE 14 High Level MAL RX Descriptor Error RXDE 15 High Level Ethernet 16 High Level External PCI SERR 17 High Level ECC Correctable Error 18 High Level PCI Powe...

Page 222: ...er OxOC5 RIW UICO_MSR UIC Masked Status Register OxOC6 Read only UICO_VR UIC Vector Register OxOC7 Write only UICO_VCR UIC Vector Configuration Register OxOC8 Read only 10 5 1 UIC Status Register UICO...

Page 223: ...rrupt occurred 8 D31S DMA Channel 3 Interrupt Status o A DMA channel 3 interrupt has not occurred 1 A DMA channel 3 interrupt occurred 9 EWIS Ethernet Wake up Interrupt Status o An Ethernet wake up in...

Page 224: ...s not occurred 1 An external IRQ 0 interrupt occurred 26 EIR1S External IRQ 1 Status o An external IRQ 1 interrupt has not occurred 1 An external IRQ 1 interrupt occurred 27 EIR2S External IRQ 2 Statu...

Page 225: ...IE MREIE MRDIE EPSIE PPMIE EIR1 E EIR3E EIR5E U11E EMIE DOlE D21E EWIE MTEIE MTDIE ENIE ECIE EIROE EIR2E EIR4E EIR6E Figure 10 2 UIC Enable Register UICO_ER 0 UOIE UARTO Interrupt Enable o UARTO inter...

Page 226: ...DE interrupt is enabled 15 EIE Ethernet Interrupt Enable oAn Ethernet interrupt is disabled 1 An Ethernet interrupt is enabled 16 EPSIE External PCI SERR Interrupt Enable oExternal PCI SERR interrupt...

Page 227: ...ritical interrupts when MSR CE 1 If a UICO_CR field is set to 0 an enabled interrupt captured in the corresponding field of the UICO_SR and enabled in the corresponding field of the UICO_ER generates...

Page 228: ...on critical 1 MAL TX EOB interrupt is critical 12 MREIC MAL RX EOB Interrupt Class a MAL RX EOB interrupt is non critical 1 MAL RX EOB interrupt is critical 13 MTDIC MAL TX DE Interrupt Class a MAL TX...

Page 229: ...Q 6 Class o An external IRQ 6 interrupt is non critical 1 An external IRQ 6 interrupt is critical 10 5 4 UIC Polarity Register UICO_PR The fields of the UICO_PR which correspond to the fields of the U...

Page 230: ...t Polarity Must be set to 1 o DMA channel 0 interrupt has negative polarity 1 DMA channel 0 interrupt has positive polarity 6 D11P DMA Channel 1 Interrupt Polarity Must be set to 1 o DMA channel 1 int...

Page 231: ...ror interrupt has positive polarity 18 PPMIC PCI Power management Interrupt Class Must be set to 1 oPCI power management interrupt has negative polarity 1 PCI power management interrupt has positive p...

Page 232: ...controlled by UICO_TRo 2 4 18 are level sensitive the associated fields must be set to 0 The external master interrupt trigger controlled by UICO_TR3 is edge sensitive this field must be set to 1 UIO...

Page 233: ...t be set to o oMAL SERR interrupt is level sensitive 1 MAL SERR interrupt is edge sensitive 11 MTEIT MAL TX EOB Interrupt Trigger Must be set to O oMAL TX EOB interrupt is level sensitive 1 MAL TX EOB...

Page 234: ...l sensitive 1 An external IRQ 1 interrupt is edge sensitive 27 EIR2T External IRQ 2 Trigger oAn external IRQ 2 interrupt is level sensitive 1 An external IRQ 2 interrupt is edge sensitive 28 EIR3T Ext...

Page 235: ...Register UICO_MSR 0 UOIS UARTO Masked Interrupt Status oA UARTO interrupt has not occurred 1 A UARTO interrupt occurred 1 U11S UART1 Masked Interrupt Status oA UART1 interrupt has not occurred 1 A UAR...

Page 236: ...E Masked Interrupt Status oA MAL TX DE interrupt has not occurred 1 A MAL TX DE interrupt occurred 14 MRDIS MAL RX DE Masked Interrupt Status oA MAL RX DE interrupt has not occurred 1 A MAL RX DE inte...

Page 237: ...ies interrupt ordering priority Vector generation is not performed for non critical interrupts UICO_VCR VBA can contain either the base address for an interrupt handler vector table or the base addres...

Page 238: ...vector is based on the field position of the current highest priority enabled active critical interrupt relative to the highest priority interrupt in the UICO_SR The generated vectors can be programme...

Page 239: ...address represented by the UICO_VR value Alternatively the routine can be at a different address and system software can treat the value of the UICO_VR as a pointer storing the interrupt handler addre...

Page 240: ...abling it UICO_VR contains OxOOOOOOOO 8 UICO_CR is reprogrammed to make the low priority interrupt non critical and UICO_ER is reprogrammed to re enable the low priority interrupt UICO_VR continues to...

Page 241: ...the saved instruction pointer to be something else possibly prohibiting guaranteed software recovery Note that precise and imprecise are defined assuming that the interrupts are unmasked enabled to o...

Page 242: ...ted to the machine check handler in the save restore register and all previous instructions mayor may not have completed successfully All previous instructions that would ever complete have completed...

Page 243: ...ptions other than the system call exception or the address of the next sequential instruction for asynchronous exceptions and the system call exception is passed to the interrupt handling routine All...

Page 244: ...n access to the TLB_entry EX 0 translated address is not permitted because TLB_entry EX 0 and an attempt is made to execute the instruction Instruction storage Noncritical Instruction translation is a...

Page 245: ...not be interrupted after it is requested on the PLB so the Guarded G storage attribute does not need to prevent the interruption of an aligned scalar load store To enhance performance the DCU can resp...

Page 246: ...Offset Interrupt Type Interrupt Class Category Page Ox0100 Critical input interrupt Asynchronous precise Critical 10 34 Ox0200 Machine check data Critical 10 35 Machine check instruction Critical 10...

Page 247: ...E DR o Figure 10 9 Machine State Register MSR 0 12 Reserved 13 WE Wait State Enable If MSR WE 1 the processor remains in oThe processor is not in the wait state the wait state until an interrupt is ta...

Page 248: ...On interrupt SRRO is set to the current or next instruction address and the contents of the MSR are written to SRR1 When an rfi instruction is executed at the end of the interrupt handler the program...

Page 249: ...When an rfci instruction is executed at the end of the interrupt handler the program counter and the MSR are restored from SRR2 and SRR3 respectively The contents of SRR2 and SRR3 can be written to GP...

Page 250: ...0 4 Interrupt Vector Offsets on page 10 27 are concatenated to the right of the high order 16 bits of the EVPR to form the 32 bit address of an interrupt handling routine The contents of the EVPR can...

Page 251: ...1 10 i t t 311 PPR OST Figure 10 15 Exception Syndrome Register ESR 0 MCI Machine check instruction o Instruction machine check did not occur 1 Instruction machine check occurred 1 3 Reserved 4 PIL Pr...

Page 252: ...ine check instruction interrupt occurs while MSR ME 0 and the instruction upon which the machine check instruction interrupt is occurring also is some other kind of ESR setting instruction program dat...

Page 253: ...critical pin interrupt See Watchdog Timer Interrupt on page 10 43 After detecting a critical interrupt if no synchronous precise interrupts are outstanding the PPC405GP immediately takes the critical...

Page 254: ...16 bits of the program counter are then written with the contents of the EVPR and the low order 16 bits of the program counter are written with Ox0200 Interrupt processing begins at the new address in...

Page 255: ...E is enabled for the machine check interrupt to be taken Software should in general clear the ESR bits before returning from a machine check interrupt to avoid any ambiguity when handling subsequent m...

Page 256: ...eption Address Register DEAR is loaded with the data address that caused the access violation ESR bits are loaded as shown in Table 10 10 Register Settings during Data Storage Interrupts on page 10 37...

Page 257: ...tion was either EX 0 or G 1 The interrupt is precise with respect to the attempted execution of the instruction Program flow vectors to EVPR 0 15 Ox0400 The following registers are modified to the spe...

Page 258: ...ng an rfi instruction restores the program counter from SRRO and the MSR from SRR1 and execution resumes at the address in the program counter Table 10 12 Register Settings during External Interrupts...

Page 259: ...te bit is set and the others are cleared These interrupts are not maskable Table 10 15 ESR Usage for Program Interrupts Bits Interrupts Cause ESR PIL Illegal instruction Opcode not recognized ESR PPR...

Page 260: ...he contents of the EVPR and the low order 16 bits of the program counter are written with OxOCOO Interrupt processing begins at the new address in the program counter Executing an rfi instruction rest...

Page 261: ...t from the FIT Time out is detected when at the beginning of a clock cycle TSR FIS 1 This occurs on the second cycle after the 0 1 transition of the appropriate time base bit The PPC405GP immediately...

Page 262: ...register is not direct data but a mask a 1 causes the bit to be cleared and a 0 has no effect Executing the return from critical interrupt instruction rfci restores the contents of the program counter...

Page 263: ...cution of the instruction Program flow vectors to EVPR 0 15 Ox1200 The following are modified to the values specified in Table 10 22 Table 10 22 Register Settings during Instruction TLB Miss Interrupt...

Page 264: ...s shown in Table 10 24 Register Settings during Debug Interrupts on page 10 45 The high 9rder 16 bits of the program counter are then written with the contents of the EVPR the low order 16 bits of the...

Page 265: ...10 46 PPC405GP User s Manual Preliminary...

Page 266: ...itionally the watchdog timer can help a system to recover from faulty hardware or software Figure 11 1 shows the relationship of the timers and the clock source to the time base 0 CPCO_CR1 CETE CPU Cl...

Page 267: ...mbers other than those specified in the PowerPC Architecture as read access time base registers Ox10C and Ox10D Write access to the time base using mtspr is privileged Different register numbers are u...

Page 268: ...c for mtspr TBl RS 11 1 1 Reading the Time Base The following code provides an example of reading the time base mftb moves the low order 32 bits of the time base to a GPR mftbu moves the high order 32...

Page 269: ...of register behavior during a PIT interrupt The interrupt handler should use software to reset the PIS field of the Timer Status Register TSR This is done by using mtspr to write a word to the TSR hav...

Page 270: ...od TCR FP TBL Bit Time Base Clocks 200 Mhz Clock 0 0 23 29 clocks 2 561lsec 0 1 19 213 clocks 40 961lsec 1 0 15 217 clocks 0 655 msec 1 1 11 221 clocks 10 49 msec The TSR FIS field logs a FIT exceptio...

Page 271: ...S bit This is done by using mtspr to write a word to the TSR having a 1 in TSR WIS and any other bits to be cleared and a 0 in all other bits The data written to the TSR is not direct data but a mask...

Page 272: ...WRS and clear TCR WRC disabling the watchdog timer The controls described in Figure 11 5 imply three different ways of using the watchdog timer The modes assume that TCR WRC was set to allow processor...

Page 273: ...by hardware and read and cleared by software The mfspr instruction reads the TSR Clearing the TSR is performed by writing a word to the TSR using mtspr having a 1 in all fields to be cleared and a 0...

Page 274: ...reset function All processor resets clear TCR ARE to 0 disabling the auto reload feature of the PIT WP WIE FP FIE 4 4 31 1 f t t WRC PIE ARE Figure 11 7 Timer Control Register TCR 0 1 WP Watchdog Peri...

Page 275: ...10217 clocks 11 221 clocks 8 FIE FIT Interrupt Enable o Disable FIT interrupt 1 Enable FIT interrupt 9 ARE Auto Reload Enable Disables on reset o Disable auto reload 1 Enable auto reload 10 31 Reserv...

Page 276: ...o the PPC405GP the debug port is typically connected to a JTAG connector on a processor board The trace interface connects to a trace port also external to the PPC405GP that is typically connected to...

Page 277: ...ition 14 does not contain a pin 181 KEY 15 181 181 16 Figure 12 1 JTAG Connector Physical Layout Top View Table 12 1 JTAG Connector Signals Pin 1 0 Signal Description 1 0 TDO JTAG Test Data Out 2 No c...

Page 278: ...HighZ 1111101 IEEE 1149 1a 1993 optional Clamp 1111110 IEEE 1149 1a 1993 optional Bypass 1111111 IEEE 1149 1 standard 12 4 2 JTAG Boundary Scan Boundary Scan Description Language BSDL IEEE 1149 1b 19...

Page 279: ...istors The optional JTAG instructions idcode and highz offer additional JTAG functionality The idcode instruction returns the PPC405GP JTAG ID which is unique for each chip version The highz instructi...

Page 280: ...er User s Guide A 20 pin male 2x10 header connector is recommended for connecting to the trace status port of the PPC405GP The connector shown in Figure 12 3 and the signal descriptions in Table 12 3...

Page 281: ...software at a dedicated interrupt vector and an external communications path to gebug software problems This mode used while the processor executes instructions enables debugging of operating system o...

Page 282: ...bug wait mode when internal and external debug modes are disabled DBCRO IDM EDM 0 debug wait mode is enabled MSR DWE 1 debug wait is enabled by the JTAG debugger and a debug event occurs For example w...

Page 283: ...a debug operation The operation depends on the debug mode For more information and a list of debug events see Debug Events on page 12 16 Freeze Timers The JTAG debug port or DBCRO can control timer r...

Page 284: ...bug Control Register 0 DBCRO a EDM External Debug Mode a Disabled 1 Enabled 1 10M Internal Debug Mode a Disabled 1 Enabled 2 3 RST Reset Causes a processor reset request when 00 No action set by softw...

Page 285: ...gisters IAC3 and IAC4 define an oDisabled address range used for lAC address 1 Enabled comparisons 15 IA34X Instruction Address Exclusive Range Selects range defined by IAC3 and IAC4 to Compare 3 4 be...

Page 286: ...ess 10 Ignore two Isbs Halfword address 11 Ignore five Isbs Word address Cache line 8 word address 6 7 D2S DAC 2 Size Address bits used in the compare 00 Compare all bits 01 Ignore Isb least significa...

Page 287: ...to the appropriate halfword in DVC2 When performing halfword compares set DBCR1 DV2BE 0011 1100 or 1111 16 19 DV1BE Data Value Compare 1 Byte Selects which data bytes to use in data o Disabled value...

Page 288: ...curred 3 TIE Trap Instruction Debug Event o Event did not occur 1 Event occurred 4 UDE Unconditional Debug Event o Event did not occur 1 Event occurred 5 IA1 IAC1 Debug Event o Event did not occur 1 E...

Page 289: ...uction Address Compare Registers IAC1 IAC4 The PPC405GP can take a debug event upon an attempt to execute an instruction from an address The address which must be word aligned is defined in an lAC reg...

Page 290: ...Address Compare DAC byte address DBCRO D1 S determines which address bits are examined 12 9 5 Data Value Compare Registers DVC1 DVC2 The PPC405GP can take a debug event upon storage or cache reference...

Page 291: ...of an instruction Branch Taken BT BT Occurs before execution of a branch instruction determined to be taken Exception Taken EDE EXC Occurs after an exception Trap Instruction TDE TIE Occurs before ex...

Page 292: ...parison to one of the IACn registers or on a range of addresses to compare defined by a pair of IACn registers 12 9 12 1 lAC Exact Address Compare In this mode each IACn register specifies an exact ad...

Page 293: ...F FFFF I I IAC1 IAC2 Figure 12 11 Exclusive lAC Range Address Compares To toggle the range from inclusive to exclusive or from exclusive to inclusive on a lAC range debug event OBCRO IA12T correspondi...

Page 294: ...t compare would not recognize a reference to that byte by load store word or load store halfword instructions because the byte address is not the EA of such instructions In such a case the D1 S field...

Page 295: ...ress in DAC2 is along with the highest memory address as shown in the preceding examples o FFFF FFFF I DAC1 DAC2 Figure 12 13 Exclusive DAC Range Address Compares The DAC Compare Size fields DBCR1 D1...

Page 296: ...gh dcread and dccci are not address specific they affect a congruence class regardless of the instruction operand address and are considered loads in the PPC405GP they do not cause DAC debug events AI...

Page 297: ...or DBSR DW1 depending on whether the operation is a load read or a store write This example corresponds to the last line of Table 12 6 In Table 12 6 n is 1 or 2 depending on whether the bits apply to...

Page 298: ...v DVC1 byte 2 data byte 2 1 DVnBE3 v DVC1 byte 3 data byte 3 10 OR DVnBEo 1 DVC1 byte 0 data byte 0 v DVnBE1 1 DVC1 byte 1 data byte 1 v DVnBE2 1 DVC1 byte 2 data byte 2 v DVnBE3 1 DVC1 byte 3 data by...

Page 299: ...12 24 PPC405GP User s Manual Preliminary...

Page 300: ...al to a class 2 unit is deasserted when the CPM controller enable bit for that unit is reset or when the unit deasserts its Sleep_Req signal The CPM class 3 interface has a CPM_Sleeplnit signal that i...

Page 301: ...al Controller Class 2 7 SDRAM SDRAM Memory Controller Class 2 8 PLB PLB Bus Arbiter Class 2 9 GPIO General Purpose Interrupt Controller Class 1 10 UARTO Serial Port 0 Class 1 11 UART1 Serial Port 1 Cl...

Page 302: ...s set to 1 and the Sleep_Req signal from the class 2 unit is asserted the unit is requesting sleep state CPM_Sleep_N to the class 2 unit is asserted When the bit is set to 0 the CPM_Sleep_N signal is...

Page 303: ...13 4 PPC405GP User s Manual Preliminary...

Page 304: ...ms an instruction fetch the decompression controller works with the memory controller SDRAM or external bus controller EBC to provide a decompressed instruction stream to the CPU The memory controller...

Page 305: ...r core provides a signal with each instruction memory reference indicating whether the reference is in compressed or uncompressed memory space The CPU s UO storage attribute is used to implement this...

Page 306: ...compression blocks the decompression controller continues to decompress instructions until its 64 byte output buffer is full In such cases the decompression controller acts as a prefetch buffer and su...

Page 307: ...Register 3 DCPO_ADDRO Ox04 R w Address Decode Definition Register 0 DCPO_ADDR1 Ox05 R w Address Decode Definition Register 1 DCPO_CFG Ox40 R w Decompression Controller Configuration Register DCPO_ID O...

Page 308: ...erved 12 15 DRS Decode Region Size 0000 0100 Reserved 0101 4MB 01108MB 0111 16MB 1000 32MB 1001 64MB 1010 128MB 1011 256MB 1100512MB 11011GB 11102GB 1111 4GB 16 30 Reserved 31 OREN Enable Decode Regio...

Page 309: ...served 31 IKB Enable Decrompression o Decompression is enabled UO storage attribute is recognized 1 Decompression is disabled UO storage attribute is ignored 14 2 4 Decompression Controller ID Registe...

Page 310: ...Register DCPO_PLBBEAR 0 31 I Address of PLS Error 14 2 7 Decompression Controller Bus Error Address Register DCPO_MEMBEAR On an error DCPO_MEMBEAR contains the address presented to the memory controll...

Page 311: ...EARlDCPO_PLBBEAR DCPO_MEMBEAR and DCPO_PLBBEAR Address Lock for Master 0 are locked to this master address when the o Master has not locked PLB_lockErr signal was active in the cycle DCPO_MEMBEAR and...

Page 312: ...MEMBEAR and DCPO_PLBBEAR 18 20 DET3 Decompression Error Type for Master 3 See description for DCPO_ESR DETO Master 3 is PCI 21 RW3 Read Write Status for Master 3 This implementation only report errors...

Page 313: ...14 10 PPC405GP User s Manual Preliminary...

Page 314: ...Part IV PPC405GP External Interfaces Preliminary IV 1...

Page 315: ...IV 2 PPC405GP User s Manual Preliminary...

Page 316: ...ndard single error correction and double error detection Designers also have the opportunity to reduce system power by placing the SDRAM controller in sleep andlor self refresh mode 15 1 Interface Sig...

Page 317: ...Note 1 During power up MemClkOut1 0 tracks SysClk until the internal PLL begins to lock At that time MemClkOut1 0 transitions to the clock rate configured via the strapping resistors 15 2 Accessing S...

Page 318: ...g the SDRAMO_CFG register li mtdcr mfdcr r3 SDRAMO_CFG SDRAMO_CFGADDR r3 r4 SDRAMO_CFGDATA address offset of SDRAHO_CFG set offset address read value of SDRAMO_CFG Programming Note Reserved fields in...

Page 319: ...anks 2 Waits SDRAMO_TR PTA cycles 3 Performs eight CAS before RAS refresh cycles each separated by SDRAMO_TR RFTA clock cycles 4 Issues the mode register write command to each bank 5 Perform eight CAS...

Page 320: ...31 Reserved 15 3 2 Memory Controller Status SDRAMO_STATUS The Memory Controller Status Register SDRAMO_STATUS allows software to determine the current state of the SDRAM controller If SDRAMO_STATUS M...

Page 321: ...15 4 Memory Bank 0 3 Configuration Registers SDRAMO_BOCR SDRAMO_B3CR 0 9 BA Base Address The base address must be aligned on a boundary that matches the size of the region as defined by the SZ field...

Page 322: ...occurs when a match exists All PMU directory entries are deallocated when a CAS before RAS refresh occurs Open pages can be spread across the system memory array on different bank selects BankSeln or...

Page 323: ...Column 6 7 7 42 AP 5 21 22 23 24 25 4 8 16 MB Row 8 21 8 9 10 11 12 13 14 15 16 12 x 8 x 2 4 Column 8 21 8 4 AP 6 21 22 23 24 25 5 4 8 MB Row 9 21 9 21 10 11 12 13 14 15 16 11 x 8 x 2 4 Column 9 21 9...

Page 324: ...s is not supported See Selected Timing Diagrams on page 15 10 for timing diagrams illustrating how the fields in SDRAMO_TR affect the signalling on the SDRAM memory interface PTA LDF RCD t 26127 29130...

Page 325: ...sactions that occur The timing diagrams in this section are intended to illustrate cycle based SDRAM programmable timing parameters only As such AC specific timing information should not be inferred f...

Page 326: ...CTP I iCASL I I I PTA I X X X Figure 15 6 Activate Four Word Read Precharge Activate MemClkOut1 0 Lf L rLrL LrLrLrL ClkEn1 0 BA1 0 MemAddr12 11 MemAddr10 AP MemAddr9 0 BankSeln DOM3 0 DOMCB MemData31...

Page 327: ...J I I DOM3 0 DOMCS Figure 15 8 Precharge All Activate MemClkOut1 0 rL rL rLrL rL rL rL rLrLrLrL ClkEn1 0 BA1 0 1 MemAddr12 0 X SankSelO L J 1 SankSel1 L 1 1 BankSel2 L RFTA 1 BankSel3 r LDF W 1 1 I r...

Page 328: ...ed and the initialization sequence has completed the refresh mechanism starts automatically with refreshing of the memory continuing independent of SDRAMO_CFG DCE Refresh requests are generated intern...

Page 329: ...partial writes a read modify write sequence including bus turn around is required to generate the write check bits and store the resultant data Table 15 8 Additional Latency when using ECC PLB Transac...

Page 330: ...in SDRAMO_ECCESR BKnE and the byte lane that experienced the correctable error is identified in SDRAMO_ECCESR BLnCE Furthermore the correctable error bit SDRAMO_ECCESR CE is set causing an ECC Correct...

Page 331: ...is set to a value of one Setting the field lock bit prevents subsequent errors for this master from being logged and overwriting the contents of the field In addition the address lock bit is set if no...

Page 332: ...ions SDRAMO BEAR 10 311 Figure 15 14 Bus Error Address Register SDRAMO_BEAR I0 31 SDRAMO_BEAR IAddress of ECC Error 15 4 7 Bus Error Syndrome Register 0 SDRAMO_BESRO This register tracks errors encoun...

Page 333: ...r master 3 Master 3 is the PCI bridge 000 No error 001 Reserved 01 X EGG uncorrectable error 1XX Reserved 21 RWS3 Read write status for master 3 o Error operation was a write operation 1 Error operati...

Page 334: ...CC uncorrectable error 1XX Reserved 9 RWS5 Read write status for master 5 oError operation was a write operation 1 Error operation was a read operation 10 31 Reserved 15 5 Self Refresh The SDRAM contr...

Page 335: ...in sleep mode SDRAM refresh continues to preserve the contents of the memory and maintain the refresh interval 15 6 1 Sleep Mode Entry Sleep mode is enabled by setting SDRAMO_CFG PME and CPMO_ER SDRAM...

Page 336: ...addition the wakeup logic also monitor the DCR bus for accesses to SDRAM configuration and status registers If either a PLB or DCR operation targeting the SDRAM controller is detected the SDRAM contro...

Page 337: ...15 22 PPC405GP User s Manual Preliminary...

Page 338: ...rther simplified through dynamic bus sizing which supports seamlessly attaching 8 16 and 32 bit wide memories and peripherals Whenever a size mismatch exists between a read or write operation and the...

Page 339: ...set O ExtReset 1 Usage PerClk See Note 1 Toggling Peripheral bus clock During an ESC transfer all ESC signal transitions and data sampling occurs synchronous to PerClk ExtReset 0 1 Peripheral reset fo...

Page 340: ...k High Z 1 External acknowledge used by the PPC405GP to indicate that an external master data transfer occurred Note 1 During a chip or system reset PerClk begins clocking 64 SysClk cycles prior to th...

Page 341: ...and attempt to use a peripheral memory bank whose output is set up as a GPIO Doing so causes an EBC transaction without an active chip select and the results are therefore undefined In the remainder...

Page 342: ...eral bus timing as follows PerCSn becomes active 0 3 PerClk cycles EBCO_BnAP CSN after the address is driven P8rOE is driven low 0 3 PerClk cycles EBCO_BnAP OEN after PerCSn is active PerBLast is acti...

Page 343: ...read transfer from a non burst enabled EBCO_BnAP BME O bank The transaction begins with the address being driven Since this is a single transfer PerBLast is also driven active along with the address I...

Page 344: ...CO_BnAP WBN cycles after PerCSn The EBC then waits until BCO_BnAP TWT EBCO_BnAP WBF 1 cycles have elapsed since the start of the transaction then drives all the PerWBEO 3 inactive If EBCO_BnAP BEM 1 t...

Page 345: ...es and For the first transfer of a burst or a single transfer to a burst enabled bank the appropriate write byte enables go low 0 3 EBCO_BnAP WBN cycles after PerCSn becomes active The EBC then waits...

Page 346: ...fter PerCSn The EBC then waits until EBCO_BnAP FWT 1 cycles have elapsed since the start of the transaction and then reads the data bus and the peripheral error input PerErr If parity checking is enab...

Page 347: ...put for the second element in the burst As shown in Figure 16 6 the EBC transfers the subsequent data items in a similar manner If EBCO_BnAP BEM 1 the PerWBEO 3 lines are byte enables and have the sam...

Page 348: ...f the burst Sampling continues once per cycle until either PerReady is sampled high or a timeout occurs When EBCO_BnAP SOR 1 data transfer occurs in the same cycle where PerReady is sampled active In...

Page 349: ...ed EBCO_CFG PTD O the EBC waits indefinitely for PerReady to become active Otherwise the EBC waits only EBCO_CFG RTC cycles from the start of the transaction until logging a timeout error Once PerRead...

Page 350: ...then waits until EBCO_BnAP TWT 1 cycles have elapsed since the start of the transaction and then begins sample PerReady If device paced timeouts are disabled EBCO_CFG PTD O the EBC waits indefinitely...

Page 351: ...e EBC waits one more cycle before sampling read data The EBC then reads the data bus and the peripheral error input PerErr If parity checking is enabled EBCO_BnAP PEN 1 the parity is also read The nex...

Page 352: ...ta elements in the burst If EBCO_BnAP BEM 1 PerWBEO 3 are byte enables and have the same timing as PerAddrO 31 The EBC then waits until EBCO_BnAP FWT 1 cycles have elapsed since the start of the trans...

Page 353: ...J WBN WBN WBEQ I WBEl WBN I WBE2 H I L L _ _tb WBN I WBEn PerWBEO 3 U L BEM O PerWE J ______ 0 n 1 perWBEO 3 J __ __ L __ ____ __ L __ BEM 1 PerWE n i F WT i BWT BWT i B WT BEQ BEl BE2 BE n SOR O Per...

Page 354: ...d in a system HoldReq HoldPri HoldAck BusReq PerRiW ExtReq ExtAck PerBLast PerDataO 31 PerAddrO 31 PerWBEO 3 PerCSn PerDE SRAM Bank EBC HoldReq Priority HoldAck BusReq R W XREQ XACK BLast DATAO 31 DE...

Page 355: ...directly control devices on the peripheral bus or read and write PLB and OPB addressable memory If the EBC detects a pending PLB request when the external master owns the peripheral bus HoldAck 1 Bus...

Page 356: ...requested read data is then serviced from within this doubleword If the next operation on the EBM interface is a read and targets this same doubleword it is serviced directly from the buffer Burst rea...

Page 357: ...n goes low when read data is available on PerData Note that the external master must not remove ExtReq until the cycle after ExtAck becomes active In addition ExtReq must be high for at least one cycl...

Page 358: ..._ A dd re s so i Pe rW S EO O 3 J PerRiW 4H c PerSLast PerDataO 31 Figure 16 13 External Master Burst Read 16 5 5 Burst Write Transfer Burst writes are preferred when accessing sequential addresses as...

Page 359: ...erClk HoldPri HoldReq lJ HoldAck PerAddrO 31 Figure 16 14 External Master Burst Write 16 5 6 External Master Error Interrupts The EBM can generate an interrupt if a PLB error is encountered while read...

Page 360: ...Error Address Register 16 29 EBCO_BESRO Ox21 RIW Peripheral Bus Error Status Register 0 16 30 EBCO_BESR1 Ox22 RIW Peripheral Bus Error Status Register 1 16 32 EBCO_CFG Ox23 RIW EBC Configuration Regi...

Page 361: ...0 256 PerClk cycles 101 512 PerClk cycles 110 1024 PerClk cycles 111 2048 PerClk cycles 5 6 EMPL External Master Priority Low The PLB priority for external master initiated 00 Low transfers when the e...

Page 362: ...ank 0 starting address register is loaded with a value of OxFFE and the bank 0 size register is loaded with a value of Ob001 2MB immediately following SysReset inactive BAS BS BU BW 1 0 11112 14115161...

Page 363: ...d or write accesses When a write access is attempted to an address within the range of the BAS field and the bank is designated as read only a protection error occurs Also when a read access is attemp...

Page 364: ...If BEM O PerWBEO 3 timing is controlled by o PerWBEO 3 are only active for write cycles WBN and WBF If BEM 1 PerWBEO 3 has 1 PerWBEO 3 are active for read and write the same timing as PerAddrO 31 cyc...

Page 365: ...F must be set to zero TH Transfer Hold bits 20 22 Specifies the number of PerClk cycles 0 through 7 that the peripheral bus is held idle after the deassertion of PerCSn During these cycles the address...

Page 366: ...trollers may qualify their PLB transactions to the EBC such that the information describing any errors that occur during these transfers becomes iocked When an error is locked subsequent errors are no...

Page 367: ...EBC External Bus Master and PCI Bridge The contents of EBCO_BESRO are accessed indirectly through the EBCO_CFGADDR and EBCO_CFGDATA registers using the mfdcr and mtdcr instructions It is possible to...

Page 368: ...t error 111 External bus timeout error 15 RWS2 Read write status for master 2 a Error operation was a write operation 1 Error operation was a read operation 16 17 Reserved 18 20 EET3 Error type for ma...

Page 369: ...Status Register 1 EBCO_BESR1 0 2 EET4 Error type for master 4 Master 4 is the MAL 000 No error 001 Parity error 010 Reserved 011 Reserved 100 Protection error 101 Reserved 110 External bus input erro...

Page 370: ...master 5 o EET5 and RWS5 fields are unlocked 1 EET5 and RWS5 fields are locked 11 AL5 EBCO_BEAR address lock for master 5 o EBCO_BEAR address unlocked 1 EBCO_BEAR address locked 12 31 Reserved Externa...

Page 371: ...16 34 PPC405GP User s Manual...

Page 372: ...ns See Figure 17 3 on page 17 5 for a graphic overview of the PCI bridge Agents on the PLB are referred to as masters or slaves Agents on the PCI are referred to as targets or slaves 17 1 1 PCI Bridge...

Page 373: ...space by means of the corresponding entry in the PPC405GP CPU s MMU or by means of the appropriate memory region bit in the Storage Little Endian Register SLER if the MMU is not being used Because the...

Page 374: ...it Interface Byte MSB f 7 f 7 Byte LSB Data Byte Value Oxnn 11 22 33 44 Little Endian Byte Address Obnn 11 10 01 00 PPC405GP Processor Core Data24 31 Data16 23 Data8 15 DataO 7 Write Data Bus CoreConn...

Page 375: ...s a PLB to PCI half bridge to enablePLB master devices to access PCI target devices The h lf bridge configuration contains a 32 byte write post buffer and a 64 byte read prefetch buffer I PLB Master I...

Page 376: ...re is one Req Gnt pair that must be attached to an external arbiter A strapping pin determines whether the internal arbiter is enabled or not Priority is round robin rotating Priority switches when a...

Page 377: ...to an 1 0 access on PCI OxOOOOFFFF in the range 0 to 64KB 1 OE8010000 Reserved OE87FFFFF PCI bridge does not respond Other bridges use this space for non contiguous 1 0 OxE8800000 PCII O OxOO800000 O...

Page 378: ...o a region in PCI OxFFFFFFFFFFFFFFFF memory space The address ranges are fully programmable The PCI address is 64 bits OxOOOOOOOO PCI Memory Range 2 OxOOOOOOOOOOOOOOOO OxFFFF FFFF PMM 2 registers map...

Page 379: ...sets used to map PLB memory regions to PCI address space PMM PMM Local Address PMM Mask Attribute 1 Size PLB Memory PCI Memory Size 1 Region L T PMM PCI Low Address Region J r Starting Address PMM PCI...

Page 380: ...in PCI memory space is programmable using the PCIPCILO_PTMnBAR registers The PTMs are enabled and disabled using PCICO_CMD MA PTM address ranges and sizes should be initialized before being enabled If...

Page 381: ...1 register Single Beat 1 a byte Read PLB address decodes to Memory Read PMMO PMM1 or PMM2 nonprefetchable Burst Read PLB address decodes to Memory Read PMMO PMM1 or PMM2 nonprefetchable PLB 4 word and...

Page 382: ...nd is also generated in response to word and doubleword burst reads of greater than 32 bytes that decode to one of the three PMMs For prefetches the PCI bridge bursts up to a 64 bytes from the PCI Mem...

Page 383: ...ngle beat read to the PCI If the PCI cycle is retried the PLB cycle is rearbitrated When the PCI bridge receives a PLB 1 S byte or byte or halfword burst read request that decodes to a PMM marked as p...

Page 384: ...PLB reads only A PLB master accessing the PCI bridge can abort PLB write cycles only under the following conditions The PCI bridge rearbitrates the cycle The PCI bridge does not see the cycle because...

Page 385: ...R1 or PTM2 BAR2 memory access flag Memory Read PCI address decodes Doubleword burst read to PTM1 BAR1 or PTM2 BAR2 memory access flag Single Beat Memory Write PCI address decodes 1 a byte write to PTM...

Page 386: ...The PCI bridge initiates all PLB reads as single beat or doubleword burst transfers Memory Read generates a PLB single beat doubleword read Memory Read Line and Memory Read Multiple commands generate...

Page 387: ...does not re request the read in 215 PCI clocks about one millisecond for a 33 MHz PCI clock PCI bridge discards the delayed read data This timer begins counting at the beginning of the initial PCI cyc...

Page 388: ...write has completed on the PCI bus or a bursting PCI master has written at least six words of data The PCI bridge continues to receive data from a bursting PCI master as it transfers data to the PLB...

Page 389: ...stored in a PCI target the control software must manually force coherency This can be done by following two rules 1 To ensure data written by a PLB master has reached the intended PCI target the PLB...

Page 390: ...of the PCI bridge registers The registers are discussed in detail in the following sections See Chapter 8 Reset and Initialization for register reset values Table 17 8 Directly Accessed MMIO Register...

Page 391: ...M 2 BAR Reserved PCI BAR Ox1F ox1C R R Reserved PCI BAR Refer to PCI Specification Version 2 2 for more information on values Reserved PCI BAR Ox23 0x20 R R Reserved PCI BAR Refer to PCI Specification...

Page 392: ...Configuration Registers The PCI bridge local configuration registers have fixed addresses in PLB space and must be accessed using single beat PLB read or write cycles of the same size as shown in the...

Page 393: ...Returns 0 when read 1 PRE Read Prefetching Enable If read prefetch is enabled the PCI bridge 1 Read prefetching is enabled prefetches 64 bytes from PCI memory in response to a PLB single beat byte bur...

Page 394: ...n 0 the PCI bridge generates a PCI dual address cycle using the value in PCILO_PMMOPCIHA as the high order 32 bits of the PCI address Figure 17 10 PMM 0 High Address Register PCILO_PMMOPCIHA I 31 0 I...

Page 395: ...F8000 and a 4KB range would be encoded as Ox11111 11 2 Reserved Returns 0 when read 1 PRE Read Prefetching Enable If read prefetch is enabled the PCI bridge 1 Read prefetching is enabled prefetches 64...

Page 396: ...MM 2 Local Address Register PCILO_PMM2LA PCILO_PMM2LA defines the PLB starting address of range 2 in PLB space that is mapped to PCI memory See PMM 0 Local Address Register PCILO_PMMOLA on page 17 21...

Page 397: ...Enable If read prefetch is enabled the PCI bridge 1 Read prefetching is enabled prefetches 64 bytes from PCI memory in response to a PLB single beat byte burst or half word burst read from PMM O 0 ENA...

Page 398: ...ster PCILO_PTM1MS 31 12 MASK Defines the size of the region of PCI The minimum range size is 4KB Valid memory space that is mapped to local ranges are always a power of 2 PLB space using PTM 1 For exa...

Page 399: ...cal PLB space using PTM 2 Determines if range 2 is enabled to map PCI memory space to PLB space The minimum range size is 4KB Valid ranges are always a power of 2 For example a value of OxFFOOOOOO ind...

Page 400: ...bridge configuration registers from the PLB side use the same mechanism as described above but set PCICO_CFGADDR BN ON o The bridge is assumed to reside on PCI bus 0 and to have a device number of O T...

Page 401: ...onfiguration Data Register PCICO_CFGDATA Accessing PCICO_CFGDATA causes one of three things to happen depending on the value of PCICO_CFGADDR 1 Generation of a Type configuration cycle on the PCI bus...

Page 402: ...PCI Vendor 10 Register PCICO_VENDlD 115 0 1Vendor ID 17 5 3 4 PCI Device ID Register PCICO_DEVID PCICO_DEVID identifies the PCI device This value is Ox0156 index Ox03 Ox01 index Ox02 Ox56 at reset The...

Page 403: ...ddress stepping when generating a Config Type 0 cycle AS is read only and returns 0 when read 6 PER Parity error response This bit is enabled for all types of PCI bus o Disabled parity errors includin...

Page 404: ...ts Bits in PCICO_STATUS are set only as a result of specific events occurring on the PCI bus They are reset by writing a 1 to the desired bit Writing a to a bit location leaves that bit unchanged OEPE...

Page 405: ...icates that the PCI target can accept Read only returns 0 when read fast back to back transactions when the transactions are not to the same agent The PCI bridge target does not accept this type of fa...

Page 406: ...SUB Figure 17 30 PCI Class Register PCICO_PCICLS 23 16 BASE Base Class Reset to Ox06 which indicates bridge device Users of the RISCWatch debugger must use the PCICO_BASECC register to access this fie...

Page 407: ...ronous mode to a value that is less than 64 the PCI bridge PCI master interface could timeout regardless of the state of its grant line In asynchronous mode the PCI master starts its timer and can tim...

Page 408: ...IST is read only and returns OxOO when read 01 Figure 17 34 PCI Built in Self Test Control Register PCICO_BIST 1 7 0 1 PCI BIST Control 17 5 3 13 Unused PCI Base Address Register Space PCI base addres...

Page 409: ...BAZ OxOO because the minimum size of this range is 4KB 3 PF Prefetchable PR 1 to indicate that prefetching is allowed 2 1 LT Location Type LT ObOO to indicate that the memory space can be located anyw...

Page 410: ...BAZ OxOO because the minimum size of this range is 4KB 3 PF Prefetchable PF 1 to indicate that prefetching is allowed 2 1 LT Location Type LT ObOO to indicate that the memory space can be located anyw...

Page 411: ...ATU8 CL PCICO_CAP pOints to the first item in the list of capabilities at address offset Ox58 which is the PCI power management capability structure 01 Figure 17 39 PCI Capabilities Pointer PCICO_CAP...

Page 412: ...specifies the burst period length of a PCI device PCICO_MINGNT is read only and returns OxOO when read 01 Figure 17 42 PCI Minimum Grant Register PCICO_MINGNT I PCI Minimum Grant 17 5 3 22 PCI Maximum...

Page 413: ...hen read 0 API Asset PCI interrupt When software sets this bit the PCI bridge asserts its Interrupt pin 17 5 3 24 Error Enable Register PCICO_ERREN ERREN enables detection and reporting of various err...

Page 414: ...e drives PCISErr when a oDisabled data parity error is detected on a write 1 Enabled cycle when the PCI bridge is the PCI target PCICO_CMD SE must also be 1 0 MAEE Master Abort Error Enable MAEE enabl...

Page 415: ...nsupported Request Set when the PCI bridge is a PLB slave and detects an unsupported request from a PLB master to an address range that PCI bridge decodes The PCI bridge allows such requests to time o...

Page 416: ...aster receives the first read data word guarantee no disconnects for PLB line reads 17 5 3 27 PLB Slave Error Syndrome Register 0 PCICO_PLBBESRO PCICO_PLBBESRO stores information about errors reported...

Page 417: ...ter 0 25 23 M1ET Master 1 Error Type See PCICO_PLBBESRO MOET 22 M1RWS Master 1 Read Write Status oError operation was a write 1 Error operation was a read 21 M1FL Master 1 PCICO_PLBBESRO Field Lock o...

Page 418: ...egister PCICO_PLBBESRO on page 17 45 for additional information about the fields of this register Only software can clear PCICO_PLBBESR1 MxFL The PCICO_PLBBESR1 MxAL fields control the and PCICO_PLBBE...

Page 419: ...ESR1 Field Lock PCICO_PLBBESR1 unlocked 1 PCICO_PLBBESR1 locked 14 M6AL Master 6 PCICO_PLBBEAR Address Lock PCICO_PLBBEAR unlocked by Master 6 1 PCICO_PLBBEAR locked by Master 6 13 11 M7ET Master 7 Er...

Page 420: ...s the PCI power management capability structure 01 Figure 17 51 Capability I entifier PCICO_CAPID I PCI Capability Identifier 17 5 3 31 Next Item Pointer PCICO_NEXTIPTR PCICO_NEXTIPTR describes the lo...

Page 421: ...ement management state therefore D1 S is state is supported hardwired to 1 8 6 AUXCUR Auxiliary Current Support The PCI bridge does not support Aux_Current therefore AUXCUR is hardwired to ObOOO 5 DSI...

Page 422: ...7 2 Reserved Returns 0 when read 1 0 PSTAT Determine the current power state of a If software attempts to write a value for an function and sets the function into a new unsupported power state to PST...

Page 423: ...this bit o No write to PCICO_CMD has occurred 1 External PCI master has written to PCICO_CMD 12 DPR Drive PCI Reset Software that asserts this bit must leave is o Normal operation asserted long enoug...

Page 424: ...pts to access the PCI bridge PCI configuration registers are retried This give the local CPU PLB master time to initialize them before the host sees them In synchronous mode the PCI subsequent target...

Page 425: ...t The PCI bridge sets SCR when a host writes PCICO_PMCSR to request a power management state change This drives an interrupt to the local processor informing it of a state change request The local pro...

Page 426: ...e taken for each and how to reset a given error 17 6 1 PLB Unsupported Transfer Type This error occurs when the bridge PLB slave encounters an unsupported PLB transfer type Table 17 11 outlines transf...

Page 427: ...no PCICO_PLBBEAR or PCICO_PLBBESRx update is performed 17 6 3 Bridge PCI Master Receives Target Abort While PCI Bus Master This error is generated when the bridge PCI master receives a target abort w...

Page 428: ...s error The following status bits are set 1 PCICO_STATUS DEPE 1 to indicate a PCI bus parity error Setting this field is non maskable Writing a 1 to PCICO_STATUS DEPE clears the field 2 PCICO_STATUS S...

Page 429: ...or is detected during the address phase of a cycle in which the bridge is the PCI target PCI uses even parity Setting PCICO_CMD PER masks this error This error does not have an explicit status bit how...

Page 430: ...wer Management Interface Specification Revision 1 1 PCI PM 17 8 1 Capabilities and Power Management Status and Control Registers The PCI bridge has a capabilities structure in the PCI configuration sp...

Page 431: ...dled with the following sequence 1 The host requests a new power state by a PCI write to the PCICO_PMCSR 2 The host PCI write is retried unless PCICO_PMSCRR DWE 0 3 The host PCI write retried or not s...

Page 432: ...reset they must be initialized before attempting to generate PCI memory cycles When the PCI bridge is a target on the PCI bus the PCI bridge can respond to memory cycles The memory cycle address range...

Page 433: ...000000 20000000 10000000 o CPU PLB PTM1 BAR1 PCI Memory Space 34000000 30000000 j 28000000 1r 0 10000000 o Figure 17 59 Example Address Map PPC405GP User s Manual Preliminary Prefetchable PCI Targets...

Page 434: ...ditional register initialization is required as follows Error handling is initially disabled error detection is masked If error handling is to be enabled PCICO_ERREN must be initialized appropriately...

Page 435: ...o the PMMO registers Note The PPC405GP allows booting from PCI memory See Chapter 9 Pin Strapping and Sharing for more information 17 9 5 Type 0 Configuration Cycles for Other Devices Twenty one devic...

Page 436: ...Figure 17 61 and Figure 17 68 show a PCI Master executing a 128 byte Write to SDRAM PCI bridge accepts several beats of data into its 64 byte write buffer before executing variable length doubleword...

Page 437: ...o PCI Memory DMA Transfer Figure 17 66 and Figure 17 73 show a DMA transfer of data from SDRAM to PCI memory The DMA PLB Master executes a 4 doubleword read burst from SDRAM followed by a 4 doubleword...

Page 438: ...Preliminary PCI Interface 17 67...

Page 439: ...______ _ I y RdDBusO 31 _ _ I __ zIN DO RdDBus32 63 11 I ttI Mm ffMi_IIIJ_ t D1 PCIClk U U U U U U U U U U U U U PCIC BE 3 0 1ICEQ 6jhoi ltItIWII 1ilii lliitiO 17 68 PCIFrame _ _ __ _ _ _ 0 1 1 PCIDev...

Page 440: ...EO 7 __ __ __ __ __ __ __ __ R W AddrAck __ __ __ J __ L __ L __ L __ __ J __ _ RdDBusO 31 IX 06 UD 010 016 022 RdDBus32 63 IX 07 x QD 011 017 023 PCIClk PCIAD31 0 PCIC BE 3 0 hO PCIFrame PCIIRDY PCIT...

Page 441: ...dDBus32 63 PCIClk PCIAD31 0 PCIC BE 3 D LI_ _ _ _ _ _ _ _ _ _ _ hO ___________ l PCIFrame _ __ _ _ _ __ _ _ _ __ _ _ _ PCIIRDY _ PCITRDY 7 PCIStop PCIDevSel _ ______________________________ Figure 17...

Page 442: ...200 l E t t c tl RiW AddrAck 1 _ l 1 _ L L _ 1_ l lL L _ l L _ L L _ I J _ _ _ RdOBusO 31 k 046 c ib fI M fJ tf i t tl t i l a t4 t _14 tiW fr 6 j 1 RdOBus32 63 047 C i fi Y0 r k2PL K I J it j 1hg 1 g...

Page 443: ..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AddrAck 0 RdDBusO 31 RdDBus32 63 PCIClk PCIAD31 0 1i fii llI r J 1 C J PCIC BE 3 0 ______________________ I PCIFrame __ __ __ __ ____ __ ______ ____ __ __ __ o...

Page 444: ...RdDBusO 31 B I v j i t i i Y f i h i i t gi iS nt r Mv RdDBus32 63 ft ifi lt U ji J S L idN i t J t2 lf f S Y ZA0 i ti jS 1 PCIClk PCIAD31 PCIC BE13 J P C IF ra tn e PCIFrame PCIIRDY PCIIRD t P C IT R...

Page 445: ...I I I I I I I I I I I I I I I I I RAN __ __ __ __ __ __ __ __ __ __ _ AddrAck ________________________________________________ WrDAck PCIClk PCIAD31 0 Dt I _ _ 117 I a 1 III iltl I i D24 PCIC BE 3 0 M...

Page 446: ...__________________________________ AddrAck _ l _ _ l _ _ l _ l_ J _ _ l _ _ WrDAck __ _ _ _ _ _ _ _ ____ __ RdDBusO 31 _ I j _ __ RdDBus32 63 I Wi i __ PCIClk PCIAD31 0 I I I I I PCIC BE 3 0 1 1_ _ _...

Page 447: ..._ _ ___ __ ______ __ _ _ 1 __ __ __ _ RdDAck o_ _ o _ o __ ___ _ __ _Jr _ _____ ___ RdDBusO 31 4 11_ PCIClk Gnt ____ __ __ __ ____ __ __ ____ __ __ ____ __ ___ PCIAD31 0 if PCIC BE 3 0 1M II tc Jh 6C...

Page 448: ..._____ ____ RdDBusO 31 RdDBus32 63 l il CQ Je PCIClk Gnt ___ ___ ___ ___ ____ ___ ___ PCIAD31 0 L 1 A 1 J iMii j r cgDI PCIC BE 3 0 I h6 X hO U I t PCIFrame __ J I PCIIRDY I I PCIDevSel I Figure 17 62...

Page 449: ......

Page 450: ...A2 X A3 X A4 X A5 X A6 x J RiW AddrAck RdDAck 8 8 8 8 r o 0 0 RdDBus32 63 ID j ijllt il lij 4 n li4 tl 6Y j l t i t8 1t 1 1 tC _ _ PCIClk PCIAD31 0 PCIC BE 3 0 PCIFrame PCIDevSel Figure 17 63 CPU Rea...

Page 451: ...A10 X A11 x J Rm RdDAck 8 I I 8 I I 8 I I 8 I I r RdDBusO 31 g 0 RdDBus32 63 I I 8 9 0 PCIClk Gnt PCIAD31 0 PCIC BE 3 0 PCIFrame PCIIRDY PCITRDY PCIStop PCIDevSel Figure 17 63 CPU Read From PCI Memory...

Page 452: ...dDBus32 63 PCIClk PCIAD31 0 PCIC BE 3 0 PCIFrame PCIDevSel hFF X hOF X hFF X hOF A12 X A13 X A14 X A15 f 8 8 8 08 041 1I11111 llIijl I 4 1I11 ltllllrn IIIIIIII I Figure 17 63 CPU Read From PCI Memory...

Page 453: ...hFF X hOF X hFF X hOF ABusO 31 AO X A1 X A2 X A3 X A4 X A5 tIIcID RiW AddrAck WrOAck WrOBusO 63 00 X 01 X 02 X 03 X 04 X 05 PCIClk Gnt PCIAD31 0 AO A1 A2 PCIC BE 3 0 h7 h7 h7 XfiQJ PCIFrame PCIIROY L...

Page 454: ...lk BEO 7 hFF hFF X hOF hOF Jt i i i i I I I I ABusO 31 A6 A6 X A7 A7 f l RfiN AddrAck 1 1 WrOAck J t t WrOBusO 63 LX 06 t 06 X 07 S 07 II vl PCIClk PCIA031 0 Ac 3_ O 4_ Ac 5_ PCIC BE 3 0 h7 h7 h7 PCIF...

Page 455: ...__ __ ___ WrDAck ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ __ ___ WrDBusO 63 11 PCIClk Gnt PCIAD31 0 A6 X 06 1 Nt A7 X 07 fall PCIC BE 3 0 h7 X hO II I h7 X hO BIt PCIFrame PCIIRDY r PCITRDY r...

Page 456: ...Preliminary PCllnterface 17 85...

Page 457: ...I I I I I I RdDBus32 63 M Mll iill1f1 1 Mi 10i KI iiq 1 d ii f 111f t iY i if0 l t L 0RWf 0f Ff i L iji i Tj i i O il t ijiCii cr t fj W tiil fl I I I I I I I I I I I I I I I I I I I I WrDAck ____ __...

Page 458: ...RdDBusO 31 L A X X X t i L L i i i ciJLc d Ft t RdDBus32 63 I i i ii f f if C sy r j 4 WrDAck __ __ __ __ __ L L__ _ _ L L__ _ J I WrDBusO 31 C X i_ WrDBus32 63 ii 1 I iix h j 0 X i ii t T XSi X i f...

Page 459: ...sO 31 RdDAck r T RdDBusO 31 RdDBus32 63 WrDAck __________________ ____________ ________________________________ WrDBusO 31 WrDBus32 63 PCIClks Ln Gnt PCIAD31 0 PCIC BE 3 0 PCIFrame PCIIRDY PCITRDY PCI...

Page 460: ...__ _ _ _ _ _ _ _ _ RdDBusO 31 RdDBus32 63 WrDAck I I I I I I I I I I I I I I I I I I I I WrDBusO 31 _ 1J WrDBus32 63 fl il Ii Ii I 111 11 11811111_111 1 IIliMl 1 1 1 1 1_1111 1 PCIClk Gnt PCIAD31 0 p...

Page 461: ...dDBusO 31 RdDBus32 63 WrDAck WrDBusO 31 WrDBus32 63 PCIClk l Gnt PCIAD31 0 05 X ____ 0 6____ X JOll I lillllllll PCIC BE 3 0 11 PCIFrame PCIIRDY PCITRDY PCIStop PCIDevSel Figure 17 66 SDRAM To PCI Mem...

Page 462: ...Preliminary PCI Interface 17 91...

Page 463: ...ple pages Each diagram begins with cycle 1 on the left facing page Cycles PLBClk BEO 7 ABusO 31 RNi AddrAck RdDAck RdDBusO 31 I I I I I I RdDBus32 63 I PCIClk PCIAD31 0 AO PCIC BE 3 0 II hC X hO PCIFr...

Page 464: ...illnlllll I Ill i lIi l l i iillll i I I i I l e lii I 1 1i 1 1i 1 i I II PJW RdDBusD 31 RdDBus32 63 AD PCIC BE 3 D i illl li B iIIt f i i __________________________ hC X PCIFrame PCIDevSel Figure 17...

Page 465: ...31 Idilii i 4 1 RdDBuS32 63 ii WI 94 _I 1 PCIClk PCIAD31 D 02 X 03 X 0 4__ X __ 0 5__ X __ 0 6__ X __ 0 7__ X D8 PCIC BE 3 D PCIFrame PCIIRDY PCITRDY PCIStop PCIDevSel Figure 17 67 PCI Master Burst R...

Page 466: ...ck _ 0 _ r r r r r RdDBusO 31 1Ijfi ilttf st tn 1j i lj f mtwi fiii j lr if itiX 024 RdDBus32 63 i il 11t y4ii W jo iHr riW illliiliWji i1 1iYil Y l vtx 025 PCIClk PCIAD31 0 D _ 0 9_ JX 010 X 011 X 01...

Page 467: ...dDAck f 7 f 7 f 7 RdDBusO 31 iI Ii iI RdDBus32 63 PCIClk PCIAD31 0 D16 X D17 X D18 X D19 X D20 X D21 0 PCIC BE 3 0 hO PCIFrame PCIDevSel Figure 17 67 PCI Master Burst Read From SCRAM Continued 17 96 P...

Page 468: ...il Wii 1ii iU v I i ilt jS h tq t ii d c bL i yk t i i AdDBus32 63 ll jjl_ k a J Jl Jai0 tiG is in i4fii 4 if s 4 ri 2 kIz i a J ij2 YUYj Kif i t j f 4 PCIClk PCIAD31 0 D22 X 023 X 024 X 025 X 026 X...

Page 469: ...044 X 046 X 048 050 X 052 81 RdDBus32 63 ex 043 X 045 X 047 X 049 X 051 X 053 l1li PCIClk r PCIAD31 0 029 X 030 X 031 I I PCIC BE 3 0 PCIFrame PCIIRDY PCITRDY PCIStop 1 PCIDevSel Figure 17 67 PCI Mast...

Page 470: ...Preliminary PCI Interface 17 99...

Page 471: ...____ ____ __________ __ AddrAck i i i PCIClk PCIAD31 0 PCIC BE 3 0 It A O X D O X D 1 X D 2__ XL D 3 h __ X I PCIFrame PCIIRDY L____ PCITRDY L____ PCIStop PCIDevSel L ________________________________...

Page 472: ...tJ tl 60 k1 al i df ij J i tj r i PCIClk PCIAD31 0 D5 X __ D 6 JX __ D 7 JX __ D 8 JX D9 X D10 x J PCIC BE 3 0 1 ____________________________________ 1 PCIFrame _ ___ ___________ ___ ____ ___ _ PCIIR...

Page 473: ...__ __ __ __ __ __ WrOAck __ __ __ __ __ __ __ __ __ _ _ ___ WrDBusO 31 WrOBus32 63 IIII III1 liliiii PCIClk PCIA031 0 011 L r X 012 X 013 X 014 X 015 X 016 X 017 PCIC BE 3 0 hO PCIFrame PCIIRDY PCITRO...

Page 474: ...y tk kB i iif i 1 WrDBus32 63 0 o 6 fjf jf i iiiil t i tl 0_ iOiiioi t 7 oiiOiiot n j PCIClk PCIAD31 0 p 018 X _0 1 9 JX 020 X 021 X 022 X 023 Ej PCIC BE 3 0 PCIFrame ________ ________ ________ __ PC...

Page 475: ...lll IIIII WrDBus32 63 M lelfrl li I I I II 1 PCIClk PCIAD31 0 CQEJ D25 X D26 X _D_2_ X D28 X D29 X D30 XJ PCIC BE 3 0 PCIFrame PCIIRDY PCITRDY __ ______ ________ ______ ________ ______ ______ ___ PCID...

Page 476: ..._ __ ____ _ AddrAck WrDAck r orJ 1 WrDBusO 31 l i 4 t i j t 4 FC i k t t i 1 L i i 030 3j I I I I I I I I I I WrDBus32 63 tS i if Y t x t jV f fu V S i i E j 1 it T t i 031 e Il PCIClk IL ___ PCIAD31...

Page 477: ...X i_ _ I ABusO 31 _ _ _ A O _ _ _ X _ _ I RiW L 0 AddrAck r _ _ _ _ _ J _ _ RdDAck I r r RdDBusO 31 A_ I i 4M AII AO XII DO 11 h6 X hO I I i I I I Figure 17 69 CPU Read From PCI Memory Slave Nonprefet...

Page 478: ...ck RdDBusO 31 RdDBus32 63 22 A1 PCIAD31 0 EI4 _ A 1 J f I gDI1 J tt PCIC BE 3 0 __ h 6__ JX _____ h O_______I g PCIFrame _ 11 1 I 1 PCIDevSel 1 Figure 17 69 CPU Read From PCI Memory Slave Nonprefetchi...

Page 479: ...fB A1 8 r 1 RdDBusO 31 _ __ 1 _ __ RdDBus32 63 tp fw ilMWP 4MIIIt IWt MMiffi1 4U ii f PCIClk Gnt PCIAD31 0 MJ AO 4 tit DO X D1 X D2 X D3 PCIC BE 3 0 hC X PCIFrame PCIIRDY PCITRDY PCIStop PCIDevSel Fig...

Page 480: ...X hFF A4 X A5 X A6 f 1 r D3 D4 RdDBus32 63 QDD1 K D 2 KfD 3 t D4 11 ta PCIClk Gnt PCIAD31 0 D D 4 JX _D_5_ JX D 6 JX D7 X D8 X D 9 CQ1Q PCIC BE 3 0 hO PCIFrame PCITRDY PCIStop PCIDevSel _ _ _ _ _ __ F...

Page 481: ...DAck RdDBusO 31 O I RdDBus32 63 OQj6 t 07 t111 t os9II1I 1 o PCIClk PCIA031 0 I 011 X 012 X 013 X 014 X 015 en PCIC BE 3 0 L ________________________________________ I III1IiI 1 PCIFrame PCIOevSel Fig...

Page 482: ...I 76 I 77 I 78 I 79 I hFF A14 X hOF i it q X A15 i L i J dJ il 1 __ n __ n RdDBusO 31 V i6 i i i2S tr is t iL j 1 ii i t t i 1 RdDBus32 63 i X i i 3 H i JFi V li j X I i t cV e Q B li itl iftll 1t j...

Page 483: ...I I I I I I I I I ABusO 31 I AO X A1 X A2 X A3 X A4 X A5 Rm I I I WrDBusO 63 L D 0 X _ D 1_ JX _D 2 X _ D 3_ JX _D 4 X D5 IICQ PCIClk Gnt r PCIAD31 0 AO X DO A1 X D1 II1II PCIC BE 3 0 h7 X hO h7 X hO...

Page 484: ...Rm AddrAck 1 WrOAck 1 I I I WrOBusO 63 06 06 III 06 X 07 8 07 q PCIClk Gnt PCIA031 0 A2 X D2 A3 X 03 0 PCIC BE 3 0 h7 x hO h7 X hO i td PCIFrame PCIIROY I PCITROY PCIStop PCIOevSel Figure 17 71 CPU Wr...

Page 485: ...hOO I ABusO 31 hOOOOOOOOOOOOOOOO RIW AddrAck WrDAck WrDBusO 63 hOOOOOOOOOOOOOOOO PCIClk Gnt PCIAD31 0 A4 X D4 41 X A5 X D5 A6 PCIC BE 3 0 h7 X hO 11 I h7 X hO i Ix h7 PCIFrame PCIIRDY I I PCITRDY PCIS...

Page 486: ..._ _ _ _ ___J Rm _ _________________________ ______________ AddrAck _ _ __ _ WrDAck WrDBusO 63 i hOO OOOOOOOOOOOOOO PCIClk I II Gnt PCIAD31 0 __ D 6__ fSt 1 1 A 7 X D 7 PCIC BE 3 0 tx_ _ h O_ _ i i i f...

Page 487: ...63 1 1 h30 WrDAck __ __ __ __ __ __ __ __ __ __ ___ WrDBusO 31 WrDBus32 63 PCIClk Gnt ________ ________ ______ ________ ________ ______ _____ PCIAD31 0 1 C g C PCIC BE 3 0 1 lf C E PCIFrame PCIIADY P...

Page 488: ...i ii t ABusO 31 RiW AddrAck ____ __ ____ _____ __ 0 _ ______ I I I I I RdDBus32 63 _ 4 _ fEi t _ 1I_ WrDAck _7 7_ 7_ I I I I WrDBusO 31 _ e wi _ _il I I I I I I I I I I I I I I WrDBus32 63 t t teIfIlI...

Page 489: ...II I IMAI MI 1 1 1 1 1 1 1 11 1 1 1 11 1 1 _1 l illliRa RdDBus32 63 ettt WrDAck WrDBusO 31 WrDBus32 63 PCIClk L _ _ _ _ _ I PCIAD31 0 PCIC BE 3 0 PCIFrame PCIIRDY PCITRDY PCIDevSel 1 I DO X 02 X 04 W...

Page 490: ...Preliminary PCI Interface 17 119...

Page 491: ...4 Ei tb U i4 ig6 DO D1 1 I II Imim W mm WrDAckr __ __ __r __ __ __ r__ __ r__ __ __ __r ___ WrDBusO 31 WrDBus32 63 111 rII 14I ii lnw l mlili l11I1I I i 41114 ilIA 1MII 1I1 lil l II 1 4 1 1 GNT_N __ _...

Page 492: ...i tti i f w I t fji iC it iitll l ti ii WlB1_ ljt it RdOBus32 63 h i _i tit tlll tm1 4tP fu i f 1f_ f1 i i I l _t PCIClk PCIA031 0 R_i_ 4 _ A1 x DO X 01 X 02 PCIC BE 3 0 lUili_W ijbjitN h7 X PCIFrame...

Page 493: ..._ _ __ _ WrOBus32 63 PCIClk Gnt _____ _____ _____ ____ ______ _ PCIA031 0 0 _ 0 3__ r X __0 4 __ r X 05 X _ 0 6_ X _ 0 7 r PCIC BE 3 0 ________________ hO ________________________ PCIFrame ____ ______...

Page 494: ...ttached to the ESC via the DMAReqn DMAAckn and EOTn TCn I Os along with the OPS attached UARTO 18 1 External Interface Signals Figure 18 1 illustrates the externall Os associated with the DMA controll...

Page 495: ...he source prior to writing the data to the destination Since many buses including the internal PLB and the SDRAM interface provide substantially better performance when bursting data the DMA controlle...

Page 496: ...ansfer Since this is inefficient the buffer should only be disabled for low data rate transfers or when the source memory is FIFO like and reads are therefore destructive When the 32 byte buffer is en...

Page 497: ...ond to a state that ever existed in the DMA controller To illustrate consider software that reads the destination address for channel 0 DMAO_DAO and then the count for channel 0 DMAO_CTO If the DMA co...

Page 498: ...ration Register DMAO_POL is used to set the polarity active state of the external DMA 1 0 signals DMAReqn DMAAckn and EOTn TCn As shown in Figure 18 2 if a bit in DMAO_POL is zero the corresponding si...

Page 499: ...O_SLP enables the DMA controller to enter sleep low power mode and programs the number of PLB clock cycles to wait when the controller is idle before going to sleep The DMA controller only goes to sle...

Page 500: ...rmed by writing a word to DMAO_SR containing a 1 in any bit position to be cleared and in all other bit positions The terminal count status DMAO_SR CSn end of transfer status DMAO_SR TSn and error sta...

Page 501: ...tive DMA channels Before a DMA channel can transfer data the channel control source address destination address and transfer count registers must be programmed If a DMA channel is setup for scatter ga...

Page 502: ...if the transfer width is a doubleword 64 bit 7 SAl Source Address Increment o Do not increment source address 1 After each data transfer increment the source address by 1 if the transfer width is a by...

Page 503: ...rity checking for peripheral o Disable parity checking mode transfers See Data Parity During 1 Enable parity checking DMA Peripheral Transfers on page 18 14 29 DEC Address Decrement If DEC 1 it is req...

Page 504: ...stination address increment bit in the channel s control register is set DMAO_CRn DAI the address is incremented by the transfer width after each data transfer However if the channel is performing a p...

Page 505: ...MAO_CTO DMAO_CT3 Reserved Number of transfers remaining 18 3 8 DMA Scatter Gather Descriptor Address Registers DMAO_SGO DMAO_SG3 When a DMA channel is setup for scatter gather transfers DMA_SGC SSGn 1...

Page 506: ...Gather descriptor table DMAO_SGC SSGn is cleared for the affected channel and the channel s error status bit DMAO_SR Rln is set For additional details see Scatter Gather Transfers on page 18 16 SSGO...

Page 507: ...ecking 18 6 Errors The DMA controller detects and reports three types of errors address alignment PLB timeout and slave errors The DMA controller reports errors through the channel error status bit in...

Page 508: ...m a particular DMA channel are enabled by setting the channel enable bit in the channel s control register DMAO_CRn CIE 1 When an interrupt occurs for a given channel the DMA controller sends a signal...

Page 509: ...ddress x 12 LK I ITCI IETI IERI I I I Count x 16 Next Scatter Gather Descriptor Table Address Table 18 6 details the usage of the bit fields in the scatter gather table Table 18 6 Bit Fields in the Sc...

Page 510: ...e configured when the DMA controller is first initialized To prevent spurious activity resulting from changing the active level for DMAReqn DMAAckn or EOTn TCn a channel s configuration in the Polarit...

Page 511: ...ral bus and DMAAckn becoming active Following the setup time DMAAckn is driven active for DMAO_CRn PWC 1 PerClk cycles During peripheral to memory transfers read data from the peripheral is sampled on...

Page 512: ...use the DMA controller does not pack or unpack data on the peripheral side of transaction Peripheral to Memory Transfer To perform a peripheral to memory DMA transfer from an ESC attached DMA peripher...

Page 513: ...AReqn pin for the channel The PPC405GP then reads the source memory and subsequently activates the DMAAckn pin to write data to the peripheral This continues until either a terminal count or end of tr...

Page 514: ...ated Memory to Memory Transfers Non Deviced Paced To perform a software initiated memory to memory DMA transfer 1 Set the transfer width DMAO_CRn PW as desired 2 Set the source DMAO_SAn and destinatio...

Page 515: ...18 22 PPC405GP User s Manual Preliminary...

Page 516: ...y for each of the three EMAC channels one receive and two transmit Software a device driver is responsible for maintaining a buffer descriptor ring and a set of data buffers in external memory for eac...

Page 517: ...from the receive channel 19 1 EMAC Features The PPC405GP EMAC features Dual speed 10 100 Mbps CSMAlCD half duplex and full duplex Ethernet MAC compliant with ANSI IEEE Std 802 3 and IEEE 802 3u supple...

Page 518: ...ncluding self assembled control pause packet transmitting Support for VLAN tag ID in compliance with IEEE Draft 802 3ac D1 0 standard VLAN tag insertion or replacement for transmit packets is a progra...

Page 519: ...ets against a set of predefined addresses specified by the current address filtering mode EMAC contains one unicast individual address register two hash tables for filtering individual and group addre...

Page 520: ...with or without a PHY connected to EMAC In internal loop back mode EMAC does not activate monitor any Mil signals The transmit channel signals are buffered internally to the receive channel However if...

Page 521: ...nding interrupt is not masked in the EMACO_ISER After such an error the channel sets EMACO_TMRO GNPO GNP1 0 as appropriate and sets EMACO_ISR DBO 1 or EMACO_ISR DB1 1 the EMACO_ISR field that is set d...

Page 522: ...rol status field of the buffer descriptor to both provide EMAC with control information write and to obtain packet status from EMAC after transmission is complete read Software writes the control bits...

Page 523: ...ansmission of a frame the PHY_CRS input was de asserted after it previously was asserted or it was not asserted at all 9 Excessive deferral o No excessive deferral R 1 Indicates that the current frame...

Page 524: ...s the first 64 bytes of the packet until it receives an indication that the collision window has passed Otherwise if a collision was detected within the collision window the packet is retransmitted au...

Page 525: ...e packet up to the minimum allowed size FCS Cycle Redundancy Check 4 bytes FCS Figure 19 5 Transmit Packet Structure Excluding VLAN Tagged and Control Packets The following options can be set for each...

Page 526: ...VLAN TCI registers for the VLAN Tag value This feature is supported only when the packet coming from the Transmit FIFO does not contain an FCS This mode is mutually exclusive with the VLAN Tag inserti...

Page 527: ...s control field Software uses this information to monitor the status of received packets See Buffer Descriptor Overview on page 20 7 for more information on the buffer descriptor structure o 2 3 4 5 6...

Page 528: ...a description of conditions for activating R this status bit Table 19 4 In Range Length Error Behavior for Various Packet Lengths Programmed Length Bytes Actual Length EMAC Action Less than 46 Differ...

Page 529: ...on a powered off client decodes this data field a wake up signal is generated In the 405GP with WOL mode enabled the EMAC discards all incoming packets and does not request data from the MAL for trans...

Page 530: ...ance by handling specific MAC control packets contained in the pause opcode EMAC supports flow control as defined in the IEEE 802 3x 1997 standard 19 5 1 MAC Control Packet The flow control mechanism...

Page 531: ...h the destination address specified to temporarily suspend the transmission of packets to EMAC Option 1 Software initiated The packet transferred to EMAC by MAL for transmission is a pause packet crea...

Page 532: ...When response to pause packets is enabled and EMAC detects a valid MAC control packet with a Pause opcode EMAC stores the value of the Timer Value field The received packet is considered a valid cont...

Page 533: ...recently received packet regardless of the current pause timer setting This indicates new pause operations take precedence over earlier pause operations 19 6 VLAN Support EMAC can handle VLAN tagged p...

Page 534: ...e following configuration options are available depending on the content of the appropriate bits in the MAL control word see section 19 3 3 1 MAL TX Descriptor Control Status Field on page 7 The Gener...

Page 535: ...ividual Address Low EMACO_IALR register When EMAC operates in multiple individual mode EMACO_RMR MIAE 1 EMAC performs a calculation on the contents of the DA field logical address filter to determine...

Page 536: ...ss is sent through the FCS circuit After the 48 address bits have gone through the FCS circuit the high order six bits of the resulting FCS 32 bit CRC are used to select one of the 64 bit positions in...

Page 537: ...ACO_RMR PME 1 3 EMACO_RMR IAE 1 and DA matches EMACO_IAHR and EMACO_IALR 4 EMACO_RMR MIAE 1 and selected Individual Address filter bit is a 1 5 EMACO_RMR PMME 1 and DA O 1 6 EMACO_RMR BAE 1 and DA mat...

Page 538: ...isters The EMAC registers are accessed through the OPB Access to the registers should be word aligned Table 19 5 EMAC Register Summary Power on Register Name Address Write Access Reset Value Access Pa...

Page 539: ...ACO_GAHT1 OxEF600840 Reset R OxOOOOOOOO R W 19 37 EMACO_GAHT2 OxEF600844 Reset R OxOOOOOOOO R W 19 37 EMACO_GAHT3 OxEF600848 Reset R OxOOOOOOOO RIW 19 37 EMACO_GAHT4 OxEF60084C Reset R OxOOOOOOOO RIW...

Page 540: ...ster is not supported 3 TXE Transmit MAC Enable oTX MAC is disabled 1 TX MAC is enabled 4 RXE Receive MAC Enable oRX MAC is disabled 1 RX MAC is enabled 5 WKE Wake Up Enable Software can change EMACO_...

Page 541: ...re details mechanism Set EMACO_MR1 EIFC 0 in half duplex 1 Enable integrated flow control mode mechanism 4 APP Allow Pause Packet o Disables processing of incoming control pause packets 1 Enables proc...

Page 542: ...ns see EMAC Transmit Operation on page 19 5 EMACO_TMRO GNPO GNP1 GNPD are self clearing Writing 0 to these fields has no effect GNPOGNFD t t 311 GNP1 FC Figure 19 17 Transmit Mode Register 0 EMACO_TMR...

Page 543: ...he sum of EMACO_TMR1 TRL and EMACO_TRTR TRT must be at least 4 smaller than the transmit FIFO size specified by EMACO_MR1 TFS 19 7 4 2 Urgent Priority Requests EMAC requests urgent priority service fr...

Page 544: ...Discard packets less than 64 bytes in length 1 Receive packets less than 64 bytes in length 3 RFP Allow Receive Packets with a FCS Error o Discard packets containing a FCS error 1 Receive packets cont...

Page 545: ...t addresses 1 Compare address of received packets with multicast addresses 13 31 Reserved 19 7 6 Interrupt Status Register EMACO_ISR EMAC generates one distinct interrupt event indication The event in...

Page 546: ...events 1 Duration of PHY_RX_DV signal less than ShortEventMaxTime constant 11 ALE Alignment Error The packet contained an odd number of oNo alignment error in received packet nibbles 4 bits 1 Alignmen...

Page 547: ...EMACO_ISR DBO does not affect TX Channel 0 while not in dependent EMC_INT mode 24 SE SQE Error 0 Applicable only in half duplex mode during o No SQEs on TX Channel 0 10 Mbps operations 0 in all other...

Page 548: ...ead from the PHY 19 7 7 Interrupt Status nable Register EMACO_ISER The EMACO_ISER indicates which conditions in the EMACO_ISR can generate an interrupt Each masking bit in the EMACO_ISER corresponds t...

Page 549: ...FCS o FCS error in received packet will not generate an interrupt 1 FCS error in received packet will generate an interrupt 13 PTLE Packet Too Long Error o Oversized packets received will not generat...

Page 550: ...Y will generate an interrupt 19 7 8 Individual Address High EMACO_IAHR EMACO_IAHR contains the high order halfword of the station unique individual address During packet reception if EMAC is programme...

Page 551: ...Register EMACO_VTPID EMACO_VTPID contains the value of the VLAN TPID Tag Protocol Identifier field 31 During packet reception packet bytes 13 and 14 are compared to the content of this register to che...

Page 552: ...ash Tables 1 4 EMACO_IAHT1 EMACO_IAHT4 31 1 These registers are used in the hash table function of the multiple individual addressing mode See Address Match Mechanism on page 19 20 for more informatio...

Page 553: ...t Source Address Low EMACO_LSAL EMACO_LSAL contains the low order word of the source address of the last good received packet The packet is considered good if EMAC is programmed to provide this packet...

Page 554: ...om the PHY 2 The software can perform read write access to the EMACO_STACR 3 EMAC clears EMACO_STACR OC sets EMACO_STACR OC 0 and starts activity on the Mil management interface 4 Return to step 1 PHY...

Page 555: ...ransmit request to the Ethernet MAC sub block If an entire packet is already located in the Transmit FIFO then EMAC initiates a transmit regardless of the programmed value The software must coordinate...

Page 556: ...lso issued when the receive low water mark is reached Software must coordinate the value of EMACO_RWMR RLWM with the value of EMACO_MR1 RFS EMACO_RWMR RLWM should be smaller than EMACO_MR1 RFS and lar...

Page 557: ...ceived EMACO_OCRX 0 31 OCRX Number of octets bytes received This field is Read Only 19 8 Mil Interface EMAC implements all Mil interface functionality in accordance with Clause 22 in the IEEE Std 802...

Page 558: ...rred from the system s memory to EMAC while in receive the data is transferred from EMAC to the system s memory buffers EMAC remains in the packet phase until the data transfer has been completed or a...

Page 559: ...when EMACO_MR1 MF 1 and EMACO_MR1 FDE 0 In dependent mode EMACO_ISER24 25 must equal EMACO_ISER27 28 EMACO_MR1 EIFC 0 if EMACO_MR1 FDE 0 EMACO_TMR1 TLR must be greater than the MAL burst size in entit...

Page 560: ...Before performing the necessary configuration changes in EMAC the software must follow one of the following scenarios Then the EMAC can be properly configured 19 10 1 2 Scenario 1 Hard soft reset was...

Page 561: ...re performs the necessary EMAC configuration keeping EMACO_MRO RXE O The software can access only part of EMAC registers marked with write access mode R in Table 19 5 EMAC Register Summary on page 19...

Page 562: ...uses the buffer descriptors to convey packet transfer status from the COMMAC core back to the software device driver Each MAL channel requires its own buffer descriptor table ring structure in memory...

Page 563: ...ptors and provides all data access facilities to the COMMACs The MAL is not aware of COMMACs such as EMAC as an entity It is only aware of the COMMAC s channels In the PPC405GP EMAC contains two TX ch...

Page 564: ...tors and communicate status regarding data transfer 20 1 1 2 OPS Master The OPS Master performs OPS transactions for MAL and is used to transfer data between a COMMAC and memory 20 1 1 3 TX Channel Ha...

Page 565: ...actions 20 1 1 8 RX Common Channel Logic The RX common channel logic is shared by all RX channels It services a single RX channel at a time selected by the RX arbiter This logic activates the PLS and...

Page 566: ...MAL fetches descriptor information 6 MAL writes control information into the GOMMAG and initiates the data move 7 Packet data is transferred from memory into the GOMMAG the GOMMAG controls the pace o...

Page 567: ...itiates the data transfer 7 The eOMMAe channel fills its FIFO storage 8 MAL stores the packet in system memory buffers pointed to by the descriptors 9 MAL reads status information from the eOMMAe and...

Page 568: ...e data cache line and is simultaneously being updated in physical memory by MAL Data buffers in contrast should be placed in cachable memory if possible The software driver can easily maintain cache c...

Page 569: ...buffer in memory It is suggested that each data buffer start on a cache line boundary and be a multiple of a cache line in size if it resides in cachable memory The cache line size in the PPC405 proce...

Page 570: ...If the first descriptor is marked as ready MAL will start processing the associated buffer When MAL begins processing a packet it writes the contents of the descriptor status control field into the CO...

Page 571: ...Back Up a Packet for Transmit MAL is capable of re transmitting the last packet back up a packet following a request from a COMMAC If re transmission is requested by the COMMAC it must be assured that...

Page 572: ...e descriptor error had occurred interrupt bit for each TX channel see MAL Interrupt Enable Register MALO_IER on page 20 31 The second one is a maskable interrupt which indicates a descriptor error eve...

Page 573: ...y the first buffer descriptor The current buffer descriptor may be closed for two reasons there is no more room left in the buffer or the COMMAC channel indicated that the packet reception ended If ad...

Page 574: ...0 24 The actual data length field within the RX buffer descriptor is written by MAL If the buffer is completely filled up the value written will match the value programmed into the matching RX Channel...

Page 575: ...As MAL finishes processing the last buffer descriptor in a given packet it reads the channel s status via an OPB transaction and writes it into the buffer descriptor s status control field In effect...

Page 576: ...ot the last data buffer descriptor in the buffer descriptor table 1 This is the last data buffer descriptor in the buffer descriptor table After this buffer has been used MAL will transmit data from t...

Page 577: ...MAC channel related data COMMAC specific control or status fields Figure 20 8 RX Status Control Field Note The bit numbering in Figure 20 8 relates to the buffer descriptor s fullword which contains b...

Page 578: ...nt packet 1 This is the last buffer in the current packet This bit is updated by MAL following the activity of the channel 20 6 6 5 Bit 4 F First 0 This is not the first buffer in the current packet 1...

Page 579: ...ion or as part of the COMMAC initialization process In order to activate a channel the following actions should be taken The channel has to be configured in MAL The related bit in Channel Active Set R...

Page 580: ...Buffer Interrupt Status Registers on page 20 28 20 7 3 1 Error Detection The MAL communication both with COMMACs and with memory is carried out via the OPB or PLB As long as this bus communication is...

Page 581: ...eported by the OPB arbiter Following this error the active bit of the associated channel is reset and channel activity is halted until reactivated by software When the channel is reactivated MAL point...

Page 582: ...ocked in this mode so software can find out if more errors occur However the Error Status field applies only to the first error that is locked Non Locked Error Mode Information about the error is writ...

Page 583: ...registers see Channel Table Pointer Registers MALO_TXCTPxR MALO_RXCTPOR on page 20 33 in order to continue from the same buffer in memory In the case of PLB errors MAL does not know which channel caus...

Page 584: ...rupts enabled for this type of error in IER Error mode locked YES Is the Error valid bit in ESR set Update Error status bits Error status bits free update Error status bits Resume operation NO NO No i...

Page 585: ...Ox182 RIW Interrupt Enable Register MALDBR Ox183 R Debug Register MALO_TXCASR Ox184 RIW TX Channel Active Set Register MALO_TXCARR Ox185 RIW TX Channel Active Reset Register MALO_TXEOBISR Ox186 R Clea...

Page 586: ...is set MAL applies the GUARDED oGUARDED signal not signal to the PLB slave when it is the initiator on the applied to the PLB slave bus 1 GUARDED signal applied When set the slave can access all the m...

Page 587: ...s active 1 Scroll to the first descriptor of the next packet 20 8 2 Channel Active Set and Reset Registers For the Channel Active Set Reset Registers MALO_TXCASR MALO_TXCARR MALO_RXCASR MALO_RXCARR ea...

Page 588: ...ARR 0 1 Transmit Channel Active Reset Each bit represents its related channel bit 0 for channel 0 etc When 1 is written to the bit channel operation is disabled There are only two TX channels in the P...

Page 589: ...llowing conditions When MAL finishes the processing of a buffer writes back the status to the current descriptor the related bit in this register is set if the I bit in the descriptor status is set Wh...

Page 590: ...mode is active See Operational Error Modes on page 20 21 for description of the Locked error mode The error status field includes an Error Valid bit which indicates whether there is an error informati...

Page 591: ...Bit 1 indicates whether the channel 10 represents an RX channel 1 or a TX channel 0 Bits 2 6 indicates the number of the channel that caused the error Note An error on the PLB cannot be related to a c...

Page 592: ...d by the slave Set condition for 1 OPS error from a slave this bit generates a maskable interrupt 31 PSEI PLS Sus Error Interrupt This bit is set following a PLS error oNo error indication from the PL...

Page 593: ...ct When one or more of the TX Descriptor Error Interrupt bits is set then the MAL_TX_DESC_ERR_INT bit is set When one or more of the RX Descriptor Error Interrupt bits is set then the MAL_RX_DESC_ERR_...

Page 594: ...the MALO_TXCTPxR regsiter and then re enable them once the MALO_TXCTPxR register is set to its new value The TX and RX Channel Table Pointer Registers have an identical format as shown in Figure 20 22...

Page 595: ...20 34 PPC405GP User s Manual Preliminary...

Page 596: ...it will be in this mode and can be put into FIFO mode to relieve the processor of excessive software overhead Here internal FIFOs are activated allowing 16 bytes plus 3 bits per byte of error data in...

Page 597: ...parity overrun framing error simulation 21 2 Serial Input Clocking The two PPC405GP UARTs can be clocked individually from an external serial clock or from an internally generated serial clock The in...

Page 598: ...1200 31 5 3763 280 1200 076800 0 0064000 2400 31 5 3763 140 2400 153600 0 0064000 4800 31 5 3763 70 4800 307200 0 0064000 9600 31 5 3763 35 9600 614401 0 0064000 19200 32 5 2083 17 19148 284237 0 2693...

Page 599: ...EF60_0XOO 1 RIW UART x Divisor Latch LSB UARTx_DLM EF60_0X01 1 RIW UART x Divisor Latch MSB 1 UARTx_LCR DLAB controls the function accessed through registers EF60_0XOO and EF60_0X01 When UARTx_LCR DL...

Page 600: ...RTx_IER Any of the five interrupts can be used to surface a UART interrupt to the PPC405GP interrupt controller Each interrupt can be enabled by setting its appropriate bit Resetting UARTx_IER 4 7 tot...

Page 601: ...and character timeout indication 3 Transmitter holding register empty 4 Modem status Table 21 3 lists the interrupt priority levels Table 21 3 Interrupt Priority Level IIR IIR IIR Priority Bit4 BitS...

Page 602: ...el 3 Note Priority 1 is highest priority 010 Priority level 2 011 Priority level 1 100 Reserved 101 Reserved 110 Priority level 2 111 Reserved 7 IP Interrupt Pending When set to 0 IIR contents can be...

Page 603: ...ic to O The receiver shift register is not cleared This bit is self clearing 7 FE FIFO Enable When set to 1 both the receiver and o Disable FIFOs transmitter FIFOs are enabled When set 1 Enable FIFOs...

Page 604: ...ecked as O If UARTx_LCR EPS 0 and UARTx_LCR PE 1 the parity bit is transmitted and checked as 1 3 EPS Even Parity Select This bit is significant only if oGenerate odd parity UARTx_LCR PE 1 1 Generate...

Page 605: ...logic 1 their inactive state 5 The four modem control outputs are connected internally to the four modem control inputs Transmitted data is immediately received to verify the UART transmit and receive...

Page 606: ...r Empty Indicator o Reset to 0 whenever the THR or the transmitter shift register contain a character In FIFO mode it is reset to 0 whenever the transmitter FIFO or the transmitter shift register cont...

Page 607: ...ads processor when the character this error is UARTx_LSR associated with is at the top of the FIFO 1 Indicates that the received data Error causes a Receiver Line Status character does not have the co...

Page 608: ...input changed state status interrupt is generated 5 TERI Trailing Edge of Ring Indicator Indicates that the RI input to the UART oSet when processor reads the Modem changed from 0 to 1 since the proc...

Page 609: ...ue of o 1 0 Figure 21 11 UART Baud Rate Divisor latch MSB Registers UARTx_DlM I 0 7 I Data bits Note UARTx_DLM is shown in standard PowerPC bit notation where 0 is the MSb and 7 is the LSb 1 8 Figure...

Page 610: ...ailable indicator is issued when the number of characters in the FIFO has reached the trigger level programmed into UARTx_FCR This indicator is reset to 0 when the FIFO character count drops below thi...

Page 611: ...available interrupts and character timeouts all have equivalent second interrupt priority Current transmitter holding register empty interrupt and Transmit FIFO empty have equivalent third interrupt p...

Page 612: ...ter FCR In non FIFO mode DMA transfers are performed using single transfers using the UART s DMA mode O This section describes proper UARTO DMA programming For more information on general DMA programm...

Page 613: ...t 11111 Divide by 32 10MHz Note Maximum serial clock frequency is slightly less than 1 2x OPB frequency 31 Reserved 21 6 2 Transmitter DMA Mode The UARTO Transmit Channel Enable field of the Chip Cont...

Page 614: ...d DMAO_CR3 TD O DMA Channel 3 transfer direction is from memory to peripheral DMAO_CR3 PL 1 DMA Channel 3 peripheral is on the OPB UARTO DMAO_CR3 PW OO Peripheral width is byte 8 bits DMAO_CR3 TM OO D...

Page 615: ...ansfers Other DMA registers and register fields must be programmed appropriately see Chapter 18 Direct Memory Access Controller on page 18 1 for more information Table 21 6 UARTO Receiver DMA Mode Reg...

Page 616: ...IC interface supports 7 bit and 10 bit addressing for master and slave transfers Addressing is described in detail in IICO Low Master Address Register on page 22 5 IICO High Master Address Register on...

Page 617: ...ace For 1O bit addressing for master or slave transfers respectively IICO_HMADR AO A4 and IICO_HSADR AO A4 must contain Ob11110 The low order byte of the 10 bit address contained in AO A7 of address b...

Page 618: ...rol and IICO_XTCNTLSS OxEF60 050F OxF RIW Cleared 8 Slave Status IICO Direct Control IICO_DIRECTCNTL OxEF60 0510 Ox10 RIW OxOf 4 22 3 lie Register Descriptions The following sections contains the bit...

Page 619: ...IIC bus first followed by the LSB byte 1 IICO_MDBUF receives data from the IIC bus when the requested master transfer is a read The first byte received is the first byte read by software from IICO_MDB...

Page 620: ...es that the IIC interface transmits on the IIC bus Programming Note IICO_HMADR is used only for 10 bit addressing When IICO_CNTL AMD 7 bit addressing only IICO_LMADR is written IICO_LMADR AO A6 form t...

Page 621: ...O bit addresses 2 A2 Address bit 2 1 for 1O bit addresses 3 A3 Address bit 3 1 for 1O bit addresses 4 A4 Address bit 4 ofor 19 bit addresses S AS Address bit S MSb for 1O bit addresses 6 A6 Address bi...

Page 622: ...ated 1 AMD Addressing Mode Does not affect slave transfers a Use 7 bit addressing 1 Use 1a bit addressing 2 3 TCT Transfer Count 00 Transfer one byte 01 Transfer two bytes 10 Transfer three bytes 11 T...

Page 623: ...HT 22 3 6 IICO Mode Control Register The lIeo Mode Control Register IICO_MDCNTL sets the major modes of operation on the IIC bus In addition IICO_MDCNTL can force the data buffers into the empty state...

Page 624: ...errides this field if o Ignore general call on IIC bus IICO_MDCNTL ESMj 1 a general call is 1 Respond to general call on IIC bus ignored 3 FSM Fast Standard Mode o IIC transfers run at 100 kHz standar...

Page 625: ...22 10 IICO Status Register IICO_STS 0 SSS Slave Status Set Read only this field is set when any of the oNo slave operations are in progress following fields are set 1 Slave operation is in progress II...

Page 626: ...SCMP 1 Note that slave operations should be serviced regardless of the state of a requested master transfer The IIC interface is placed in sleep mode by setting the CPCO_ER IIC via software Awaking th...

Page 627: ...d IICO_MDCNTL IRQP 0 IICO_EXTSTS IRQP should be ignored 1 3 BCS Bus Control State Read only 000 Unused if this value is read a major IIC hardware problem occurred 001 Slave selected state the IIC inte...

Page 628: ...ted Transfer aborted When set to a 1 a No transfer is pending or transfer is in requested master transfer was aborted by progress a NOT acknowledge during the transfer of 1 A requested master transfer...

Page 629: ...Slave Address Register IICO_LSADR 0 AO Address bit 0 1 A1 Address bit 1 2 A2 Address bit 2 3 A3 Address bit 3 4 A4 Address bit 4 S AS Address bit S 6 A6 Address bit 6 LSb for 7 bit addresses 7 A7 Add...

Page 630: ...used to decode the first address byte that was transmitted on the IIC bus and bit 7 is in a don t care state 22 3 11 IICO Clock Divide Register The IICO Clock Divide Register IICO_CLKDIV establishes a...

Page 631: ...O Interrupt Mask Register IICO_INTRMSK specifies which conditions can generate an IIC interrupt when the IIC interrupt is enabled IICO_MDCNTL EINT 1 Figure 22 15 illustrates the IICO_INTRMSK EIRC EIWC...

Page 632: ...Q on Incomplete Transfer oDisable 1 Enable 6 EITA Enable IRQ on Transfer Aborted oDisable 1 Enable 7 EIMTC Enable IRQ on Requested Master Transfer Complete oDisable 1 Enable 22 3 13 IICO Transfer Coun...

Page 633: ...ve Status Register The IICO Extended Control and Slave Status Register IICO_XTCNTLSS provides additional control of IIC interface functions and reports the status of slave operations Figure 22 17 illu...

Page 634: ...CO_MDCNTL HSCL 1 and IICO_SDBUF contains data the slave will send the data IICO_XTCNTLSS SRS is not set unless the master requests additional data 2 SWC Slave Write Complete Normal operation or slave...

Page 635: ...For half word accesses these fields are valid on the third OPB clock following the transfer For byte accesses these fields are valid on the second OPB clock following the transfer If any of the follo...

Page 636: ...signals directly the IIC controller must be placed in the reset state IICO_XTCNTL SRST 1 IICO_DIRECTCNTL MSDA MSC are used to verify that IICO_DIRECTCNTL SDAC SCC were written successfully and that th...

Page 637: ...routine would not see status for the subsequent interrupts A more typical situation involves the case where an interrupt handler has read the IIC status for the active interrupt and a second on deck...

Page 638: ...slave needs service request manage the data first Read data out of the slave buffer IICO_SOB for slave reads or write data into the IICO_SOB for slave writes Next clear the slave needs service reques...

Page 639: ...22 24 PPC405GP User s Manual Preiiminary...

Page 640: ...programmed to emulate an open drain driver All module 1 0 inputs are synchronized to the OPSClk before being stored in the Input register All registers except the Input Register are both read and writ...

Page 641: ...e synchronized to DPBClk before being stored Table 23 1 Macro 110 Interface Signals Signal Name 1 0 Function GPI0_ln O 23 I Input to the GPIO Controller directly from Pin Z Receiver Output The bi dire...

Page 642: ...follows GPID Enable Disable 10 J 18 119 311 Figure 23 2 CPCO_CRO Bits Controlling GPIO 4 TRE CPU Trace Enable Trace interface cannot be used when GPIO o GPI01 9 are enabled is enabled 1 GPI01 9 are di...

Page 643: ...rrupt IR01 as GPI018 14 G19E GPIO 19 Enable o Enable interrupt IR02 as an interrupt 1 Enable interrupt IR02 as GPI019 15 G20E GPIO 20 Enable o Enable interrupt IR03 as an interrupt 1 Enable interrupt...

Page 644: ...the GPIO_ln state 23 5 2 Detailed Register Description The following sections provide a bit description of the GPIO registers All registers are accessed from the OPB The GPIOO_IR register is read only...

Page 645: ...ic is shown in the table below When emulating an open drain driver the module 1 0 driver never drives a 1 level It either drives a level or it is in the high impedance state emulating an open drain 1...

Page 646: ...3 28 register settings 10 40 summary 10 39 and 24 15 and 24 15 andc 24 16 andc 24 16 andi 24 17 andis 24 18 architecture PowerPC 1 4 arithmetic compares 3 13 arithmetic instructions 3 49 Preliminary a...

Page 647: ...X 2 PPC405GP User s anual bng 24 24 bnga 24 24 bngctr 24 28 bngctrl 24 28 bngl 24 24 bngla 24 24 bnglr 24 32 bnglrl 24 32 bnl 24 24 bnla 24 24 bnlctr 24 28 bnlctrl 24 28 bnll 24 24 bnlla 24 24 bnllr...

Page 648: ...24 38 cntlzw 24 38 compare instructions Preliminary arithmetic 3 13 in core listed 3 50 effect on CR fields 3 13 logical 3 13 Condition Register See CR conditional branches AA field 3 35 BI field 3 3...

Page 649: ...25 40 DCPO_CFG 14 6 25 41 DCPO_CFGADDR 25 42 DCPO_CFGADDR Decompression Controller Address Register X 4 PPC405GP User s Manua accessing 3 21 DCPO_CFGDATA 25 43 DCPO_CFGDATA Decompression Controller Da...

Page 650: ...ndirect access 3 20 offsets 3 20 EBCO_BEAR 25 68 Preliminary EBCO_BESRO 25 69 EBCO_BESR1 25 71 EBCO_BnAP 25 73 EBCO_BnCR 25 75 EBCO_CFG 25 76 EBCO_CFGADDR 25 78 EBCO_CFGADDR Peripheral Controller Addr...

Page 651: ...24 32 bflrl 24 32 bge 24 23 bgea 24 23 bgectr 24 27 bgectrl 24 27 bgel 24 23 bgela 24 23 bgelr 24 32 PPC405GP User s Manual bgelrl 24 32 bgt 24 23 bgta 24 23 bgtctr 24 27 bgtctrl 24 27 bgtl 24 23 bgt...

Page 652: ...eqv 24 41 for ernor 24 43 for eror 24 44 for erxor 24 46 for mfspr 24 113 Preliminary for mterf 24 116 for mtspr 24 120 for nor nor 24 139 for or or 24 140 for ori 24 142 for rlwimi rlwimi 24 146 for...

Page 653: ...31 25 94 GPRs general purpose registers interrupt control instructions 3 52 overview 3 6 summary 1 10 guarded G storage attribute controlled by SGR 6 19 preventing speculative accesses 3 37 virtual mo...

Page 654: ...0 bclr 24 30 bclrl 24 30 bl 24 19 bla 24 19 cmp 24 34 cmpi 24 35 cmpl 24 36 cmpli 24 37 cntlzw 24 38 Preliminary cntlzw 24 38 crand 24 39 crandc 24 40 creqv 24 41 crnand 24 42 crnor 24 43 cror 24 44 c...

Page 655: ...ianuai stb 24 156 stbu 24 157 stbux 24 158 stbx 24 159 sth 24 160 sthbrx 24 161 sthu 24 162 sthux 24 163 sthx 24 164 stmw 24 165 stswi 24 166 stswx 24 167 stw 24 169 stwbrx 24 170 stwcx 24 171 stwu 24...

Page 656: ...storage reference B 29 storage reference alignment of 3 27 storage reference in core 3 48 TLB management 3 53 interrupt controller interface 1 9 interrupt enable register Preliminary description 21 5...

Page 657: ...P User s Manual macchwsu 24 97 macchwu 24 98 machhw 24 99 machhwsu 24 101 machhwu 24 102 machine check interrupts causes 10 35 defined 10 23 machine check instruction interrupts handling 10 35 registe...

Page 658: ...3 mulhhwu 24 124 mulhwu 24 126 mulhwu 24 126 mullhw 24 127 mullhwu 24 128 mulli 24 129 mullw 24 130 mullw 24 130 mullwo 24 130 mullwo 24 130 N nand 24 131 nand 24 131 neg 24 132 Preliminary neg 24 132...

Page 659: ...ster See EBCO_CFGDATA physical address map 3 2 PIO 25 198 PIO process 10 X 14 PPC405GP User s Manual illustrated 6 12 PIT 11 4 25 199 PIT programmable interval timer interrupts register settings 10 41...

Page 660: ...AO DMAO_SA3 18 10 DMAO_SAO DMAO_SA3 25 62 DMAO_SGO DMAO_SG3 18 12 DMAO_SGO DMAO_SG3 25 63 DMAO_SGC 18 13 25 64 DMAO_SLP 25 65 DMAO_SR 18 7 25 66 during debug exceptions 10 45 Preliminary EBCO_BEAR 25...

Page 661: ...HA 25 188 PCILO_PMM1 PCILA 25 189 PCILO_PMM2LA 25 190 PCILO_PMM2MA 25 191 PCILO_PMM2PCIHA 25 192 PCILO_PMM2PCILA 25 193 PCILO_PTM1 LA 25 194 PCILO_PTM1MS 25 195 X 16 PPC405GP User s Manual PCILO_PTM2L...

Page 662: ...20 Preliminary SDRAMO_RTR 25 221 SDRAMO_TR 25 222 secondary opcodes A 33 serial interface characteristic 21 2 serial to parallel conversion 21 1 SGR 25 224 SGR Storage Guarded Register controlling spe...

Page 663: ...SUOR string instructions access protection 6 16 structure mapping examples 3 29 stswi 24 166 stswx 24 167 stw 24 169 stwbrx 24 170 stwcx 24 171 stwu 24 173 stwux 24 174 X 18 PPC405GP User s Manual stw...

Page 664: ...de buffer See TLB translation address See address translation trap 24 191 TSR 11 8 25 238 tw 24 190 fetching past 3 39 tweq 24 191 tweqi 24 194 twge 24 191 twgei 24 194 twgle 24 191 twgt 24 191 Prelim...

Page 665: ...timer interrupts causes 10 43 interrupts register settings 10 43 write strategies controlled by DCWR 4 7 used by DCU 4 7 write through W storage attribute controlled by DCWR 6 18 when controlled by TL...

Page 666: ...Preliminary...

Page 667: ...n this document was obtained in specific environments and is presented as illustration The results obtained in other operating environments may vary While the information contained herein is believed...

Page 668: ...International Machines Corporation in While the information contained is believed to All information contained IBM Microelectronics Division www ibm com Microelectronics Division GK1 0 3 11 8 03...

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