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IBM Personal System/2 50, Technical Reference

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Summary of Contents for Personal System/2 50

Page 1: ......

Page 2: ...time It is possible that this publication may contain reference to or information about IBM products machines and programs programming or services that are not announced in your country Such reference...

Page 3: ...ystem features and specifications Section 2 Programmable Option Select describes registers used for configuration Section 3 System Board describes the system specific hardware implementations Warning...

Page 4: ...Notes Iv...

Page 5: ...2 2 8 System Board POS Register 3 Hex 0103 2 9 Adapter Enable Setup Register Hex 0096 2 10 Section 3 System Board 3 1 Description 3 3 Micro Channel 3 3 Adapter Identification 3 3 Central Arbiter 3 3 M...

Page 6: ...Notes vi...

Page 7: ...te to Hex 0090 3 5 3 3 Arbitration Register Read Hex 0090 3 5 3 4 System Memory Map 3 8 3 5 System Board Memory Connector Type 1 3 9 3 6 System Board Memory Connector Type 2 3 10 3 7 Presence Detect E...

Page 8: ...Notes vIII...

Page 9: ...Section 1 System Overview Description 1 3 System Board Features 1 3 System Board Block Diagram 1 5 System Board I O Address Map 1 6 Specifications 1 7 Model 50 System Overview 1 1...

Page 10: ...Notes 1 2 Model 50 System Overview...

Page 11: ...eturns the model and submodel bytes and BIOS revision code The following figure shows these bytes and the system board types Model Submodel Revision Byte Byte Code System Board FC 04 00 Type 1 FC 04 0...

Page 12: ...put 256KB video memory Driven by System timer channel 2 The audio sum node signal Eight independent DMA channels Single or burst transfers and read verification 16 levels of system interrupts Interrup...

Page 13: ...ller Coprocessor Serial I optional t Port I I CMOS Memory Clock Controller l I DMA b Parallel I I Controller Port r Buffer I M I I iCC B Control Buffer c h u a 0 80288 f Data r n Microprocessor f Addr...

Page 14: ...em Control Port B Keyboard Auxiliary Device RT CMOS and NMI Mask DMA Page Registers 0 3 DMA Page Registers 4 7 Central Arbitration Control Point Card Selected Feedback Register System Control Port A S...

Page 15: ...a to System Board RAM DMA Controller 10 MHz 100 na Clock Number of Walta 1 o 1 Single Transfer 300 110 Access Memory Access Burst Transfers 300 110 Access Memory Access N System Board Memory Access De...

Page 16: ...Rate Typically performed every 15 1 jls Bua Master Accesa to System Board RAM DMA Controller 10 MHz 100 na Clock Number of Walta o 1 1 o Single Transfer 300 110 Access Memory Access Burst Transfers 3...

Page 17: ...Draw Low Range High Range Frequency Maximum Allowable Current Keyboard Port Auxiliary Device Port Electromagnetic Compatibility 360 mm 14 1 in 420 mm 16 5 in 140 mm 5 5 in 9 55 kg 21 Ib 1 8 m 6 ft 1 8...

Page 18: ...Notes 1 10 Model 50 System Overview...

Page 19: ...Address Map 2 5 Card Selected Feedback 2 6 System Board Setup 2 6 System Board Enable Setup Register Hex 0094 2 7 System Board P S Register 2 Hex 0102 2 8 System Board P S Register 3 Hex 0103 2 9 Adap...

Page 20: ...Notes 2 2 Model 50 POS...

Page 21: ...d not use the adapter identification 10 unless absolutely necessary Compatibility problems can result If an adapter and the system board are in setup mode at the same time bus contention will occur no...

Page 22: ...tem board functions Adapter Setup Bit 3 in the Adapter Enable Setup register hex 0096 must be set to 1 to allow adapter setup Bit 5 in the System Board Enable Setup register hex 0094 must be set to 1...

Page 23: ...POS Register 0 Adapter Identification Byte Low Byte 0101 POS Register 1 Adapter Identification Byte High Byte 0102 POS Register 2 0ption Select Data Byte 1 Bit 0 is Card Enable 0103 POS Register 3 0p...

Page 24: ...o subsystem system board 110 or an adapter is addressed and functioning Bit Function 7 1 Reserved o Card Selected Feedback Figure 2 2 Card Selected Feedback Register Hex 0091 Bits 7 1 Reserved Bit 0 T...

Page 25: ...When this bit is set to 1 the system board functions are enabled Bit 6 Reserved BI15 When this bit is set to 0 the video subsystem is placed in the setup mode and controlled through POS Register 2 hex...

Page 26: ...ured as an 8 bit parallel bidirectional interface When set to 1 this bit disables the bidirectional mode This bit is set to 0 at power on and POST sets it to 1 Bits 6 5 These bits select the configura...

Page 27: ...rface system board serial port and system board parallel port regardless of the state of bits 4 2 and 1 System Board POS Register 3 Hex 0103 With the system board in setup this register controls the s...

Page 28: ...are addressed as 0 through 3 respectively When bit 3 is set to 1 these bits select the connector that is put into setup Each channel connector has a unique card setup signal CD SETUP associated with i...

Page 29: ...r 3 9 Real Time Clock Complementary Metal Oxide Semiconductor RAM 3 12 RT CMOS Address Register and NMI Mask Hex 0070 3 13 RT CMOS Data Register Hex 0071 3 13 RT CMOS RAM I O Operations 3 14 Real Time...

Page 30: ...Notes 3 2 Model 50 System Board...

Page 31: ...Adapter Identification When the system is powered on an adapter can issue an 10 of hex 0000 for up to 1 second after channel reset to indicate it is not ready Any adapter that continues to issue an ad...

Page 32: ...n level 2 can be held inactive by devices on levels 0 and 1 by a refresh operation and by the previous controlling master The diskette drive controller should not be held inactive for more than 12 mic...

Page 33: ...te Figure 3 3 Arbitration Register Read Hex 0090 Bit 7 Setting this bit to 1 enables system microprocessor cycles during arbitration cycles This bit can be set to 0 if an arbitrating device requires t...

Page 34: ...out has occurred and resets bit 6 in this register to O Bit 4 This bit is reserved and should be O Bits 3 0 These bits are undefined for a write operation and should be set to O Reading these bits re...

Page 35: ...y checked and is assigned addresses at the top of the first and last 1MB of address space hex OEOOOO and FEOOOO Random Access Memory Subsystem The RAM subsystem on the system board starts at address h...

Page 36: ...256 byte portion of this RAM is reserved as a BIOS data area A 1KB portion of this RAM is reserved as an extended BIOS data area See the IBM Personal Systeml2 and Personal Computer BIOS Interface Tec...

Page 37: ...1 N A 5Vdc 2 I Column Address Strobe 3 1 0 Data Bit 1 4 I Address Bit 1 5 I Address Bit 2 6 1 0 Data Bit 2 7 I Address Bit 3 8 I Address Bit 4 9 N A Ground 10 1 0 Data Bit 3 11 I Address Bit 5 12 I Ad...

Page 38: ...110 Data 9 16 0 Address 4 52 110 Data 25 17 0 Address 5 53 110 Data 10 18 0 Address 6 54 110 Data 26 19 N A Reserved 55 110 Data 11 20 110 Data 4 56 110 Data 27 21 110 Data 20 57 110 Data 12 22 110 Da...

Page 39: ...onnected to ground G or not connected N The following table shows those combinations supported by Model 50 Type of Memory Presence Detect Slgnall Module Package 0 1 2 3 1 MB Memory at 120 ns G N N N 1...

Page 40: ...locked to prevent battery removal and loss of password and configuration information The following figure shows the RT CMOS RAM bytes and their addresses Addre Hex 000 000 OOE OOF 010 011 012 013 014...

Page 41: ...otherwise intermittent malfunctions and unreliable operation of the RT CMOS RAM can occur Bit 7 When this bit is set to 1 the NMI is masked off the NMI is disabled This bit is set to 1 by a power on r...

Page 42: ...operation following a write to hex 0070 should access hex 0071 otherwise intermittent malfunctions and unreliable operation of the RT CMOS RAM can occur The following steps are required to perform I...

Page 43: ...006 Day of Week 6 007 Date of Month 7 008 Month 8 009 Year 9 OOA Status Register A 10 008 Status Register 8 11 OOC Status Register C 12 000 Status Register 0 13 Figure 3 11 Real Time Clock Bytes Note...

Page 44: ...ction of a divider output frequency The system initializes the rate selection bits to a binary 0110 which selects a 1 024 kHz square wave output frequency and a 976 562 microsecond periodic interrupt...

Page 45: ...frequency as set by the rate selection bits in Status Register A The system initializes this bit to O Bit 2 This bit indicates if the time and date calendar updates use binary or binary coded decimal...

Page 46: ...1 this bit indicates that a periodic interrupt occurred Bit 5 When set to 1 this bit indicates that an alarm interrupt occurred Bit 4 When set to 1 this bit indicates that an update ended interrupt oc...

Page 47: ...e configuration information is incorrect Power on checks require that at least one diskette drive be installed bit 0 of the Equipment byte hex 014 is set to 1 Bit 4 When set to 1 this bit indicates th...

Page 48: ...power on diagnostic programs Diskette Drive Type Byte Hex 010 This byte indicates the type of diskette drive installed Bit Function 7 4 First Diskette Drive Type 3 0 Second Diskette Drive Type Figure...

Page 49: ...ve 48 tracks per inch 360KB High capacity diskette drive 720KB High density diskette drive 1 44MB Note All combinations that are not shown are reserved Figure 3 19 Diskette Drive Type Byte Bits 3 0 Fi...

Page 50: ...gure Bits Number of 76 Diskette Drives 00 One Drive 01 Two Drives 10 Reserved 1 1 Reserved Figure 3 21 Equipment Byte Bits 7 6 Bits 5 4 These bits indicate the operating mode of the display attached t...

Page 51: ...00 is equal to 2048KB The low byte is hex 17 the high byte is hex 18 Reserved Bytes Hex 019 through 031 These bytes are reserved Configuration CRC Bytes Hex 032 and 033 These bytes contain the cyclic...

Page 52: ...NMI Nonmaskable interrupt requests from system board parity and channel check are subject to mask control with the NMI mask bit in the RT CMOS Address register The Watchdog Timer and system channel ti...

Page 53: ...this port is read and this bit is set to 1 a parity check has occurred Bit 6 When this port is read and this bit is set to 1 a channel check has occurred Bit 5 When this port is read this bit indicat...

Page 54: ...ndicates the Watchdog Timer status When this bit is set to 1 a Watchdog time out has occurred For more information about the Watchdog Timer refer to the Hardware Interface Technical Reference Bit 3 Th...

Page 55: ...0 either by a system reset or a Write operation When a Write operation changes this bit from 0 to 1 the alternate reset pin is pulsed high for 100 to 125 nanoseconds The reset occurs after a minimum...

Page 56: ...curity space Power on password installation is a function of a program contained on the Reference diskette Once the power on password utility has been installed the password can be changed only during...

Page 57: ...these interfaces is maintained The functional interfaces for the Personal System 2 products are compatible with the following interfaces The Intel2 8259 interrupt controllers without edge triggering...

Page 58: ...Adapter the IBM Color Graphics Monitor Adapter and the IBM Enhanced Graphics Adapter The parallel printer ports Parallel 1 Parallel 2 and Parallel 3 in compatibility mode Generally compatible with the...

Page 59: ...tion control point 3 5 channel check latch 3 25 CMOS RAM 3 12 configuration CRC bytes 3 23 configuration RT CMOS 3 19 connectors memory 3 9 control port B 3 24 D date century byte 3 23 description pro...

Page 60: ...rvice 3 4 NMI signal 3 4 nonmaskable interrupt NMI 3 24 p parallel port 2 8 parity check enable 3 25 password power on 3 28 performance system 1 7 pointing device electrical 1 9 port B 3 24 POS See pr...

Page 61: ...6 status watchdog 3 26 switch to real mode 3 27 system address map 1 6 system board block diagram 1 5 features 1 4 I O address map 1 6 I O byte 2 8 memory 3 7 memory connectors 3 9 memory enable 2 9 m...

Page 62: ...Notes X 4 Index...

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