Appendix B. System address maps
47
DMA I/O address map
The following figure lists resource assignments for the DMA address map. Any
addresses that are not shown are reserved.
03E0 – 03E7
8
Available
03E8 – 03EF
8
COM3 or COM4
03F0 – 03F5
6
Diskette channel 1
03F6
1
Primary IDE channel command port
03F7 (Write)
1
Diskette channel 1 command
03F7, bit 7
1 bit
Diskette disk change channel
03F7, bits 6:0
7 bits
Primary IDE channel status port
03F8 – 03FF
8
COM1
0400 – 047F
128
Available
0480 – 048F
16
DMA channel high page registers
0490 – 0CF7
1912
Available
0CF8 – 0CFB
4
PCI configuration address register
0CFC – 0CFF
4
PCI configuration data register
LPTn + 400h
8
ECP port, LPTn base a hex 400
OCF9
1
Turbo and reset control register
0D00 – FFFF
62207
Available
Table 33. I/O address map
Address (hex)
Size (bytes)
Description
Table 34. DMA I/O address map
Address
(hex)
Description
Bits
Byte
pointer
0000
Channel 0, memory address register
00 – 15
Yes
0001
Channel 0, transfer count register
00 – 15
Yes
0002
Channel 1, memory address register
00 – 15
Yes
0003
Channel 1, transfer count register
00 – 15
Yes
0004
Channel 2, memory address register
00 – 15
Yes
0005
Channel 2, transfer count register
00 – 15
Yes
0006
Channel 3, memory address register
00 – 15
Yes
0007
Channel 3, transfer count register
00 – 15
Yes
0008
Channels 0–3, read status/write command register
00 – 07
0009
Channels 0–3, write request register
00 – 02
000A
Channels 0–3, write single mas register bits
00 – 02
000B
Channels 0–3, mode register (write)
00 – 07
000C
Channels 0–3, clear byte pointer (write)
A
000D
Channels 0–3, master clear (write)/temp (read)
00 – 07
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