IBM CPC700, User Manual

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12-2 Processor Local Bus (PLB)
12.2 PLB Arbiter Registers
PLB arbiter registers are accessed using the addresses in Table 102.
12.2.1 PLB Arbiter Control Register (PACR)
The PACR controls PLB arbitration priority, which is determined by PLB priority mode and PLB priority
order.
12.2.2 PLB Error Address Register (PEAR)
The read-only PEAR contains the address of the access on which a bus timeout error occurred.
The PEAR can be locked by the master. Once locked, the PEAR cannot be updated, if a subsequent
error occurs, until all PESR[FLCKn] fields are cleared (n is the master ID).
Table 102. PLB Arbiter Registers
Mnemonic Register Name Address Access
PACR PLB Arbiter Control Register 0xFF50_085C R/W
PEAR PLB Error Address Register 0xFF50_0858 R/O
PESR PLB Error Status Register 0xFF50_0850 R/Clear
Figure 65. PLB Arbiter Control Register (PACR)
0 PPM PLB Priority Mode
0 Fixed
1 Fair
1:2 PPO PLB Priority Order
00 Masters 0, 1
01 Masters 1, 0
10 Reserved
11 Reserved
3:31 Reserved
Figure 66. PLB Error Address Register (PEAR)
0:31 Address of bus timeout error
0 1 2 3 31
PPM
PPO
0 31