IBM CPC700, User Manual

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7-12 UART
in the transmit FIFO since the last THRE = 1. If bit 7 of the FCR is 1 (FIFOs enabled), the first transmitter
interrupt after changing this bit (bit 7 of the FCR) is immediate.
RCVR FIFO trigger level interrupts, received data available interrupts, and character timeouts all have
equivalent second interrupt priority. Current transmitter holding register empty interrupt and XMIT FIFO
empty have equivalent third interrupt priority.
7.3.2 Polled Mode
When bit 7 of the FCR = 1 (FIFOs enabled), and bits 4-7 of the IER are all set to 0 (interrupts disabled), the
UART is in FIFO polled mode of operation. The receiver and transmitter are controlled separately, so either
can be in polled mode of operation. In polled mode, the user program must check the LSR to see the
status of the receiver and/or transmitter.
Bits 3-6 of the LSR specifies which errors (if any) have occurred. Character status errors are handled in the
same way as in interrupt mode. Since bit 5 of the IER = 0, the IIR is not affected. Bit 7 of the LSR is set as
long as there is at least one character in the receiver FIFO. Bit 5 of the LSR indicates if the transmitter
FIFO is empty. Bit 1 of the LSR indicates if the transmitter FIFO and the transmitter shift register are empty.
Bit 0 of the LSR indicates if there are any errors in the receiver FIFO.
In FIFO polled mode, there are no character timeout or trigger levels; however, the FIFOs are still capable
of holding characters.
7.4 UART Reset and Sleep Mode
Both UARTs are reset upon a reset of the CPC700. They can also be reset individually by software via the
UART reset bits in the CPRRESET register. They can also be placed in sleep mode via the UART sleep
bits in the CPRPMCTRL register. See Chapter 6., “Clock, Power Management, and Reset” for more infor-
mation.