IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 7-7
7.2.1.3 FIFO Control Register
The FIFO control register has the same address as the IIR and is a write-only register. This register is used
perform FIFO control operations such as selecting the type of DMA signaling, setting the receiver FIFO
trigger levels, clearing the FIFOs, and enabling the FIFOs.
6 0 Overrun error (OE) indicator. Reset to 0 whenever processor reads LSR.
1 Overrun error (OE) indicator. Data in the RBR was read by the processor before the next character
was transferred into the RBR, hence the original data was lost. OE detected when this bit is 1. In
FIFO mode, if the incoming data continues to fill the FIFO beyond the trigger level, an OE occurs
only after the FIFO is completely full and the entire next character has been received in the receiver
shift register. The processor is informed of the OE immediately upon occurrence. The character in
the shift register will be overwritten and will not be transferred to the FIFO.
7 0 Receiver data ready (DR) indicator. Reset to 0 when all data has been read from the receiver FIFO
or the receiver buffer register.
1 Receiver data ready (DR) indicator. An entire incoming character has been received into the RBR or
receiver FIFO.
Table 74. FIFO Control Register Description
FCR Bits
Bit # Value Description
0 and1 Bit 0 = 0
Bit 1 = 0
Receiver FIFO level trigger level set to 1 byte.
Bit 0 = 0
Bit 1 = 1
Receiver FIFO level trigger level set to 4 bytes.
Bit 0 = 1
Bit 1 = 0
Receiver FIFO level trigger level set to 8 bytes.
Bit 0 = 1
Bit 1 = 1
Receiver FIFO level trigger level set to 14 bytes.
2 - Reserved
3 - Reserved
4 0 DMA mode select. If bit 7 of this register is 1 (FIFOs are enabled), this bit set to logic 0 will cause
RXRDY and TXRDY outputs to change from DMA mode 1 to DMA mode 0 (single transfer DMA).
1 DMA mode select. If bit 7 of this register is 1 (FIFOs are enabled), this bit set to logic 1 will cause
RXRDY and TXRDY outputs to change from DMA mode 0 to DMA mode 1 (multiple transfer DMA).
5 0 Transmitter FIFO reset. The 1 that is written into this position is self-clearing.
1 Transmitter FIFO reset. A logic 1 written here will clear all bytes in the transmitter FIFO and reset all
of its counter logic to 0. The transmitter shift register is not cleared by this bit.
Table 73. Line Status Register Description (Continued)
LSR Bits
Bit # Value Description