CPC700 User’s Manual—Preliminary
7-1
Chapter 7. UART
The CPC700 contains two universal asynchronous receiver/transmitters (UARTs) which provide two wire,
full duplex serial interfaces to support communications with serial peripheral devices. Each UART is com-
patible with the NS 16550 chip and includes a 16-byte send and a 16-byte receive FIFO.
Features of the UART include:
• Compatible with the NS 16550
• 16-byte send FIFO, 16-byte receive FIFO
• Full duplex operation
• Programmable baud rate generator
• Supports 5- to 8-bit word size, 1/2 stop bits, even/odd/no parity
• Two wire transmit/receive external interface
The UART performs serial-to-parallel conversion on data characters received from a peripheral device, and
parallel-to-serial conversion on data characters received from the processor. The processor can read the
complete status of the UART at any time during the functional operation. Status information reported
includes the type and condition of the transfer operations being performed by the UART, as well as any
error conditions, such as parity, overrun, framing and break interrupt.
This UART is functionally identical to NS16550 in character mode (on power up it will be in this mode), and
can be put into FIFO mode to relieve the processor of excessive software overhead. Here, internal FIFOs
are activated allowing 16 bytes (plus three bits per byte of error data in the RCVR FIFO) to be stored in
both receive and transmit modes.
The frequency of the UART serial clock is the CPC700’s SYS_CLOCK divided by 4. For example, if the
CPC700’s SYS_CLOCK is 33.33 MHz, then the UART serial clock is 8.33 MHz. A programmable baud rate
generator is included that is capable of dividing the UART serial clock by a divisor of 1 to (2
16
-1) and
producing the 16x clock required for driving the UART’s internal transmitter/receiver logic.
The UART has an interrupt system that can be programmed to the user’s requirements, helping to mini-
mize the computing required to handle the communications link. UART interrupts are capable of triggering
an interrupt request to the CPC700’s interrupt controller. If enabled properly in the interrupt controller, a
UART interrupt can be used to interrupt the processor. See Chapter 10., “Interrupt Controller” for addi-
tional information.
Note: The CPC700 UARTs do not provide modem control capability with its simple two-wire
implementation.
Summary of Contents for CPC700
Page 10: ...Table of Contents x Table of Contents...
Page 16: ...Tables xvi List of Tables...
Page 28: ...1 12 CPC700 User s Manual Preliminary...
Page 72: ...3 36 Processor Interface...
Page 132: ...4 60 Memory Controller...
Page 184: ...5 52 PCI Interface...
Page 194: ...6 10 Clock Power Management and Reset...
Page 224: ...8 18 IIC...
Page 244: ...10 10 Interrupt Controller...
Page 246: ...I 11 2 JTAG...
Page 250: ...12 4 Processor Local Bus PLB...
Page 262: ...14 10 Register Summary...
Page 267: ...CPC700 User s Manual Preliminary...