IBM CPC700, User Manual

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5-46 PCI Interface
3. Register 49h, bit 1 (Error Status Register, PCI_SERR# on Data Parity Error bit) which indicates
PCI_SERR# assertion on detected data parity error, is set if the mask at register 48h, bit 1 (Error Enable
Register, Data Parity SERR_ Enable) is set to 1. The PCI_SERR# on Data Parity Error bit can be cleared
by writing a 1 to it.
5.10.3.5 PCI Master Data Bus Parity Error Detection
This error is generated when a data bus parity error is detected on the PCI bus during a cycle which is
mastered by the CPC700’s PCI master. The CPC700’s PCI master will check parity on read cycles and
sample PCI_PERR# on write cycles. The bridge PCI master may assert PCI_PERR# if it detects a parity
error on a read as explained below. PCI uses even parity.
The mask for this error is register 04h, bit 6 (PCI Command Register, Parity Error Response bit). If an error
is detected, register 06h, bit 8 (PCI Status Register, Data Parity Error Detected bit) is set. The Data Parity
Error Detected bit can be reset by writing a 1 to it.
If register 48h, bit 2 (Error Enable Register, MErr Assertion Enable bit) is set and the error is detected as
explained above, the PLB slave will assert Sl[x]_MErr on the PLB bus in response to the error. For reads,
Sl[x]_MErr will be asserted for each data beat in which bad parity was detected. For all writes, Sl[x]_MErr
will be asserted for each data beat in which bad parity was detected, but asynchronously to the actual
transfer of write data on the PLB bus.
The following status bits are set:
1. Register 06h bit 15 (PCI Status Register, Parity Error Detected bit) is set if the bridge PCI master detects
bad parity on read data, regardless of the state of the Parity Error Response bit. The Parity Error Detected
bit can be cleared by writing a 1 to it.
2. If a data bus parity error is detected as an error, register 49h, bit 2 (Error Status Register, MErr Assertion
Event bit) is set to indicate an event which would cause Sl[x]_MErr to be asserted by the bridge PLB slave
regardless of the state of the MErr Assertion Enable bit. The MErr Assertion Event bit can be reset by writ-
ing a 1 to it.
3. The PLB Slave Error Address Registers (SEAR’s) and the PLB Slave Error Syndrome Register are
updated as follows: The address of the PCI transaction for which parity errors occurred is saved in one of
the SEAR registers (50h, 54h, 58h or 5Ch). SEARx is set if the MxAL field ((Master x Address Lock - x cor-
responding to the master id of the PLB master whose read or write was master aborted) is cleared, mean-
ing SEARx is unlocked. If the MxFL (Master x Field Lock) field is cleared, the MxET (Master x Error Type)
field of register 4Ch (SESR) is set to 001b to indicate Parity Error, and MxRWS (Master x Read/Write Sta-
tus) is set to 0 on a write, 1 on a read. No SEAR or SESR update is performed if either the parity Error
Response bit or the MErr Assertion Enable bit is not set.
5.10.3.6 PCI Address Bus Parity Error While PCI Target
This error occurs when a PCI address bus parity error is detected during the address phase of a cycle in
which the bridge is the PCI target. PCI uses even parity.
The mask for this error is register 04h, bit 6 (PCI command register, Parity Error Response bit). This error
does not have an explicit status bus, however the following actions are taken:
1. Register 06h, bit 14 (PCI Status Register, PCI_SERR# Asserted bit) is set to indicate assertion of
PCI_SERR# if the mask at register 04h bit 8 (PCI Command Register, SERR# Enable bit) is set to 1. This
status bit is cleared by writing a 1 to it.