IBM CPC700, User Manual

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5-44 PCI Interface
5.10.3 Error Descriptions
The following sections describe in detail how these errors are generated, what actions are taken for each,
and how to reset a given error.
5.10.3.1 PLB Unsupported Transfer Type
This error occurs when the CPC700’s PLB slave encounters an unsupported PLB transfer type. Table 60.
outlines transfers not supported by the interface’s PLB slave.
Upon detection of this error, the CPC700 will set the PLB Unsupported Transfer Type bit of the Error Status
Register (bit 0).
5.10.3.2 PCI Master Abort
This error is generated by the CPC700’s PCI master when no target responds with PCI_DEVSEL# within
the required time-out window and error detection is enabled. The CPC700’s PCI Interface PLB Slave may
assert Sl[x]_MErr on the PLB bus in response to this error as explained below.
There are two masks associated with this event. Actual error detection is masked by register 48h, bit 0
(Error Enable Register, Master Abort Error Enable bit). If the error is detected, Sl[x]_MErr will be asserted
if register 48h, bit 2 (Error Enable Register, MErr Assertion Enable bit) is set to 1. For reads, the PLB Slave
will still complete the transfer on the PLB bus, but will drive all 1’s on the read data bus as well as the
appropriate Sl[x]_MErr line for each data beat. For posted writes, Sl[x]_MErr will be asserted for one cycle,
asynchronously to the actual corresponding write data beat on the PLB. For connected writes, Sl[x]_MErr
will be asserted with the data transfer and the data will be discarded. If Master Abort Error Enable is
cleared, the error is masked and Sl[x]_Merr is not asserted, regardless of the setting of MErr Assertion
Enable.
The following status bits are set:
1. If a master abort is signalled, register 06h, bit 13 (PCI Status Register, Master-Abort bit) is set. Setting of
this bit is non-maskable. It and can be reset by writing a 1 to it.
2. If master abort is detected as an error, register 49h, bit 2 (Error Status Register, MErr Assertion Event
bit) is set to indicate an event which would cause Sl[x]_MErr to be asserted by the PLB slave, regardless of
the setting of the MErr Assertion Enable bit. The MErr Assertion Event bit can be reset by writing a 1 to it.
3. The PLB Slave Error Address Registers (SEAR’s) and the PLB Slave Error Syndrome Register are
updated as follows: The address of the aborted PCI request is saved in one of the SEAR registers (50h,
54h, 58h, or 5C). SEARx is set if the MxAL field (Master x Address Lock - x corresponding to the master ID
of the PLB master whose read or write was master aborted) is cleared, meaning SEARx is unlocked. If the
MxFL (Master x Field Lock) field is cleared, the MxET (Master x Error Type) field of register 4Ch (SESR) is
Table 60.PLB Unsupported Transfer Types
PLB_size(0:3) PLB Transaction PCI Address Space
1xxx Burst read/write any
0001, 0010, 0011 4, 8 & 16-word line read/write I/O, Configuration
0011 16-word line read/write Memory