IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 5-43
The reset value is 2, which is not appropriate for all configurations. In order to ensure PCI 2.1 compliance
for initial target latency, this register must be set as follows:
5.9.3.35 PCI Subsequent Target Latency Timer Duration
In synchronous mode, its value equals the maximum number of PCI clocks to disconnect. In asynchronous
mode, its value plus 3 equals the maximum number of PCI clocks to disconnect. The asynchronous value
must be 2 or less. The reset value is 1.
5.10 Error Handling
5.10.1 Introduction
The CPC700’s PCI Interface supports the detection and reporting of several types of errors. The errors are
reported to the PLB or the PCI and status information is saved in the configuration register set so that error
type determination can be done.
All errors are associated with either a cycle on the PLB bus or a cycle on the PCI bus.
Each error that can be detected has a mask associated with is. If the mask is set, then the detection of that
error condition is disabled. There are also masks for the PCI_SERR#, PCI_PERR# and PLB_MERR[0:15]
signals that prevent reporting of any error my means of that signal. These masks do not prevent the detec-
tion of the errors.
5.10.2 Error Types
•
PLB unsupported transfer type
•
PCI master abort generated (while PCI master)
•
PCI target abort received (while PCI master)
•
PCI target data bus parity error detection
•
PCI master data bus parity error detection
•
PCI target address parity error detection
•
PLB master PLB_MErr detection
Table 59.Register Settings
Configuration
Acceptable
Values
Resulting
MITL
Recommended
Value
Resulting
MITL
Primary Bridge, Sync 31 or less 31 31 31
Primary Bridge, Async 18 or less 32 18 32
Peripheral Bridge, Sync 16 or less 16 0 2
Peripheral Bridge, Async 2 or less 16 0 16