IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 4-41
4.7.4 Dynamic ECC Testing
It is possible to verify that the ECC logic is properly detecting and correcting errors. However, due to the
nature of the memory interface design it is required that only one master at a time access the memory con-
troller during this exercise. For instance, in most cases this test would be performed immediately after reset
and before the PCI is allowed to begin accessing memory. In this scenario, the one-master-at-a-time
requirement will be satisfied since only the CPU will be accessing memory.
Also, when the ECC logic is presented with more than 2 bit errors, the detection results are unpredictable.
For example, if a specific byte has errors on 3 or more bits, the ECC logic may report an uncorrectable
error (UE), correctable error (CE) or both or neither. In general if you perform a 4-beat read when multiple
uncorrectable errors exist, you can be assured of detecting at least a single uncorrectable error which will
generate a machine check interrupt (MCP) if that capability is enabled.
A simple test of ECC is as follows:
1. immediately following reset, the ECC logic is disabled by default
2. configure and enable the memory/ROM controller using DCR cycles
3. write to system memory
4. read from memory location just written to verify correct operation
5. enable ECC (see details in Section 4.9.4.1, “ECCCF - ECC Configuration Register”)
6. read from memory location written in step 3. The system should detect an uncorrectable ECC error
since the memory syndrome/check bits had unknown values before the ECC logic was enabled.
7. if desired, the ECC Error register can now be read and should reflect the error
8. reset the ECC Error register by writing all FFFF_FFFF’s.
4.8 Memory Data Flow
The following tables illustrate the dataflow between the local processor and memory, the local processor to
the PCI, and from the PCI bus to memory.
Table 36. Local Processor to Memory Controller Data Flow
CPU ADR/DATA Memory Controller DATA
Word Word Adr Byte Adr Bit Range Byte Enable Bit Range
DH0 A[29]=0 A[30:31]=00 0:7 0 0:7 (MSB)
DH1 A[29]=0 A[30:31]=01 8:15 1 8:15
DH2 A[29]=0 A[30:31]=10 16:23 2 16:23
DH3 A[29]=0 A[30:31]=11 24:31 3 24:31
DL0 A[29]=1 A[30:31]=00 32:39 4 32:39
DL1 A[29]=1 A[30:31]=01 40:47 5 40:47
DL2 A[29]=1 A[30:31]=10 48:55 6 48:55
DL3 A[29]=1 A[30:31]=11 56:63 7 56:63 (LSB)