IBM 7090 Instruction-Reference Download Page 65

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Summary of Contents for 7090

Page 1: ......

Page 2: ...IIrn Customer Engineering Instruction Reference 7090 Data Processing System System Fundamentals 7100 Central Processing Unit 7151 Console Control Unit 7606 Multiplexor...

Page 3: ...ense Indicator Register SI 28 7 1 02 Address Register 166 3 1 05 Index Registers XR 28 7 1 03 Program Register 166 3 1 06 Program Register PR 29 7 1 04 Sense Indicators 166 3 1 07 Shift Counter SC 29...

Page 4: ...orm 223 6895 and all earlier editions Tills edition has been revised throu9hout and should be reviewed completely Address comments concerning this manual to IBM Corporation CE Manuals Department 296 P...

Page 5: ...CORE STORAGE CARD MACHINES To Channels B D CENTRAL PROCESSING UNIT MULTIPLEXOR DATA CHANNEL A TAPE UNIT FIGURE 2 5 2 7090 SYSTEM COMPONENTS REGISTERS SWITCHING FUNCTIONS AND DATA PATHS...

Page 6: ...sible 1 1 00 GENERAL SYSTEM OPERATION A computer system may be made to add subtract multiply or divide According to its make up a system may also print read cards punch cards read or write mag netic t...

Page 7: ...n outside user Commonly used forms of output are information on magnetic tape punched cards printed reports or indicator lights 1 3 00 7090 SYSTEM MAKE UP The 7090 system includes all five of the sect...

Page 8: ...r IV s per Data Channel 7607 II 7100 CPU 2 7151 Console 721 Card Punch 7607 II 7606 Multi plexor 711 Card Reader 716 I I 7607 II 7302 Core Stor 7607 II 7607 II Print r I Power 400 208v 3 to All Frames...

Page 9: ...dels 1 and 2 control the flow of information between the 1 0 units and core storage A 7607 Modell can control any combination of ten 729 II and 729 IV tape units and up to one each of reader punch and...

Page 10: ...check panel 1 4 00 7090 GENERAL LOGIC The 7090 system operation can be compared to a 407 514 summary punch operation The card feed in the 407 is input storage arithmetic and control are in the 407 the...

Page 11: ...into storage In the beginning the author of the program decides what instructions and commands to use and in what order to use them There are several ways to get these instructions and commands in to...

Page 12: ...ractions 1 0 710 0 5468 0 101 100 1102 2 0 2510 0 28 0 012 3 0 3310 0 2518 0 010 101 0012 4 0 14510 0 1128 0 001 001 012 5 0 91510 0 7248 0 111 010 12 6 0 48 0 12 0 510 7 0 578 O 101 1112 0 73410 8 0...

Page 13: ...addresses one for each location Because all opera tions in the 7090 system are done in binary notation there are 15 binary positions used for addressing storage locations Only 15 are required because...

Page 14: ...12 16 257 2 Sections 16 384 Word Locations Per Section FIGURE 2 1 1 STORAGE LOCATIONS IS 11 51 FIGURE 2 2 1 DATA WORD FIGURE 2 2 2 INSTRUCTION WORD FIGURE 2 2 3 COMMAND WORD 13...

Page 15: ...ress that is different from the address field of the instruction 2 2 03 Data Channel Command Word Similar in format and application to the CPU instruction word the data channel com mand word gains its...

Page 16: ...Multiplexor 3 17 Storage FIGURE 2 3 1 FUNDAMENTAL SYSTEM COMPONENTS USED IN A B C PRINT C 15...

Page 17: ...ols in the data channel Because the lo cation counter is not needed in A B C print C it has been omitted from Figure 2 3 1 The channel address counter holds the storage address for the data word being...

Page 18: ...ic components of the entire sys tem Although the adders are not registers and have no capacity for holding numbers they play such a prominent part in almost every CPU operation that they cannot be con...

Page 19: ...e It then advances one to 00001 in preparation for calling in the next instruction when the first has completed its operation The function of the first instruction is to select the card reader on chan...

Page 20: ...0015 B 10 a a11 0 0 a oio a 1 0 0 0 0 a 010 a 010 a 0 0 a 0 0 0 oio a 1 0 a 1I 00005 Store the Contents of the AC at Location 00011 C 10 0 a11 oio a oio a 010 a 010 a 0 0 a 1 0 1 1 1 0 0 01 00006 Writ...

Page 21: ...toring factors A and B This time the CPU does not send for 00002 again but allows the PC to retain 00003 and sends this to AR and MAR Now the word at 00003 comes to SR and PRo Decoding PR causes the a...

Page 22: ...d to 00010 so when channel A has received its com mand the CPU receives the contents of 00010 as an instruction Decoding a PR of zeros causes the CPU to stop The operation code of zeros is called halt...

Page 23: ...7090 system study the operation of the individual current switching component circuits that make up the system These are explained in Transistor Components Circuits IBM Customer Engineering Manual of...

Page 24: ...points of Figure 3 1 2A With the input line active the signal at test point 2 becomes active Test point 2 conditions the TO with its output test point 3 conditioning one leg of the TA The set pulse co...

Page 25: ...18 19 20 35 I I I J I I SC12 17 AD3 8 18 Pos u 1 I 1S 11 Prog Reg 1 Shift Ctr I Q pi 13 11 112 171 Adder t 3 17l 9 10 17 XR A B C 1 I t I 1 n 3 Prog Ctr 171 13 Adr Sw 171 u u I I a E 0 U 130 35 11 5 I...

Page 26: ...O 5 I i I 4 I lit i I i I I i 5 I I LL _____ t 1 I i 6 I I II I I I I I I Set Each Divi sion Equal s 20 Nanoseconds A Hold Output FIGURE 3 1 2 SHIFT CELL Reset Count Count Count Caunt 0 1 2 3 X On 0 O...

Page 27: ...all zeros Speed Up Counting In a counter position for a large number normal circuitry where one position feeds the next higher position can cause a considerable delay An example of this delay is shown...

Page 28: ...ep o 0 1 0 0 01 o FIGURE 3 1 6 NORMAL COUNTER RIPPLE DELAY PC 6 7 and a 1 PC9 10 11 Equals 1 PC12 13 14 Equals 1 PC1S 16 17 Equals A r A A A Step PCS Step pca Step PCll Step PC14 Step PC17 FIGURE 3 l...

Page 29: ...In several floating point operations the MQ holds the least significant 35 bits of the result 3 1 04 Sense Indicator Register SI Systems 2 06 00 1 2 06 35 1 The sense indicator register is a 36 positi...

Page 30: ...s 16 and 17 have a bit Position 15 has both triggers preset by AS 15 to SC 15 Because the SC is not being stepped at this time trigger B of position 15 will latch on The SC is divided into groups of t...

Page 31: ...counter The high order position PC2 is used to signal that all addresses in core have been set to zero on the clear operation only The remaining positions 3 through 17 indicate the location of the nex...

Page 32: ...68uu 2D Position 17 Output CAP 6Suu 2H FIGURE 3 I SB SHIFT COUNTER POSITIONS 16 AND 17 Step Pulse Trigger A PCI7 Trigger 8 PCI7 Trigger A PCI6 Trigger B PCI6 Trigger A PCI5 0 Trigger B PCI5 Value Tgr...

Page 33: ...a word is brought out of core storage The address goes from the address register to the address selec tion components in core storage 3 1 10 Address Switches AS Systems 3 06 06 1 3 06 10 1 The address...

Page 34: ...ad circuits LAC The logic of the operation of the look ahead circuits is shown in Figure 3 1 10 and Figure 3 1 11 Notice that for look ahead purposes the adders are grouped into five groups of five ad...

Page 35: ...3111 25V iY QV 30V 33A 22A 17A 12A 32V 21V 11V A 16V 10V A 31V 20V ISV 9V 30V Co 14 9 2 02 42 1 34V 19V 14V 8V 3V Co 3 Q 29V 23V 13V 7V 2V 2 02 40 1 12V 22V A 6V A I V A A IIV A A 21V 16V 10V SV PV 26...

Page 36: ...Q 14 9 LA Co 35 30 S 4 LA 29 25 LA 24 20 LA A 19 15 LA 24 20 LA A 14 9 LA 19 15 LA 14 9 LA Co 29 25 S 4 LA 24 20 LA 19 15 LA A Co 29 25 14 9 LA 24 20 LA 19 15 LA Co 24 20 A eN 19 15 LA 14 9 LA C l S...

Page 37: ...milar instructions have the same primary operation code Direct outputs of the program register or storage register are sent to individual machine circuits to cause the machine to operate according to...

Page 38: ...s are used to execute an instruction when information from core storage is not needed Most instructions use only one E or L cycle for their execution but some instruc tions require multiple E or L cyc...

Page 39: ...ding gates house the multiplexor circuitry Data flow from core storage to the multiplexor storage bus then to either the CPU or anyone of the data channels See Figure 4 0 1 The address field 21 35 of...

Page 40: ...5 3 17 3 17 I r Multiplexor Multiplexor Multiplexor Storage Bus Storage Bus Address Switches OR ing S 1 20 I 21 35 S 1 35 3 17 r It CPU Channel Memory Data Memory Channel Location Storage Bus Input Sw...

Page 41: ..._ 3 Clock Trigger 4 Clock Trigger U W I W r r i0 ______ n ________ n ____ I 5 Clock Trigger A5D Clock Pulse w w i w ____ Ir1 r1 I rL 6 Clock Trigger U U I U A6D Clock Pulse 7 Clock Trigger A7D Clock P...

Page 42: ...nd data channels Because of inherent delays in logic blocks clock pulses distributed to the CPU arrive about one clock pulse late For this reason those clock pulses distributed from the multiplexor to...

Page 43: ...el Channel Location Input Switches Input Switches Counter Sw s 1 A D 35 S l E H 35 3 E H 17 60 26 01 1 60 26 01 1 60 10 13 1 Channel Location Counter Switches A D 3 17 60 10 13 1 FIGURE 4 1 2 FLOW FRO...

Page 44: ...s The switches have three outputs all of which are active simultan eously Two of the outputs feed both banks of the data channels and terminate at the location counter switches The third output feeds...

Page 45: ...also feeds the multiplexor address switches These positions are gated through the switches only during a look ahead address control operation I Cycle Flow At 16 D3 data on the multiplexor storage bus...

Page 46: ...ne cycle therefore the end operation trigger is turned on during I time This forces go to I time on Systems 8 00 12 1 Go to I time will turn on the master I time trigger and will prevent turning on of...

Page 47: ...17 01 Reset Tag Reg 17 01 2 12 S0 1 2 11 40 01 2 08 01 1 SB S 3 11 PR S I 9 17 S02 2 1 40 1 PR 1 S POD 3 01 00 Address Modification f SB S 1 2 PR S 8 9 17 02 2 11 40 1 f PR 6 9 SOD 3 07 00 SR 18 3S AO...

Page 48: ...nged Execution of this instruction is identical to that of store except for the routing of AC P to the storage register sign position AC P 35 is gated to SR S 35 on Systems 2 12 02 1 Store MQ STQ 0600...

Page 49: ...R III D1 3 06 18 1 AD 3 17 AS E9 D3 Turn off IA Tgr Ell Dl 2 10 65 1 I Time of IA Type Instruc tion Prevent Most of E Time Outputs 2 15 13 1 SB _SR E7D1 2 12 50 1 No Next Cycle Determined by Instructi...

Page 50: ...Ctr 2 09 00 1 Ye 0 STO srQ I l AC S 1 35 MQ S 35 SR SR E1 D1 E1 D1 2 12 01 1 2 12 07 1 t I SR SB E4 D3 2 09 00 1 J 1 1 SB Memory Data Reg End Op MF Store Prefix 2 09 01 1 FIGURE 5 3 1 STO 0601i STQ 0...

Page 51: ...on the SB Store Instruction Location Counter STL 0625 1 E Figure 5 3 4 The contents of the program counter which contains the location of the STL instruc tion plus one replace the contents of position...

Page 52: ...09 01 1 MF Store Tag 2 09 01 1 MF Store Decrement 2 09 01 1 2 09 00 1 AC P 35 SR E1 D1 SR SB E4 D3 2 09 00 1 MF Store Prefix FIGURE 5 3 2 STP 0630 STD 0622 STT 0625 STA 0621 FIGURE 5 3 3 SLQ 0620 FIG...

Page 53: ...1 J SR 5 35 SR 5 35 MQ 13 Dl MQ 13 Dl 7 17 4D 1 2 12 40 1 FIGURE 5 3 5 LDQ 0560 FIGURE 5 3 6 XCA 0131 1 I Time Pri Op 12 MQ SR 11O Dl 2 12 07 1 End Op I Time Next Inst SR S 35 AD P 35 10 D6 AD Q 35 A...

Page 54: ...seven or less at any L10 time of a shift instruction This means that up to five shifts may be made in the 1 time of the following instruction Shifting to the left is the same as multiplying by a powe...

Page 55: ...2 11 78 1 L Time LEnd Op Al0 Dl 8 00 01 1 Yes t L_ _ __1 LLS Inst Shift Gate Ll 1 2 09 70 V to SC 0 2 11 79 1 Set MQ S AC S o 2 12 42 1 ACl 1 MQ 1 AC 35 r _ _Y_es 2 12 42 1 r 2 LGL Turn On AC Ov Tgr...

Page 56: ...contents of the MQ including the sign left the number of places designated by the address Bits shifted out of MQ l enter the sign position and from the sign position enter MQ 35 5 3 03 Fixed Point Ar...

Page 57: ...AC RT Step SC Each Clock Pulse FIGURE 5 3 11 ARS 0771 Step SC Each Clock Pulse 2 11 79 1 Shift Gate LIto SC 0 2 11 79 1 Set and Shift AC Q 34 and MQ I 34 RT 2 12 33 1 2 12 43 1 Yes LRS AC S MQ S AC 35...

Page 58: ...6 Sec Op 13 AS 10 17 SC 111 01 Yes FIGURE 5 3 13 RQL 0773 SR 1 35 AO 10 03 2 12 14 1 SR S AC S 12 01 2 12 37 1 Change SR 5 E9 01 2 09 95 1 AO Q 35 AC 12 01 2 12 31 1 2 12 15 1 Set AC 5 Plus 16 01 2 12...

Page 59: ...ycle of the next instruction The contents of the AC or the l s complement of the AC and the contents of the SR are added in the adders Whether to use true AC or complemented AC is determined by the co...

Page 60: ...OV Tgr 2 10 36 1 SUB SBM Set SR S Minus E9 Dl 2 09 95 1 2 12 24 1 2 12 22 1 Set SR S Plus E9 Dl 2 09 95 1 2 12 22 1 2 12 24 1 Carry AD 35 14 03 2 12 29 1 FIGURE 5 3 15 ADD 0400j ADM 0401j SUB 0402j S...

Page 61: ...e word indicated by the address is considered negative This negative word is added algebraically to the contents of the AC The execution of SBM is the same as ADD except that the sign of the SR word i...

Page 62: ...15 18 1 End Op in I E Control 2 09 46 1 I f I Time Next Instruction MQ SR Signs Unlike 2 12 94 1 Set MQ AC Signs Minus Ell Dl 2 12 92 1 SR AD All L Time 2 12 14 1 AC AD L Time 2 12 24 1 AD AC L2 D1 L...

Page 63: ...R the AC is cleared and the sign is set This allows the MPY to start with the AC containing zeros Also during the E cycle the word coming from storage is tested to see if all positions contain a zero...

Page 64: ...the MQ and the remainder of the dividend is left in the AC The sign of the MQ is set to the algebraic sign of the quotient as determined by the SR and AC signs The sign of the remainder remains the sa...

Page 65: ...as MPY Except that the Above is also Done During the I Cycle after MPY FIGURE 5 3 18 MPR 0200 E Time SR S l 35 AD P 35 EO D3 2 12 15 1 1 AD 3 17 AS E2 D1 AS 12 17 SC E2 Dl 3 06 16 1 Prevent 438 SC E3...

Page 66: ...1 I AD 3 17 AS E2 DI 3 06 16 1 No AS 12 17 SC E2 Dl 2 11 78 1 I E End Op To End Op Figure 3 5 20B I S_R_ _A_C_ ____ N_O_ Ye ISR AC t I 0 Carry I and To Diy Check Fig 3 5 20B A Comp MOl AC 35 2 12 42 1...

Page 67: ...l 2 09 51 1 Comp MQ1 AC 35 2 12 42 1 A L Time 1 1 Divide Ck EndOpEl1 2 09 50 1 J End Op Sh AC P 35 and MQ 2 35 Lt 2 12 34 1 2 12 42 1 Turn On T1 Ell 2 10 53 1 Div Step SC L3 Dl L7 Dl L11 Dl 2 09 51 1...

Page 68: ...d L cycles A Q carry as the result of the E cycle test allows normal divide operation to take place Toward the end of the E cycle the AC and MQ are shifted left the SC is stepped and the MQ sign is se...

Page 69: ...plemented Positions containing ones are changed to zeros and positions containing zeros are changed to ones This instruction is executed by complementing the AC to the AD and replacing the contents of...

Page 70: ...FIGURE 5 3 21 RND 0760 0010 Turn on Ace OV Tgr 2 10 36 1 ClM 2 12 22 1 FIGURE 5 3 22 ClM 0760 0000 COM 0760 0006...

Page 71: ...ms A floating point number is said to be in normal form when the digit immediately to the right of the point is a significant bit 1 If the number is a zero it is said to be in unnormal form The except...

Page 72: ...cycles Execution of the instruction is accomplished during the L cycles To differentiate between the different types of L cycles there is a tally counter This is a five stage counter whose output is a...

Page 73: ...Tgr 2 13 27 1 2 13 22 1 2 13 21 1 2 13 95 1 2 10 3S 1 t Yes C AC C SR Ca r _ _ _ _ _ _ _ N o C A C __ C SR Interchange AC and SR t SR S _ AC S AC S SR S AC l 35 SR AD Q 35 AC A6 D1 A6 D1 A6 D1 A6 Dl...

Page 74: ...me 2 13 42 1 OBJECTIVES Step SC Every Clock Time 2 13 71 1 1 Test for Possible Double Precision Handling 2 Add Signs Alike or Signs Unlike 2 12 47 1 Yes Turn Off T2 Tgr A2 Dl 2 10 31 1 SR I 35 AD AO D...

Page 75: ...s Position Change the Sign of Acc SR was than Acc 2 No 9 Carry Re complernent and Leave the Sign SR was than Acc No AC 35 Sk 3S Off Turn on FP Tgr A6 01 Turn on Col 9 Corry Tgr 2 10 37 1 On MQ 0 SR AD...

Page 76: ...3 31 1 MQ Now Complemented 1 in SR Set Sr to MQ to Complete Double Precision SR 1 35 _ MQ A8 DI 2 13 41 1 Turn off FP Tgr Al0 D 2 10 29 1 I From Addition signs unlike OBJECTIVES 1 Zero Test Acc Frac D...

Page 77: ...nt of Number of Shifts Required to Normalize AC Underflow is Possible 2 10 29 1 2 13 24 1 2 13 27 1 AD Q 8 AC Al1 D1 2 13 31 1 FP End Op 2 10 35 1 I Time OBJECTIVES Next Instruction 1 Compute MQ Char...

Page 78: ...S because this is easier to do in the computer The AC is cleared rather than let shifting take place because machine time is saved Second Step L Time Second step L time is used to shift the AC and MQ...

Page 79: ...vailable circuits must be used to get the complement to the MQ Therefore the AC is gated to the SR and the SR is gated to the MQ Fifth Step L Time Fifth step L time is used for normalizing the result...

Page 80: ...ude of the floating point number stored at the location indicated by the address from the floating point number in the accumulator Execution of this instruction is the same as FAD except that the sign...

Page 81: ...35 SR EO D3 2 12 07 1 MQ 0 Turn On FP Tgr E2 Dl 2 12 07 1 Turn On FP Tgr 2 10 29 1 OBJECTIVES 1 Multiplicand to SR 2 Zero Test Mul tipJ ier Fraction and Multiplicand for a Normal Zero 3 33B to Shift C...

Page 82: ...d Char AD l S SR M Dl Zeros to SR l S 2 13 04 1 MQ 1 S SR A6 Dl 2 13 12 1 AC Q S AD A8 D3 SR l S _ MQ A6 D1 2 13 41 1 SR 1 S _ AD AS D3 Multiplier Char to SR Zeros to MQ l S Addition of Multiplicand a...

Page 83: ...y 2 10 24 1 Yes SC 0 No MQ 35 Yes P d 1 o_n__ t __ Off 1 AC 9 A3 DI A7 Dl All Dl 2 10 27 1 Step SC Every Clock Time 2 09 54 1 Sh AC and MQ Rt A3 Dl A7 Dl AIl Dl 2 09 54 1 FIGURE 5 3 24C UFM 0260 FMP 0...

Page 84: ...g 2 s Complement of 1 t MQ 9 _AC 35 A10 01 2 13 42 1 I Eod Op I I Time 1 Next Inst OBJECTIVES 1 Set MQ Char if AC Frac t 0 2 Set Signs of AC and MQ 1 l_AD 35 AC O S AD 10 D3 10 D3 2 5 Comp 33S AD 10 D...

Page 85: ...checking circuits on Systems 2 12 47 1 The FP trigger is used to remember the MQ zero condition and to cause end operation at the end of the E cycle First step L time is used to get the initial chara...

Page 86: ...g point number stored at location X The result is a floating point quotient in the MQ and the floating point remainder of the dividend in the AC The sign of the MQ is the algebraic sign of the quotien...

Page 87: ...Dl 2 10 27 1 I Time Pri Op 76 L Time MQ 9 1 Yes FP Rnd Gate LO D6 2 10 27 1 No No One AD 35 LO D6 2 13 27 1 019 Carry Yes CarryAD 9 AD 8 2 10 46 1 Sh AC 9 34 Rt L8 Dl 2 12 33 1 End Op FIGURE 5 3 25 F...

Page 88: ...End Op if AC Frae Equal s Zero 4 Char Oiff to AC if FP Tgr is on I yeS dder 9 Carry No Turn o No AC SR Sol 9 Carry 2 10 37 1 Turn On T2 Tgr A3 01 2 10 38 1 Turn on ivide Chk Tgr A3 01 and Tl Tgr 2 10...

Page 89: ...31 1 Reset AC To I Time Fig 5 3 26D Turn Off FP Tgr A2 D1 2 10 29 1 AC Q 35 AD A4 D3 2 13 24 1 AD Q 35 AC A2 Dl 2 13 31 1 Carry AD S M OO 2 13 27 1 Char Increased by One Quotient Overflow is Possible...

Page 90: ...pts 26 Shifts 2 Compute Quotient Char 3 Re compute Original Dividend Char and Set to AC Q S 4 End Op Go to I Time AC Q 35 AD 3rd Step L 2 13 24 1 No 6 AD 9 35 AC A2 Dl A6 Dl Al0 Dl 2 13 31 1 I MQ 35 A...

Page 91: ...S 1 Set Char of Remainder to Original Dividend Char 2710 if T2 is off No Divide Check and AC Frac 1 0 Stop If Divide Check Occurred A_ 2 K O_ff______ Restore Remainder to True Number t Comp AC 9 35 AD...

Page 92: ...ction 3 Step the shift counter down to 2610 the desired number of shifts to move a bit from MQ 35 to MQ 9 Third step L time is used to do the actual division The objectives of third step L time are to...

Page 93: ...same as TQP except that the AC sign rather than the MQ sign is tested See Systems 2 10 08 1 Transfer on Overflow TOV 0140 I If the AC overflow trigger is on as a result of a previous operation a tran...

Page 94: ...Cndtl AO AS 19 03 2 10 09 1 SR 18 35 AO P 17 19 03 FIGURE 5 3 27 TRA 0020 SR 18 35 AO P 17 19 03 2 12 16 1 Any Trans or Store and Trap One Cycle Trans Cond Met FIGURE 5 3 28 Tap 0162 Block Normal AO...

Page 95: ...are left unchanged The operation is performed by adding the contents of the MQ to the complemented accumulator contents The Q carry trigger is then matched with the re gister signs to determine whethe...

Page 96: ...S 2 10 09 1 L Time MQ S 35 SR L2 01 2 12 07 1 SR AO L5 06 2 12 14 1 l AS AR 111 01 3 06 18 1 AC S Plus Yes No Carry AO 35 2 09 30 1 I _ 1 No Transfer on Equals __________ ____________ J FIGURE 5 3 30...

Page 97: ...Any Trans or Store and Trap 2 11 55 1 FIGURE 5 3 31 TCO 0060 0061 0062 Etc TeN 0060 0061 0062 Etc Any Trans or Store and Trap FIGURE 5 3 32 TRC 0022 0022 0024 Etc TEF 0030 0030 0031 Etc...

Page 98: ...an instruction transfer or trap is taken to location 0001 One instruction trap transfer is immune to trapping mode The locating of successful transfers and the trap to a common check point make trapp...

Page 99: ...00 J ITrans Ctrl I 2 11 55 1 IAd e PC I 19 D1 2 11 51 1 1 Prevent AD AS AR 3 17 AS 111 Dl 19 D3 3 06 18 1 2 10 09 1 E Time 1 I MF Store PC AS Orl EO D3 2 09 00 1 3 05 09 1 f AS SR 21 35 E2 Dl 3 06 12...

Page 100: ...cumulator P position causes the computer to skip one instruction If there is no bit in P the computer takes the next instruction in sequence Low Order Bit Test LBT 0760 0001 I L Figure 5 3 35 A bit in...

Page 101: ...o o I Time Pri Op 76 No No On Turn Off Div Ck Tgr LlO Dl 2 10 53 1 Off FIGURE 5 3 35 PBT 0760 0001 LBT 0760 0001 DCT 0760 0012 I Time Pri Op 52 SB SR E7 Dl 2 12 50 1 FIGURE 5 3 36 ZET 0520 NZT 05 O...

Page 102: ...SR S 35 AD P 35 L Time SB SR E7 Dl 2 12 50 1 SR 1 35 AD Comp AC Q 35 L Time AD L Time Turn On Q Carry Trigger 2 10 36 1 No FIGURE 5 3 37 CAS 0340i LAS 0340 CAS On CAS On...

Page 103: ...gical word S 1 35 stored at location X The sign of the AC is disregarded the contents of the AC and storage are unchanged If the contents of the AC are greater than the contents of storage location X...

Page 104: ...09 60 1 FIGURE 5 3 38 PSE 0760 0140 I Time Pri Op 76 SR 18 35 AO P 17 19 03 2 12 16 1 Sense Op Pnl Class Adr A14 UA 1 2 3 or 4 Turn On Sense Light 1 2 3 or 4 2 09 60 1 FIGURE 5 3 39 PSE 0760 0141 014...

Page 105: ...e Figure 5 3 42 The computer causes an impulse to appear at the specified exit hub of the control panel of the printer attached to Data Channel A B C D E F G or H respectively Figure 5 3 43 MSE 0760 X...

Page 106: ...Channel 6 00 05 1 6 00 07 1 SR 18 35 AD P 17 19 D3 FIGURE 5 3 41 PSE 0760 1341 2342 3341 ETC Sense Skip L9 Dl FIGURE 5 3 42 PSE 0760 1360 2360 ETC 6 00 05 1 6 00 07 1 FIGURE 5 3 43 PSE 0760 1361 1372...

Page 107: ...1 SR 18 35 AD P 17 19 D3 2 12 16 1 Sense Skip L9 Dl FIGURE 5 3 44 MSE 0760 0141 0142 0143 0144 106 Turn Off I O Ck Tgr Lll D1 2 10 53 1 SR 18 35 AD P 17 19 D3 To Sense Skip DOT Or 2 09 58 1 Sense Skip...

Page 108: ...tart button causes the computer to proceed in L time of a transfer operation and the computer takes an instruction trans fer to location X When halted the PC contains the address of the HTR instructio...

Page 109: ...32 03 1 Turn Off BOT Ind 12 02 60 32 02 1 FIGURE 5 3 46 BTT 0760 ETT 0760 Turn Off EaT Ind 12 02 60 32 02 1 Turn On Mst Stop Tgr 110 01 4 20 11 1 Turh On Start Tgr AO A8 Turn Off Mst L Time Tgr All 0...

Page 110: ...Turn on Mst Stp Tgr 110 D1 4 20 11 1 Turn On Start Tgr AO AS 4 20 07 1 Cond Met Up from I Time 2 10 07 1 FIGURE 5 3 4S HTR 0000 109...

Page 111: ...1 2 11 P re PC vent AS 03 5 09 1 19 3 0 3 06 16 1 3 06 18 1 t t t End Op 8 00 02 1 Prevent AR pC 13 01 3 06 05 1 FIGURE 5 3 49 XEC 0522 I Time Pri Op 76 L Time End Op I Time Next Inst 2 12 92 1 FIGURE...

Page 112: ...5 1 Section 3 5 01 except that SI 0 35 is taken to the SR rather than AC S 1 35 SI 0 35 to the SR S 1 35 is shown on Systems 2 12 13 1 OR Storage to Indicators OSI 0442 I E Figure 5 3 52 This instruct...

Page 113: ...115 051 Electronic Reset of 51 EO D3 FIGURE 5 3 52 LDI 0441 051 0442 115 0440 FIGURE 5 3 53 RIS 0445 112...

Page 114: ...2 12 14 1 RIR RIL AO P 35 SR S 35 12 01 2 12 04 1 2 12 16 1 FIGURE 5 3 54 SIR OQ55 SIL 0055 RIR 0057 RIL 0057 fiR 0051 ilL 0051 113...

Page 115: ...truction is used as a reset mask for the left half of the indicator register A one in the control field resets the correspond ing indicator position Execution of this instruction is similar to that of...

Page 116: ...SR S 35 AO P 35 14 03 2 12 15 1 Electronic Reset of SI 12 01 2 12 64 1 FIGURE 5 3 55 PAl 0044 PIA 0046 OAI 0043 RIA 0042 IIA 0041 115...

Page 117: ...ple down the adder and carry out of the AD P The adder P carry is used to condition the transfer Transfer if Indicators Off TIF 0046 1 L Figure 5 3 56 If all of the ones in the AC are matched by zeros...

Page 118: ...Any Trans or Store and Trap Comp AC 0 35 AD LO D3 AD P 35 SR 5 35 L2 D1 2 12 04 1 FIGURE 5 3 56 TlO 0042 TIF 0046 117...

Page 119: ...SR S 35 AD P 35 LO D3 2 12 15 1 SR S 35 AD P 35 L8 D3 2 12 15 1 FIGURE 5 3 57 aNT 0446 OFT 0444...

Page 120: ...hed the computer takes the next instruction in sequence Execution of this instruction is the same as ONT except that the SR 18 35 is compared against SI 0 17 Right Half Indicators Off Test RFT 0054 I...

Page 121: ...SR lS 35 AD lS 35 LO D3 SR S 35 AD P 35 LS D3 2 12 15 1 SR lS 35 AD P 17 LO D3 AC Q 35 SR Q S 35 L1O Dl FIGURE 5 3 5S RNT 0056 LNT 0056 RFT 0054 LFT 0054...

Page 122: ...on is made and the computer takes the next instruction in sequence The comparison between the index register contents and the decrement is made by gating the decrement and the 2 s complement of the in...

Page 123: ...XR AD L Time SR S 35 AD P 35 L4 D3 FIGURE 5 3 59 TXI 1000 SR 18 35 AD P 17 19 D3 2 12 16 1 AD 3 17 XR L5 Dl L10 D1 2 12 70 1 Inst TNX TXL TIX TXH Yes XR S Deer TNX TXL T1X TXH FIGURE 5 3 60 TIX 2000...

Page 124: ...e specified index register in true form To shift the address field to the decrement positions of the adders AC 21 35 is routed through the SR to AD P 17 Place Decrement in Index PDX 0734 1 Figure 5 3...

Page 125: ...2 12 16 1 FIGURE 5 3 61 TSX 0074 FIGURE 5 3 62 PAX 0734 PDX 0734 PAC 0737 PDC 0737...

Page 126: ...nt SR 18 35 AO P 17 19 03 2 12 16 1 Note Tag 0 Block XR Adders 10 03 Put Zeros in SR 1 20 by Operating Set and Hold Lines Zero Already in SR S L I AS Goes to SR 21 35 FIGURE 5 3 63 PXA 0754 PXO 0754 1...

Page 127: ...dex Complemented AXC 0774 I Figure 5 3 65 This instruction loads the specified index register with the 2 s complement of the address portion 21 35 of the instruction Execution ofAXC is similar to that...

Page 128: ...2 12 70 1 FIGURE 5 3 65 AXT 0774 AXC 0774 2 12 16 1 2 12 15 1 AD 3 17 XR El1 Dl XR AD 10 D3 Carry AD 17 10 D3 FIGURE 5 3 66 LXA 0534 LXD 0534 LAC 0535 LDC 0535...

Page 129: ...into the SR at the same time Sand Q remain unchanged AND to Accumulator ANA 0320 I E L Figure 5 3 69 This instruction places the logical AND of the word stored at location X and the AC P 1 35 in the a...

Page 130: ...FIGURE 5 3 67 OR5 0602 58 5R E7 Dl AC Q P 35 5R Q 5 35 E7 D1 2 12 01 1 2 12 15 1 FIGURE 5 3 68 ORA 0501 129...

Page 131: ...r ANS T AC lY 5T SR 5 35 L7 D1 SR S 35 SR Form Comp of S 35 L7 D1 And in SR 2 12 02 1 2 12 11 1 SR S 35 AD P 35 L8 D3 t 2 12 15 1 Exchange SR ACC t r AD Q 35 AC Comp of AND L1O D1 AC P 35 SR S 35 L1O...

Page 132: ...raction 2 12 22 1 AD P 35 AC L2 Dl 2 12 30 1 SR S 35 AD P 35 L4 D3 2 12 15 1 OR in SR p of Sum AC P 35 SR AD P 35 AC OR in AC R S 35 L6 Dl L6 Dl 2 12 02 1 2 12 30 i 1 SR S 35 AD P 35 14 D3 Sh AC P 35...

Page 133: ...ituting the equation 2 in equation 1 3 EXCLUSIVE OR A B 2 A B 2 A or B 01000 00010 00110 And Simplifying equation 3 4 EXCLUSIVE OR 2 A or B A B 01110 01000 00110 5 3 12 Convert Instructions The three...

Page 134: ...f words from storage These words are found by adding AC 30 35 the first six bit group to SR 21 35 initially the instruction address and directing storage to this modified address The word thus found i...

Page 135: ...o of Conversions in SC 1 E Time Shift AC Rt EO D6 6 Shifts 2 12 33 1 Step SC E6 0l 1 Step 2 11 79 1 SB SR E7 01 Yes 6 Bit 2 12 50 r l tr t SC 0 No SR S 5 AC SR 18 35 AO A C 3 o 35 A 0 Develop Desired...

Page 136: ...of these representations equal to the count of the instruction with the contents of positions S 5 of a like number of words from storage The location of the first of these storage words is found by a...

Page 137: ...D3 3 06 16 1 AS AR All D1 3 06 18 1 I End Op IiIt1 l A I 2 09 49 1 Il2 12 70 1 6 Bit Replacement for MQ FIGURE 5 3 72 CRQ 0154 E Time Shift MQ Lt EO D6 2 12 42 1 Step SC E6 D1 2 11 79 1 SB SR E7 Dl 6...

Page 138: ...and a number of E cycles equal to the count Convert by Addition from MQ CAQ 0114 Min I L Figure 5 3 73 Max I L 6E This instruction treats the MQ as six 6 bit representations as does CRQ This instructi...

Page 139: ...tate MQ Lt Off 6 Shifts O 2 1 CAQTg C Step SC E6 Dl 2 11 79 1 SR S 35 AD P 35 E4 D3 2 1 1 1 AC Q 35 AD E4 D3 2 1 41 AD Q 35 AC Addition E6 Dl 2 12 31 1 I Yes SB SR rB1 L E 7 D 1 SC 2 12 50 1 SR 1S 35...

Page 140: ...6 2 223 700 3100 3306 3007 2 527 140 3100 3307 3008 3 032 400 3100 3308 3009 3 335 640 3100 3309 3100 0 3200 3400 3101 23 420 3200 3401 3102 47 040 3200 3402 3103 72 460 3200 3403 3104 116 100 3200 34...

Page 141: ...n CAQ Next C MQ Start Table Table Start Lac S 1 5 Lac Refer C S 1 19 C 21 35 Count 7 3000 3007 2 527 140 3100 2 527 140 3100 5 0 3100 3100 0 3200 0 3200 4 t o 2 527 140 6300 9 3200 3209 21 450 3300 21...

Page 142: ...oating point divide operation 2 Position 15 is set to one if overflow occurs in either the accumulator or MQ 3 Position 16 is set to one if overflow or underflow occurs in the accumulator 4 Position 1...

Page 143: ...D3 2 10 51 1 Force Str 17 Dl 2 11 40 1 AS AR 111 Dl 3 06 18 1 MF Store Decrement Zero in AR I Cycle Following Floating Point Operation Prevent Channel Trap 16 Dl 2 10 56 1 Prevent Interrupt 15 Dl 2 1...

Page 144: ...t trap are shown on Systems 2 10 51 1 An overflow or underflow causes the floating point trap trigger to be turned on This trigger initiates a pseudo STR instruction by blocking the instruction follow...

Page 145: ...automatic manual switch is set to MANUAL With the machine in this state the operator may enter and execute an instruction interrogate any locations in storage for a visual check of the information st...

Page 146: ...0 0 3 Panel Channel c a Select u 0 0 Storage Register 00 20 11 0 Trap Ind e c 0 Accumulator Register 00 20 30 0 See Fig 2 3 2 MQ Register 00 20 40 0 L for Breakdown 00 60 xx 0 9 02 01 1 Margina l Chec...

Page 147: ...in the transfer trapping mode Simulate The simulate lamp is on when the 7090 is operating in any of the following modes associated with the 704 709 or 7090 compatibility program 1 1 0 select and sens...

Page 148: ...is enabled to trap on a tape check The lamp for a particular channel is off when the channel is disabled Channel Tape Check These lamps one for each channel are on if any error is detected while writ...

Page 149: ...Power On Red The console power on lamp is on whenever power is applied to the console Central Components Power Check Yellow The central components power check comes on whenever a fuse or circuit break...

Page 150: ...tely removed from the 7090 system except the voltage to HR 24 and HR 30 points in the power control unit The emergency off switch is to be used only in emergencies because of possible dam age to circu...

Page 151: ...n Ctrl Tgr Man Ctr Tgr Man Ctrl Tgr On Ungated On Ungated On Gated Gated by Manual 04 20 05 1 04 20 05 1 04 20 05 1 and AO Allow Keys to be Turn on Op Turn On Tgrs Active in Auto PaneI Ctrl Tgr For Ot...

Page 152: ...p trigger Clear Key Figure 6 1 4 The clear key is only operative if the computer is in automatic status Pressing the clear key 1 Fires a 1 usec single shot to reset the clock and all channel registers...

Page 153: ...Fire Man 4 20 06 1 Or SS t 4 20 04 1 t Store Ori Turn On Man Or Tgr 2 09 00 1 1 OO 1 t Bring Up Clear Stg Turn On Clear Stg Tgr 4 20 06 1 4 20 06 1 If I Turn Off t MST Tgr Turn Off Man 4 20 11 1 Ori T...

Page 154: ...End Op Tgr at ElO Turn Off MST Tgr 4 20 11 1 Mst I Tgr 8 00 18 1 Reset PR 10 D3 2 11 40 1 1 Suppress SB to SR TR PR IC4 20 14 1 Suppress PC Adv 4 20 14 1 f Inhibit Op Keep to PR 2 11 40 1 Op Keys to S...

Page 155: ...ing Up Disp Minus On Disp Hold Tag Eff Addr Eff Addr Ori Reg Reset 4 20 20 1 4 20 20 1 2 08 01 1 t Calcu late Eff Hold AD3 Carry Addr Tgr Reset 2 10 65 1 2 12 76 1 t SR 18 35 to Gate XR Adders P 17 Sp...

Page 156: ...peration is under control of a toggle switch located on the customer engineer test panel The operator has the choice of low speed with a delay of 104 milliseconds between each in struction or high spe...

Page 157: ...ff MST Tgr 4 20 11 1 Bring Up Not BCycle Int 8 00 13 1 Gate Master I Time 8 00 18 1 Reset PR 10 D3 2 11 40 1 t Turn Off Op Panel Ctrl Tgr 4 20 16 1 Execute Inst End Operation A6 All I All Fire Man Tur...

Page 158: ...0 05 1 1 Turn Off End MSTTgr A Operation 6 4 20 11 1 On at 14 Bring Up Not Turn On B Cycle All Man Stop Tgr Interrupt 8 00 13 1 4 20 18 1 t OffatA1 Gate Master Turn On I Time All MST Tgr 8 00 18 1 4 2...

Page 159: ...skipped The six sense switches may be set on or off from the operator s panel The condition of the switch may then be checked by sense instructions in the program to determine whether to skip the fol...

Page 160: ...DATA PROCESSING SYSTEM t 6 Control Switch D J FIGURE 6 2 1 CUSTOMER ENGINEER TEST PANEL 159 30 Control Switch...

Page 161: ...g divide T 2 is turned on if the quotient is greater than 2 T 2 is turned on at the beginning of a floating multiply second step to gate second step operations The T 2 trigger is found on Systems 2 10...

Page 162: ...e All AND A9 D1 Turn on Tgr Tgr Turn On Tgr 2 09 46 1 Reset at L11 D1 f Reset 16 D1 FIGURE 6 2 2 AND CAQ AND FP TRIGGERS FP Tgr 2 10 29 1 CAQ T r 2 09 49 1 f Fire Man Or SS 4 20 04 1 Turn On Man Or Tg...

Page 163: ...trigger 6 2 02 Switches I a Interlock Switch The I a interlock switch is effective only when the system is in manual status It has two positions automatic and manual With both the automatic manual an...

Page 164: ...and L When the machine cycle key is inserted into the customer engi neer s panel and pressed the machine cycle trigger and machine cycle gate trigger are turned on at A O The machine cycle trigger tu...

Page 165: ...Time Orl Cycle Gate Tgr A3 4 20 16 I 4 20 10 I L Mach Cycle A Key FIGURE 6 2 4 Fire Man Or SS 4 20 04 1 t Turn On Man Or Tgr 4 20 05 1 t Turn On Mach Cycle Tgr Turn Off Man Or Tgr 4 20 10 1 J Turn On...

Page 166: ...of gates in any single module or combination of modules can be biased at the same time The only exception is the 7302 memory This module is under control of only one key A and the whole module will be...

Page 167: ...is a 15 position register of triggers It is labeled 3 through 17 The address register signals the desired address to the core control circuits Figure 7 1 1 Control lines for the address register are A...

Page 168: ...Reset AR A MF AR L n 8 Time 7 1 1 ADDRESS REGISTER S8 3 11 to PR MF S8 0 A TOA OPK PR Out ut of PR Reset Pr Re R 7 1 2 PROGRAM REGISTER SR SI A Set Ind TOA A Invert SI A R Comp Output SR SI A TOA A R...

Page 169: ...ounter are ADV PROG CTR PC to AS 02 11 51 1 03 05 09 1 The program counter is a count up counter and can sequentially step through a program 7 1 07 Accumulator Systems 02 03 00 1 02 03 37 1 The accumu...

Page 170: ...ht A Gate MQ to SR SR MQ 7 1 4 MQ POSITION Gate AC SR A AC SR r AC Left In 0 TAO TAO AC Rij In AD to AC I Set AC I R r R A Hold Ace Right Out I Gate Shift Right A Gate Shift Left Left Out A Gate AC A...

Page 171: ...ms other than the normal diagnostic programs may be used to troubleshoot the machine For instance in diagnosing troubles which appear only when the cus tomer s program is being run the program may be...

Page 172: ...Hold XRC A R P Gate XRC AD XRC Output P Gate XR AD FIGURE 7 1 6 INDEX REGISTER r Gate SR SR 0 A Ace SR r TAO j MQ SR AS SR MF SB SR TAO SR SI Adder to SR SI to SR L Comp SI to SR A R SR to MQ Gate OP...

Page 173: ...cc Step address in Acc by one Repeat These instructions are used so this program will not be destroyed even if a diagnostic program using a trapping mode is later run on the machine Store Address The...

Page 174: ...storage starting from location 20 are searched Op Deer Tag Adr 0 IOCD 15 00003 1 HPR Halt to set keys 2 ENK 3 STQ 00017 4 CLA 00020 5 CAS 00017 6 TRA 00010 7 TRA 00014 10 CLA 00004 11 ADD 00016 12 STA...

Page 175: ...one phase in some power supply will usually be indicated by a larger spread in the voltage reading of the three phases The normal readings should be recorded for future reference This procedure is no...

Page 176: ...vel internal syne N All 01 Test pt 1 lJSee em 03A 1 volt em 40170 lOx attenuation on Systems 8 00 40 1 internal syne Cloek Trigger 1 Test pt 1 IJsee em 03A 1 volt em 4EI7B lOx attenuation on Systems 8...

Page 177: ...1 4 While still synchronized on I time change the instruction still under continuous enter instruction from LDQ to CLA 0500 Check the following points that the C pulse set is wholly contained within...

Page 178: ...20 14 0 2 10 53 1 Trap Control Indicators 00 60 02 0 2 10 56 1 X Carry AD 3 00 20 19 0 2 12 76 1 9 Carry 00 20 19 0 2 10 37 1 9 Overflow 02 20 19 0 2 10 39 1 7 3 02 Indicator Lights Indicator lights a...

Page 179: ...the switch lever is brought as deeply as possible into the plastic rocker Removal and Replacement To remove a switch it may be necessary to loosen the bar upon which all the switches are mounted This...

Page 180: ...ht hand motor mounting bracket to the next bracket 3 Take out the screws holding the right hand motor to the mounting bracket 4 Unplug and remove the motor Remove the right hand coupling sleeve from t...

Page 181: ...s on the frame or gate in question with a voltmeter to see if they act ually change as they should Sometimes one can determine by listening whether the marginal check relays in the power supply have b...

Page 182: ...tor portion They consist of a 104 conductor a 34 conductor and a 75 conductor connection The 104 conductor cable contains the marginal checking control lines the 34 conductor cable contains the 400 cy...

Page 183: ...8HOIB 08 H 09 0 1 4o 08H05B D 0 D 0 0 0 D 0 0 o o EXAMPLE 0 l L L 01 08H09B 08HOIC 08H05C 08H09C 08HOID TAIL GATE FRONT VIEW 08H05D 08HO 90 FIGURE 7 6 1 CONSOLE GATES AND TAILGATE 1 I I I I I TAIL GAT...

Page 184: ...X 107 X X 71 X X 79 X X 85 X X 91 X X 79 X 85 X X 79 X X 79 107 X X 107 116 114 114 X X III X X 104 126 X X 102 X 99 X X X X X X X X X X X X X X XX 126 OPERATION CODE ALPHA OCTAL LDI 0441 LDQ 0560 LFT...

Page 185: ...X X 94 X X 94 X X 94 X X 94 X X 94 x X 94 X X 94 X X 94 X X 94 X X 94 X X 94 X X 94 X X 94 X X 94 X X 94 X X 97 X X 97 X X 97 184 OPERATION CODE ALPHA OCTAL TEFD 0031 TEFE 0032 TEFF 0032 TEFG 0033 TE...

Page 186: ...00 06 1 06 00 06 1 06 00 06 1 06 00 07 1 06 00 07 1 02 10 61 1 60 65 04 1 60 65 04 1 60 65 04 1 60 65 04 1 60 65 04 1 185 Operation Code RDCF RDCG RDCH RDS REW RFT RIA RIL RIR R1S RND RNT RQL RUN SBM...

Page 187: ......

Page 188: ...RUCTION REFERENCE FORM 223 6895 1 FROM NAME OFFICE NO CHECK ONE OF THE COMMENTS AND EXPLAIN IN THE SPACE PROVIDED o SUGGESTED ADDITION PAGE TIMING CHART DRAWING PROCEDURE ETC o SUGGESTED DELETION PAGE...

Page 189: ...NESS REPLY MAIL NO POSTAGE STAMP NECESSARY IF MAILED IN U S A POSTAGE WILL BE PAID BY IBM CORPORATION P O BOX 390 POUGHKEEPSIE N Y ATTN CE MANUALS DEPARTMENT 296 STAPLE F OLD F IRST CLASS PERMIT NO 81...

Page 190: ......

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