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Version 1.0 

11/08/01 

 

 

 
 
 

(c) Copyright International Business Machines Corporation 2001 

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All information contained in this document is subject to change without notice. The products described in this document 

are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death 

to persons.  The information contained in this document does not affect or change IBM product specifications or 

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property rights of IBM or third parties.  All information contained in this document was obtained in specific environments, 

and is presented as an illustration.  The results obtained in other operating environments may vary. 

 
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Summary of Contents for 25CPC710

Page 1: ...interleaved memory controller supports SDRAM at 100 or 133 MHz both single bank and dual bank PC100 PC133 and registered DIMMs are supported The memory controller design requires the use of an extern...

Page 2: ...e reset state The two Reset registers CPC0_RSTR and CPC0_SRST have been modified to include bits to support program control operation of hard and soft reset signals for the additional processors Conne...

Page 3: ...s one additional clock cycle to the internal sequencer signals for read operations of registered DIMMs Setting SDRAM0_MCCR 19 1 shifts the following signals by one clock cycle MUX_SEL MUX_CLKEN1B_ MUX...

Page 4: ...CI 32 bus is disabled Bit 16 of chip control register CPC0_PGCHP can be read to determine the detected arbitration mode a 0 indicates the internal arbiter is in use and a 1 indicates an external arbit...

Page 5: ...al packaging v I O Pinout Deletions The following I Os are no longer present on the DD3 revision INTERFACE SIGNAL NAME IMPACT Memory Interface SDCS_12 SDCS_13 SDCS_14 SDCS_15 SDRAS_2 SDRAS_3 SDCAS_2 S...

Page 6: ...ecomes SDQM SDRAM0_MCCR 14 1 Memory Interface SDCAS_1 becomes SDQM SDRAM0_MCCR 14 1 Memory Interface WE_1 becomes SDQM SDRAM0_MCCR 14 1 Memory Interface G_ARB becomes SDQM SDRAM0_MCCR 15 1 60x bus Int...

Page 7: ...bit to 1 disables the correction logic PCILx_DLKCTRL 28 when set to 0 enables the erratum 9 correction logic to function correctly when the programmed value in the PCI local register PCILx_DLKCTRL 8 1...

Page 8: ...plantation or other life support applications where malfunction may result in injury or death to persons The information contained in this document does not affect or change IBM product specifications...

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