IBM 2030 Manual Of Instruction Download

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Summary of Contents for 2030

Page 1: ...Field Engineering Manual of Instruction Processing Unit System 36D Model 3D...

Page 2: ...30 I O Control Field Engineering Manual of Instruction Form 225 3362 Minor Revision August 1965 This edition 225 3360 is identical in content to the previous edition Z25 336Q The IBM Confidential clas...

Page 3: ...ramming Introduction Micro Program Examples Control Field Mnemonics Parity Bits ROS Addressing ROAR Contro1s ROS Timings Physical Description Machine Check Handling Forced Micro Program Entries Overal...

Page 4: ......

Page 5: ...CTION lated applications have more similari ties than differences For example because of teleprocessing and other factors scientific applications require high speed input output similar to that requir...

Page 6: ...ng speed of any particular unit Sub ject to these constraints a program written for a smaller System 360 will run without modification on a larger one While this upward compatibility is certainly an a...

Page 7: ...s per month as a Model 30 The answers will be the sallie only the number of answers in a given period of time will be different There are two basic differences between models core storage capacity and...

Page 8: ...m 360 Model 30 the 2030 processing unit provides all system control The processing unit is given instructions by a programmer These instructions are interpreted and executed by the processing unit Exe...

Page 9: ...ing problem with greater speed and efficiency than ever before This opens up greatly increased computer potential in every area In order to realize this potential it was apparent to the designers that...

Page 10: ...orage basic control program functions will be supplied with magnetic tapes or direct access devices Additional 1 6 capability can be utilized as more main storage is added For systems having 8K bytes...

Page 11: ...ort program generators sort merge specialized language it can be used in all kinds of applications including both commercial and scientific The FORTRAN language allows the pro grammer to code a mathem...

Page 12: ...ommercial vs Scientific Computers 1 8 The scientific computers were usually fixed word length machines and used a pure binary form of coding On the other hand the commercial computers were usually var...

Page 13: ...ers binary numbers or many different codes A half word is 2 bytes A word is 4 bytes A double word is 8 bytes Control Unit Printer Data can be fixed length 2 4 or 8 bytes or variable length up to 256 b...

Page 14: ...are probably a little perplexed about this byte by now You know that a byte consists of eight data bits and a parity bit You know that each byte is individually addressable by a 24 bit 1 10 binary ad...

Page 15: ...e I Byte Byte IByte Byte IByte Byte IByte Byte 0000 0001 0002 0003 0004 0005 0006 0007 0008 Half Word Half Word Half Word Half Word Word Word Double Word Figure 1 9 Boundary Restrictions The rule is t...

Page 16: ...perations use any of 4 double word floating point reg isters In Figure 1 10 you can see the logical 1 12 structure of the CPU for the System 360 and its relationship to the main storage There are two...

Page 17: ...s used by computers of the IBM 1401 family In it the data fields were b ought out of main storage operated upon and the results went back into main storage Figure 1 11 Other computers such as those of...

Page 18: ...g to the system the length of the fields In computers of the past this was done several ways The 1401 used a special word mark bit over the high order position of the data The IBM 70S II used zone bit...

Page 19: ...d oper and such as fixed length divide a pair of adjacent registers are used In these cases an even odd pair of reg isters such as 0 1 or 6 7 are used and the even register is addressed In this case b...

Page 20: ...ating on them with much precision To do floating point arith metic the System 360 has four floating point re isters Figure 1 18 Addresses Main I Storage Control Instructions I Section IFloating AlU Po...

Page 21: ...f the available main storage addresses The area of the main storage unit used for registers is called auxiliary storage Another example of hardware differen ces is in the control section of the System...

Page 22: ...n storage the channel requests a storage cycle The amount of data bandIed var ies depending on the particular model of System 360 After the data has been placed in main storage the channel waits for a...

Page 23: ...of an I O device with a self contained adapter The IBM 2803 tape control is Adapter Printer 1443 Model N1 Standard Interface Figure 1 21 Control Units and Adapters an example of a stand alone adapter...

Page 24: ...nels are designed to operate with high data rates 1 0 devi ces such as magnetic tape disk units drums and buffered card devices are the 1 20 E L Sel Ch 2 Up to Eight Tape Drives devices most likely to...

Page 25: ...sters and left there On a multiplexor channel it is possi ble to have I O devices operating simul taneously To have all this information in the multiplexor channel s registers would require a set of r...

Page 26: ...ing system apply here Let us check The base is two so the maximum symbol value is one The binary numbering system has only two valid symbols 0 and 1 Example Digit Base Place 0101 Ox2 3 1x2 a Ox2 1x2 0...

Page 27: ...00 28 50 0011 0010 32 60 0011 1100 3C Examples Express the hexadecimal hex numbers as a sum of terms in decimal hex 482 4x162 8x16 1 2x16 4x256 8x16 2x1 1024 128 2 1154 decimal hex 8C6 8x162 12x16 1 6...

Page 28: ...heSystem 360 uses hexadecimal floating point and the hexadecimal point 1 24 of all numbers is placed to the left of the high order leftmost nonzero digit Hence all quantities may be thought of as a he...

Page 29: ...ment notation with a one bit in the sign position In all cases the bits between the sign bit and the leftmost Significant bit of the integer are the same as the sign bit i e all zeros for positive num...

Page 30: ...true form but overflow sign is incorrect 57 00111001 Hiqh order carry no 92 01011100 sign position carry 142 10010101 overflow Sign position indicates a complement result but overflow signals are inco...

Page 31: ...Operation Analysis Before any packed decimal arithmetic can take place a sign operation analysis must be performed The result of this analysis determines whether the opera tion is to be a true add or...

Page 32: ...at to subtract six really means comple ment add six The result will be the correct decimal number in true form Example 8421 8421 0001 0110 0110 0110 0111 1100 0001 1000 NC C 1001 0100 1010 0000 0011 0...

Page 33: ...ent is expressed in excess 64 arithmetic The Signed exponent is algebraically added to 64 A result above 64 indicates a positive exponent a result below 64 indicates a negative exponent Conversion Exa...

Page 34: ...Normal ization consists of shifting the frac tion left and decreasing the charac teristic one for every hexadecimal digit shift Floating Point Multiply and Divide The multiplication of two floating p...

Page 35: ...part of an oper ation remain unchanged The floating point instructions are the only instructions using the floating point registers DATA FLOW SYSTEM CONTROL Read Only Storage ROS controls data moveme...

Page 36: ...s A oJ r P ROS I SAL WX Bus t Next Address Information Control Register P q z Bus T F I From External Interrupt To Machine Control Points Figure 1 25 IBM 2030 Data Flow lJ L J Z Bus Register Storage N...

Page 37: ...e location in core addressed by the MN register These three opera tions are instructed by micro programming through the use of ROS control fields DATA BUSES There are 7 general data buses which move i...

Page 38: ...er position being the zero Reference to a particu lar bit in a register then can be S7 which is the low order position of the S register etc In addition to the ten registers there are other registers...

Page 39: ...ters and floating point registers are addressed with a 4 bit binary address As a result instructions are of different lengths depending on the location of data System 360 instructions may be one two o...

Page 40: ...Bits 0 and 1 of the Op Code specifies whether data is in main storage in the general registers or in floating point registers Because the instruction length depends on the location of the data the ins...

Page 41: ...ses are generated by adding a displacement value to a base address The instruction contains the dis placement value as well as the address of the general register containing the base address The gener...

Page 42: ...ain Storage As can be seen in the above example our 12 000 byte program starts a loca tion 2 048 and runs through location 1 38 14 047 We have divided the program into three sections The first two sec...

Page 43: ...d in one of the general registers When only one of the operands is in main storage the instruction is 2 halfwords in length To add a main storage operand source operand to a general register operand d...

Page 44: ...portion of the instruc 2n is unchanged 3 The values in the base and index registers are unchanged Thus the only thing we did was generate a storage address by adding the contents of the base register...

Page 45: ...I ADD I 3 I 7 I 4 I 1024 I ________ ______ ______ ______ ______J For the above RX type instruction the storage address is generated by adding the low order 24 bits of the contents of registers 7 and...

Page 46: ...S Format and looks like this 1 42 r T T I Op Code L I B1 I D1 I B2 I D2 I l r r J I I I I I I L ___ J l_________J l________J Length Location Location Code of 1st of 2nd Operand Operand Destina Source...

Page 47: ...s a range of 0 to bytes 10 Only general registers to can be used as Ease or index registers 11 What happens if register 0 is spec ified as a base or index register 12 Label the fields of the following...

Page 48: ...scussion we can think of I time as being separate from E time Instructions are generally thought of as having two parts One part of the instruction is used to tell the computer what to do such as Add...

Page 49: ...address portion of the current PSW must be updated for each instruction that is fetched and executed That is if an RR type instruction is fetched from location 1000 the instruction address portion of...

Page 50: ...ranch to location 2000 the instruction address portion of the current PSW will be changed to 2000 In the above example bits 40 63 the instruction address of the current PSW might actually be updated t...

Page 51: ...of 0000 results in a no op instruction A mask field of 1111 results in an unconditional branch instruction One of the instructions of the System 360 is an instruction called Branch on Condition This i...

Page 52: ...0000 b It can test for a specific result such as an equal compare by set ting one of the bits of the mask field r1000 c It can test for a multiple result such as an equal or low compare 1 48 by settin...

Page 53: ...S Extensive programming features dic tate the need for an operating sys tem In an operating system environment control programs perform such func tions as program loading storage protection I O operat...

Page 54: ...In other words the data processing system was idle about half the time while the operator was Setting up for the next problem pro gram Clearly this was an ineffecient way to control an installation In...

Page 55: ...l program remained in 3 main storage as the problem pro grams were executed The control program served only as a linkage between jobs Its only fUnction was to bring in a new problem program as each jo...

Page 56: ...or Prog A Data In this function of a control program control will pass back and forth between the problem and control programs during the execution of the problem program This differs from the origina...

Page 57: ...ain storage and fetches a new PSW from main storage Processing resumes at the instruc tion address specified by the instruction address portion of the current PSW just loaded There are five classes of...

Page 58: ...upervisor 1 54 Can be caused by pressing an interrupt key on the operator s console Caused by an instruc 3 Program 4 Machine 5 1 0 tion known as super visor call aused by a program check Caused by a m...

Page 59: ...Divide 00000000 00001111 1 2 Complete Supervisor Call Old PSW 32 New PSW 96 Instruction Bits 00000000 rrrrrrrr 1 Complete 1 r Bits 8 15 of Supervisor Call Instruction External Old PSW 24 New PSW 88 Ex...

Page 60: ...ain the address of the next instruction that would have been execut ed if the interrupt had not occurred 1 56 When the interrupt is complete the supervisor may elect to return to the point of departur...

Page 61: ...s the current PSW is stored in one of five locations reserved for the old PSW It is at this time that the interruption code of the current PSW is set r 1 Interrupt I I Occurs I I I L T J I I I r I Set...

Page 62: ...tion supervisor call the current PSW prior to the interrupt is stored in location 0032 Then the dou bleword at location 0096 is brought out and becomes the current PSW This PSW directs the system to t...

Page 63: ...ol section This is the last instruction in the supervisor s interrupt handling routine Note that this return to the problem program by replacing the PSW is done by means of an instruction load PSW and...

Page 64: ...Supervisor Call interruption 1 60 The Supervisor Call instruction is of the RR format The R1 and R2 fields of a Supervisor Call instruction are placed in the interruption code field of the SVC old PSW...

Page 65: ...nnot be masked Sometimes in a program it is not desir able to allow an interrupt This is most apparent when we consider the I O interrupt In the System 360 it is possible to have simUltaneous 1 0 oper...

Page 66: ...1 62 The system mask that determines whether or not to mask I O and external interrupts is in the current PSW In the case of an I O interrupt the chan nel causing the interrupt will be stored in the i...

Page 67: ...try PROGRAM MASK Program checks such as a specification exception also can cause an interrupt While machine checks cause machine interrupts program checks will cause a program interrupt On a program i...

Page 68: ...I mode A key difference is in the rep resentation of sign values If bit 12 of the PSW contains a one the ASCII sign codes will be internally generated rather than the extended BCD codes for signs For...

Page 69: ...sed to indicate the state of the instruction associated with that PSW 12 15 r IA M W PI L_______ J t Problem State Bit When bit 15 of the PSW is zero the instruction associated with that PSW is part o...

Page 70: ...erviced 1 66 r r ISupervisor I IProblemI I I Load PSW I I 1 I I IProgram I IProgram I L__________J L ______J The problem program would enter the supervisor program by way of an inter rupt This interru...

Page 71: ...______J Main Storage SET PROGRAM MAS INSTRUCTION The Set Program Mask instruction is used to change the setting of the condition code and program mask in the current PSW Set Program Mask is of the RR...

Page 72: ...rflow REVIEW QUESTIONS ON SYSTEM 360 AND INTERRUPTS 1 List the five classes of interrupts a _______________________ b ____________________ _ c ____________________ _ d _ _ _ _ _ _ _____________ _ 1 68...

Page 73: ...to change the current PSW easily because of the concept of privileged instruc tions However what is to prevent the problem programmer froIl modifying the New PSW s which are in main storage After all...

Page 74: ...that block of main storage 2 A protection exception will result in a program interrupt if the two keys are not identical If one of the keys contains a zero the keys are said to match and the protec t...

Page 75: ...ed by the R2 field r T T I 08 I 3 I 5 I L____ ___ ___J t t t I I I I I I Set I I I This register Storage J I l has the address Key I of the 2k block I I Rey is in this register Storage addresses in th...

Page 76: ...storage key instruction is a privileged operation It may be issued only when bit 15 of the PSW problem state bit is zero In a typical supervisor controlled operation the supervisor causes a problem pr...

Page 77: ...storage key of 15 This means that unless a problem program has a key in its PSW of 0 or 15 it will not be able to modify or change information in the area being used by the supervisor program This is...

Page 78: ...instruction to help a supervisor program assign storage keys It is called Insert Storage Key This instruction does not change any storage keys Its purpose is to inspect or examine a storage key The In...

Page 79: ...lock Rey A 0 B 1 C 2 0 3 If an instruction with a PSW key of 3 attempts to alter data in block c a The data will be stored and the program will continue b The data will be stored and the program will...

Page 80: ...rruption code of the new PSW b Program interrupt with a pro tection violation indicated in the interruption code of the new PSW c Program interrupt with a pro tection violation indicated in the interr...

Page 81: ...parallel tied through a resistor to a positive voltage source The anodes of the diodes face in the direction of the positive source Figure 2 1 While any of the input lines are negative current flows t...

Page 82: ...his is only one type of inverter Input lines are connected differently on other circuits but the principle of operation is the same The inverter has only one input and the output is always of oppo sit...

Page 83: ...o the line which prevents signal reflec tions and noise The logic block is labeled DLR and is of the 5 10 nanose cond family of circuits REMEMBERING DEVICES Remembering devices can be shown as single...

Page 84: ...tive the output will drop The output line will always follow the data line when the control line is active THE FLIP LATCH Combinations of AND and OR logic blocks are used to allow several set lines an...

Page 85: ...Hold latch will always follow the Data line True False 10 The requires a latch back line CENTRAL PROCESSING UNIT CPU CLOCK A 2 megacycle clock circuit produces clock pulses P1 P2 P3 and P4 The overlap...

Page 86: ...as the esc and Osc lines and are used in the same manner to turn on and turn off the clock latches This timing chart shows that all clock latches are on for 500 nanoseconds and that they successively...

Page 87: ...P4 e Clock Reset R I FL OSC A N I D Figure 2 15 CPU Clock Timings This distribution system sends out 500 nanosecond pulses to each large card that needs the particular pulses The pulses are then swit...

Page 88: ...pulses for internal operations of gates pulses and reset lines as well as providing timing pulses for the multiplexor channel to which I O equipment is attached The clock must be told to start and st...

Page 89: ...equest t A Load Key Switch N System Reset Switch Clock Stop Key Switch Timed MC Stop Reset 0 Mach Reset Switch R or Power On Reset L Figure 2 17 CPU Clock Control clock start latch is reset if it is r...

Page 90: ...registers The data is then gated to the ALU in differ ent combina ions Any register can be gated individually onto the A bus and to the A register under the control of the ROS field CA The A register...

Page 91: ...W V GX ll Status kV 11 Decode 11 r r CK 0 In Out fc B Bus A Bus 0 o A B 1 P B r Register ALU P WX Bus A oJ r Register r WX i 4 lJ l1 l1 B US tzd I Iu Lv 1 I I J 1 T L D R P I IStorage JI P ROS t Next...

Page 92: ...8 0 0 0 0 7 0 7 7 o 0 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 7 7 7 Control Register Storage Address Latches ReadintoA register Read into B register Functional and Carry Controls A Input to ALU High Low or Cr...

Page 93: ...ich indicated a complement binary add The CC field forces a carry into position 7 of ALU PACKED DECIMAL ADDITION Two conditions must be considered to do decimal addition First a pack B register 14 A r...

Page 94: ...r bit group is 8 register 6 Circuit 14 6 000 1 0 1 0 0 o 1 1 0 0 1 1 0 investigated and if no carr exists six is subtracted from each four bit group Data from the decimal corrector circuit is then put...

Page 95: ...only one up level ALU DETAILED DESCRIPTION The ALU unit through the combinations of three control lines can perform the following functions Adding and subtracting by comple ment entry ANDing output o...

Page 96: ...o 1XX Not CCO 01X L Connect or CC1 CC1 CC2 XII Figure 2 27 Decode of ALU Control Lines 2 16 Numeric Decode Mnemonic 2 0 0 1 1 4 DC 5 1C 4 DC 5 1C 6 CC 7 l f Q Q l f Add Operation also Exclusive Or Fro...

Page 97: ...line up and Not Carry In line down meatlsthat no inputs can be active to AOI 5 and that an input must be active at AOI 6 The condition at AOI 5 can be satisfied by a down level from AOI 1 A OR N D Su...

Page 98: ...d for cor rect answers The Carry Latch is the third posi tion of the S Register S 3 Carries into and out of ALU involve several circuits As shown in the exam ples previously given a carry can occur fr...

Page 99: ...to set the Carry Latch which is position 3 of the 5 register 53 You will notice from Figure 2 31 that in order to set 53 a carry out of the zero pOSition of ALU had to be switched with Gate Carry to...

Page 100: ...bit 4 is ON the output of the decimal corrector will produce L Z BUS 4 Bit and L Z Bus 4 Bit If the 4 bit position is Q l these two lines will have the opposite voltage level output Three bit position...

Page 101: ...ARITHMETIC CPERATICN 1 Data to ALU is supplied from 2 ALU lines are bits wide 3 The control of data moving through ALU is by 4 List the four basic ALU operations 5 Data can be gated to ALU from the A...

Page 102: ...t is the R register This register has two input sources and three major destinations See Figure 2 18 One input comes from the main storage unit consists of 9 bit lines 8 parity and is labeled Storage...

Page 103: ...are latch es and latches 4 Register read out is non destructive True False 5 All registers read out to the B bus but only three registers read out to the A bus True False CORE STORAGE ADDRESSING THEO...

Page 104: ...In the example shown the four low order digits 1111 15 decimal combine with the two high order digits 10 32 decimal to select storage location 101111 47 decimal Ten Digit Addressing Ten binary digits...

Page 105: ...Binary Position 32 16 8 4 2 00 Binary Value 15 16 00 16 31 32 32 48 47 48 63 Figure 2 37 Six Digit Addressing 2 25...

Page 106: ...0960 0 1 0015 0911 0975 0 4 0016 0 1 0031 0927 0991 0 0032 o l 0047 0943 1007 0 OM8 0944 1008 0063 0959 1023 16 Binary Position 128 64 32 16 8 4 2 Binary Value 0 0 0 0 0 0 Figure 2 38 Ten Digit Addre...

Page 107: ...96 0960 1 1 1024 1920 1984 7168 8064 8128 14 15 7183 00 0016 7184 8080 8144 01 1944 00 16 15 7199 32 00 8000 48 l 14 15 0047 1071 1967 2031 8015 8111 8175 00 0048 0944 1008 1968 2032 8016 01 7168 Figu...

Page 108: ...erties of magnetic core storage reveals that this device can be readily applied to produce an extremely fast storage device capable of storing the information required in the IBM 2030 Processing Unit...

Page 109: ...ice 1 2 Current 1 2 Current Figure 2 41 Half Current Principle TWo Wire Addressing Two wires pass through each magnetic core Core is magnetized by additive effects of the two magnetic fields By passin...

Page 110: ...switch and the right address selection switch coincident current will be produced in core That one core will be flipped to a polarity dependent on the direction of current flow Figure 2 44 The core s...

Page 111: ...6 32 Figure 2 43 8R Storage 00 01 14 15 00 01 14 15 00 08 1 r 8GROU OFI6ROWS 0000 0896 0960 1024 1920 1984 7168 8064 8128 ___r ___ r __ __ __ r L__ l9W L J 3 E r ___ r __ r r __r __ r __ r r_c J_ 8127...

Page 112: ...Binary 1 o o Address 0 Value 0 896 00 00 Address Value 1024 Figure 2 44 Magnetic Core Drive 2 32 00 Address Value 1024 Address o Value 00 896 00 Binary 1 Binary 0 0 Binary 0 jll 0 0 0 0 0 0 0 0 all 0...

Page 113: ...to no bit status a pulse is induced onto the sense winding Changing core to bit status called writing Changing core to no bit status called reading A magnetic core stores information by remaining in e...

Page 114: ...Set Core to Binary 0 Figure 2 46 Core Read...

Page 115: ...d ing Notice that to read out the addressed core requires the core to be flipped to the no bit status As far as the core itself is concerned the information is lost This type of information retrie val...

Page 116: ...Eight drivers 16 gate decodes and 128 gate transistors for each end of the Y drive lines The gate transistor with both base and emitter conditioned is turned on to supply drive current 2 36 2 3 2 N R...

Page 117: ...ode switch to condition the bases of four gate tran sistors one in each of the four groups From the 16 and 32 bits tN register 3 and 2 bits of the address one of four read drivers is turned on to cond...

Page 118: ...same relative core in each of the nine identical core planes Inhibit Controls writing in cores 2 38 Address Selection and Drive Sense winding shared by inhibit circuits Inhibit current prevents core f...

Page 119: ...re plane With no inhibit cur rent flowing through the sense inhibit winding of the addressed core coinci Figure 2 50 Inhibit dent current in the drive lines causes the core to flip For each core that...

Page 120: ...age unit is an additional 512 position aux iliary storage section In this section 256 positions are reserved for Use by the multiplexor channel The other 256 positions of local storage are used by the...

Page 121: ...U in a code that determines which area is to be addressed In the case of the 8K storage unit if the M register 3 bit is zero then the desired address is in multiplexor storage If the M register 3 bit...

Page 122: ...by a Y driver In this case the multiplexor read driver is turned on because the M register 3 bit is zero and because the CPU Main Auxiliary latch is set to Auxiliary STORAGE CLOCR There is a separate...

Page 123: ...acing a storage address in the MN register The storage circuitry is signaled to read and the storage clock is started Figure 2 54 A storage read cycle results during which time the desired storage loc...

Page 124: ...rom FL3 propagates down remainder of delay line 10 Depending on drive pulse width requirements a delay line tap turns FL3 off 11 Trailing edge of drive pulse propagates down TD4 lO5 lO6 Figure 2 54 De...

Page 125: ...drive lines 64X read gate transistors 64X write gate transistors 16X gate decode switches 4X read drivers 4X write drivers 128Y drive lines 128Y read gate transistors 128Y write gate transistors 16Y g...

Page 126: ...ap 1200 ns Write Call Latches Delay Tap 200 ns Delay Tap 950 ns Delay Tap 150 ns Delay Tap 775 ns Delay Tap 300 ns Delay Tap 750 ns Delay Tap 300 ns Delay Tap 750 ns 1 Delay Tap 500 ns Delay Tap 150 n...

Page 127: ...ciple allows twice as many storage positions to be addressed with the same drive circuitry Phase reversal takes place between 8K blocks Y drive lines wired through phase reversal plane X drive lines a...

Page 128: ...th for these currents The result is in phase write currents in the desired position in the basic 8K block To read out a core storage position in the second 8R block drivers Xl and Y2 are turned on Cir...

Page 129: ...the N register The M register 2 and 3 bits would both be set to one All other M register bits would be set to zero The 16K auxiliary storage unit has the four auxiliary drivers two read drivers and t...

Page 130: ...and 1 bits control drivers A 32K core storage unit is formed by tying two 16K units together in such a way that the Y selection and drive cir cuitry is shared Figure 2 58 Addi tional X drivers and X...

Page 131: ...Figure 2 58 32K Phase Reversal M REGISTER 2 BIT YES...

Page 132: ...des four additional 256 byte blocks of auxiliary storage These additional blocks of auxiliary storage provide additional subchannels for the iBultiplexor channel With the four additional blocks auxili...

Page 133: ...above the range 00000 32767 and starts the clock in the second 32K storage unit MEM ORY CPU INTERFACE Each 32R storage unit communicates with the CPU over an interface All address es data and control...

Page 134: ...d is actually before zero time in the CPU clock cycle If the early MO signal is present at the clock control circuitry at zero time of the CPU clock cycle the CPU read call signal starts the second 32...

Page 135: ...Driver Control Phase Reversal Decode Control Sample Binary 0 1 0 0 1 1 0 Address 7 2 5 6 STORAGE READ EXAMPLE Storage drive lines selected by MN register bits Clock selected by high order bit positio...

Page 136: ...ure 2 61 1 Start the clock for the first 32R storage unit MS321 2 3 2 56 Start 1st 32R clock Not Early MO eM register O bit Read Call Define area of storage to be addressed MS321 Use Main Mem Not Loca...

Page 137: ...eing turned on MS151 Y Gate Term Current Source from power supply Phase Read B from clock M Reg Not 2 Bit controlled 5 Sense and amplify the resultant data byte Each 8K block of storage has two sets o...

Page 138: ...rite the data into the addressed position To write a byte of data into a core storage position the CPU signals the core storage unit with a write call The address in the MN register does not change be...

Page 139: ...TOR MSI51 M Reg 7 Bit and Not M Reg 6 Bit Y GATE DECODE MS031 Figure 2 62 Storage Write Example Circuit Objectives Figure 2 62 Start the clock for the first 32K storage unit MS321 1 2 Start 1st 32K cl...

Page 140: ...Y drive line It is the result of the Y read gate terminator being turned on MS 151 Y Gate Term Current Source from power supply Phase Write A from clock M Reg ot 2 Bit controlled 5 Activate the approp...

Page 141: ...SA Inh Line 6 Bit Al These are the two ends of the inhibit winding for the desired 4 096 positions of the 6 bit plane of the third 81 block of storage For simplicity only the 6 bit is shown Nine inhi...

Page 142: ...registers 8 bits plus parity bit The parallel output of these registers is fed to the core storage addressing circuitry over the CPU to memory interface There is no gate at the output of the MN regist...

Page 143: ...condition where the address constructed in MN is outside the addres s range of the storage unit is called memory wrap Sensing this condi tion simply involves checking the M register 0 1 and 2 bits Fo...

Page 144: ...64 the core storage unit Information to be placed into the core storage unit must first be gated through the ALU to the R register Once in the R register this byte is available to the core stor age i...

Page 145: ...age sizes are the same as for the 2 0 microsecond M2 memory offered on early 2030 s The 8K 16K 32K and 65K refer to 8 192 bytes 16 384 bytes 32 768 bytes and 65 536 bytes of storage respectively Like...

Page 146: ...formation in the R register is placed into the ad dressed position FUNCTIONAL UNITS CORE ARRAY Timing and Interlock Signal R I 0 L L 11 Reg r r 7 7 1 fNO I r g ond Systems Reg 7 7 2030 Basic Circuitry...

Page 147: ...2 2048 Positions 2048 Positions 1 1 T 2048 Positions 2048 Positions 32 1 T 1 2048 Positions 2048 Positions 32 1 I t 64 Lines I I 1 64 Lines I I Figure 2 66 Core Plane Layout 32 Lines i j 71 1 I I I I...

Page 148: ...cores The tenth core in the top half of the last plane experiences coincident drive 9urrent However this core output is not sensed Depending on the direction of drive current the ten cores are switche...

Page 149: ...ame nine planes To address a particular position the appropriate Y One X Winding Second 16K V Winding Goes Through All 18 Planes Figure 2 69 32K Storage Winding winding is selected and driven This mak...

Page 150: ...sts of delay lines and timing latches The clock is started by either read call or write call from the 2030 The M2 I core storage unit contains a tim ing generator referred to as the storage clock Havi...

Page 151: ...MM102 n v oA Read Set Control MM102 lI Read 1 MM103 Read 2 MMI03 r X source Read MM102 V 1 Y Source Read MMI02 Strobe MMI03 La Read Echo MM113 II Data Ready MMI02 Figure 2 72 Core Storage Read Timing...

Page 152: ...e storage clock Current sources are special circuits de signed to supply drive current to the X and Y windings In the basic 8K storage unit there are four current sources X source read X source write...

Page 153: ...U05AE 1 U05AF I 05AG_ Go A 1 Write Clock Timing 1U05AE 1 U05AF 1 I O __I 6A __ Figure 2 74 Current Sources 1 1 I I I T ___ I I Write Current 1 Driver UI6AY Y Source Write Read Current 1 1 1 Driver Y S...

Page 154: ...n system acts like a switch at each end of the drive lines to direct the current source drive current to a single drive line Figure 2 75 Thus the current source supplies the current and the gate and 2...

Page 155: ...te and Selection I System I o o 0 I I I I I I I I I I TIII1TIT TIITTlll TTIll111 TTTITTTT TTllTTTT Il r 44 f 4 4 i I I I I f Gate and Selection System L_______________ ______________ Note Heavy Line I...

Page 156: ...Logic SENSE INHIBIT SYSTEM A combination sense inhibit winding is used 532EF Diodes Each sense inhibit winding goes through 4096 cores parallel to the X drive lines During a read cycle the sense inhib...

Page 157: ...D 6 6 __I __ _ Not Bit A Driver Circuit storage clock gates the sense amplifier output to a data latch which stores the bit until used by the processing unit During a read cycle if a core does not swi...

Page 158: ...the temperature of the core array A thermistor near the core array senses the array temperature The variation in 2 78 thermistor resistance signals a separate unit called a proportional controller Th...

Page 159: ...and 256 bit positions for multiplexor storage In the 8K unit these top positions would correspond to the 5 6 7 or P bit positions see figure 2 67 The eight auxiliary storage wind ings intersect with t...

Page 160: ...Positions TOP 8 Auxiliary Storage Lines 4 for CPU Local Storage 4 for Multiplexor Storage 2048 Positions 128 Positions 2048 Positions 128 Positions 2048 Positions 128 Positions 2048 Positions 128 Pos...

Page 161: ...dressed position are set to logical O This means the addressed position con tains an even parity byte 000000000 The write call signal from the 2030 starts the storage clock and conditions a write cycl...

Page 162: ...OIO d Iill r 16 155 111 L OOI r J D Lor OOO l 0 L _ MM302 X Read and Write Gates SI5ES S15ET Y line r c 5157 L L J tJc J tJC 616 r I l r l L W L J Y line all DR f _ r S t e l I r t f 157 16 I L t fl O...

Page 163: ...m storage clock b Turn on the y read current source MM252 Y Source Read from storage clock Go not M register 0 bit c Turn on RD 0 010 MM402 This is a Y decode switch for the source side of the Y line...

Page 164: ...lect and drive the same X and Y drive lines as were driven on the read cycle However now they are driven with current in the opposite direction Consider the Y line first For this it is necessary to tu...

Page 165: ...13 14 15 not N Reg 4 Bit X Wr 0 8K Rd 8 16K Source Wr 0 8K Rd 1 8 16KB The appropriate set of inhibit drivers must be gated so that only one set of these drivers turns on For this ad dress Inhibit 0...

Page 166: ...provide control of the extra Y lines Circuit control of auxiliary storage for the 8K unit requires four additional Y line bump decode drivers Figure 2 80 These drivers are controlled by the M register...

Page 167: ...WR I l r N Reg 1 IA Lr ri l H J DR I H I RD X Lines DR N Reg 0 WR N Reg 1 I A r L LJ L Rd Current Source DR H Read 2 Control 0 32K RD H m 67 DR 69 WR I 73 r 75 M Reg 3 d IA Bump d Drive lns Use Mein...

Page 168: ...me core planes The Y winding is one set of 128 lines threading through all core planes The result is that if one X winding and one Y winding are driven with drive current nine cores ex perience coinci...

Page 169: ...tly the same as for the 8K unit with the ex ception of the X control driver and X source driver The X control driver deter mines the direction of current flow in the X winding by switching on the prop...

Page 170: ...Description The 32K storage unit consists of 18 core planes The Y windings go through all 18 planes in a serial manner see Figure 2 69 There are two sets of X windings one for the first 16K and one fo...

Page 171: ...e curcuitry and sense and inhibit circuitry A single set of logics is pro vided to cover addresses up to 32 767 These logics contain appropriate notes to make one set of logics applicable for both uni...

Page 172: ...ogic page MM142 This same page applies to both the first 32K and the second 32K For the first 32K the M register O bit is inverted to p oduce the Go signal The M register O bit is re quired to produce...

Page 173: ...M register 0 bit simply blocks the Write Set latch and the drive pulse to the delay line when Write Call occurs This is possible be cause the M register is not changed between read and write cycles an...

Page 174: ...e MM002 write echo is a signal required by the 2030 in manual store operations It follows a 2 94 Write Call and indicates that the Write Call has been received that the memory clock is running and tha...

Page 175: ...s block diagram the control points have been numbered For example the in gate control point for the G register is numbered 3 To help illustrate again the need for control points we will use the logic...

Page 176: ...a pulse through the capacitor turns the SAL on and its output can gate the contents of R to the in bus 3 2 Out Bus S Register Now let s build a little The rest of the statement says in effect read in...

Page 177: ...our control points the SAL s and a selection for the source the line driver and coupling capacitor In our block diagram thus far we have only shown SAL s that were active r s s for our specific logic...

Page 178: ...se the line driver now we will read out R and also read in R Although this is right electrically and is a legitimate operation it doesn t satisfy the function of our logic statement 3 4 S Register We...

Page 179: ...EAD OUT R PUT THE OUTPUT THROUGH THE LOGIC UNIT AND READ IN S Check using Figure 3 6 Now we have a storage device and every time we impulse the Out Bus S Register line driver it performs the same fUnc...

Page 180: ...J R Register G Register S Register Out Bus In Bus r EE ILme t Driver Fi9ure 3 6 Multiple SAL Selection 3 6...

Page 181: ...is word or to add another We would like to continue to perform the first function we developed Let s add Out Bus S Register another ROS word and another driver Figure 3 8 This new word can perform the...

Page 182: ...R Register T I I T Line Driver 1 I I I Figure 3 8 Multiple Drivers 3 8 G Register Line Driver 2 S Register...

Page 183: ...rd of laminated fiber board These strings of plates are called sense pads The plates connected to a line driver RCS word are connected differently SAL 6 SAL 7 SAL 8 They are laid out in parallel on a...

Page 184: ...ure 3 11 the Mylar strip with a programmed ROS word is shown placed over tbe sense pads If tbe line driver is impulsed it will activate the SAL s required for our first logic statement In Figure 3 12...

Page 185: ...360 Model 30 the ROS word is 60 bits wide This means there are 60 capacitor plates on one line driver SAL 5 S In SAL 6 S Out SAL 7 Logic In SAL 8 Logic Out The words are packed on a sheet of Mylar exa...

Page 186: ...Line Driver I Line Driver 2 SAL I RIn SAL 2 ROut Figure 3 12 Two ROS Words 3 12 SAL 3 Gin SAL 4 GOut SAL 5 S In SAL 6 S Out SAL 7 logic In SAL 8 Logic Out...

Page 187: ...Figure 3 13 ROS Document 3 13...

Page 188: ...111111111111 1IIIIIiiliii illllllllill Ilglllllllll _ L L _ iU o IX _ rr i rz M...

Page 189: ...eads out the same control gates every time 2 An impulsed line driver provides a pulse through a capacitor to turn on J Control SALS Register Timing Ring a L ROS Field Decoder To Machine Control Points...

Page 190: ...CM I cu I CA CB I CK I P pi CD I F 1 CG 1 CV 1 cc J CS JA A AI I N 012345 5 A 0123 0123 012 I 01 I 0 23 01 I 0123 I K C I 0123 I 012 I 01 I 01 I 012 I 0123 I A 0 0 0 I I I 2 RO CA W 3 V67 0 AI 4 STI S...

Page 191: ...igure 3 11 These fields are used to control all data movement within the CPU ALL DATA MOVEMENT IS THROUGH THE ALU Arithmetic Logic Unit We will discuss the func tion control fields and the way they co...

Page 192: ...a bit for the straight or cross switches The machine stop func tion is also found here B CONTROL CG The 2 bit CG field controls the high low 4 bit gating from 3 18 the B register to ALU There is no s...

Page 193: ...core from R If followed by a store cycle the output from core is not used but lost The new informa tion for core is the data already in R and this is gated back to core If the read cycle is followed...

Page 194: ...ng other than 00 then this combination specifies Main Memory Figure 3 19 ROS Branch Control Fields 3 20 Branching Control CN CH CL CS The branching control fields CN 6 bits CH 4 bits CL 4 bits and CS...

Page 195: ...egisters 8 Branching is controlled by the and pOSitions of the ROS address 9 The field is often used as the source for constants 10 The CM and CU fields provide the gates for control ROS WORD FORMAT M...

Page 196: ...S Branch Ibis line cheCKS conditions which determine the X6 and Xl positions for branching Branch ing occurs dependent on GO and Gl If GO and Gl are both set to one a 1 1 branch is taken Line Eight Pr...

Page 197: ...ply Mult Mult D MuttS D 1101 Divide Divide D Divide S Divide Divide 0 Divide S Convert Add E 1110 Add Add U D Add U S to Dec logical Add U D Add U S Subtract Convert Subtract F 1111 logical S U D Sub...

Page 198: ...as written by a micro programmer might appear as shown in Figures 3 23 3 25 and 3 26 The des cription of each ROS word that is used to execute the instruction will be made in reference to the actual...

Page 199: ...Fi9ure 3 23 I Cycle Start 00 OIle E K iOll BIN A DXH t J l V 5 KBB N L5 C G4_ _ _53 10 _011E FL PT SINGLE HO G II ___ OllF FL PT DOUBLE HO A2 FIXED POINT 01 011D E K OI I BINI A DXH KL V 5 C R _ _ _...

Page 200: ...brings up the control lines to set the G register data to the A register input The B register input and carry insert pOSitions are zero The expression on the C line is 0 S7 This statement brings up co...

Page 201: ...ust also be updated Assume at this point there is a carryout that S3 is set to a one and let s see when and how this is handled by the micro program The C line of this ROS word causes the control line...

Page 202: ...X 1 2 v77 77777771 Floating Point Reg 2 3X 1 _ _ _ _ 3 _ _ I 0 6M0 6M CPU Store 4X 4 5X 1 1_ L1 5_ 1 I Ef I J G U V L O S 6X 6 9 7 L F lo a tin g P oi nt R egL 6 L L Floating Point Reg 4 7X 1 J 1 L J...

Page 203: ...lier that when the J register data had the value of one added to it and a carryout resulted that the I register must also be updated On the branch line an unconditional 1 0 branch is taken to address...

Page 204: ...C C L5 CAN5NZ_S2 C r R K W R R K_W R R Rl G3 RO 57 R56 SS Rl_____ EXT MINU5 5GN Ol 03AD E K l1l1 BIN A O K D 5 T N L5 C R R 1 57 11 03AF E BIN A 0 0 T N L5 R R 1 57 ADD OR 5UBT 10 03A6 E K OOOI BIN A...

Page 205: ...ill remember controls the high order poSi tions of the ROAR address The CK con trol field K value sets the W register to the value shown on the E line of this block To explain why let s look at the br...

Page 206: ...ad by the expres sion UV MN M LS M LS can be either main core M or local storage LS This portion of the expression further checks the G register Since G register determines that our Op code is in RR f...

Page 207: ...SS 0100 Regenerate WRITE the sum to core Branch 1 0 to address OleE ADDRESS 01CE Read the last byte of data from register 5 UV MN M LS Change the address in the T register T O T Reg 7 Byte 1 Old T reg...

Page 208: ...e set 1 a respectively The 2 position of the N register is set by the CN ROS control field 0 it position Position N3 is set by the CX ROS control field 0 position N4 is set to a 1 uncondi tionally N5...

Page 209: ...The data is then A source B source 0000 xxxx x are the program mask tits 0010 0000 R register set 0010 xxxx The four high bits 0010 when returned to core signify that our resultant answer was greater...

Page 210: ..._ 1 11 0lE3 E K I01l BIN A S KBB N LS C R R 1___1 1 0 0106 1 5 WRITE 1 __________ CO SO R R 0 ____ TEST PRO MASK Figure 3 26 Set Condition Register 00 01E8 E K IOO0 BIN A RL KH R 5 C 0 56 R R 0 ZERO O...

Page 211: ...gram mask bits by allowing or preventing a bit on the Z bus Let s assume the data in R is xxxx 1 yyy The x positions are those for the condition code The 1 means that this position is set The y positi...

Page 212: ...ral purpose registers as specified by X2 and 82 to the binary number specified 3 38 by the 02 field The facts that you will need before starting are these 1 General purpose register 4 X2 contains the...

Page 213: ...O tC OC S WRITE C ANSNZ S2 R R G2 G3 0 1 01 1 E BIN A DiR tC OC S WRITE ANSNZ S2 RG 3 01 0131 E BIN A J IO l JC S WRITE C R R 1 __ 11 0133 E BIN A J O l J S WRITE C R R GO ____ O 11 013 E BIN A V J S...

Page 214: ...s set to zero A carry is inserted The result of the addition is set into the J register J 3 40 A Register B Register Carry Insert ALU OUtput xxxx xxxx J Reg data 0000 0000 1 xxxx xxxx 1 An uncondition...

Page 215: ...as data One of the facts given was that register 15 contained the value of 1860 in binary this is Byte 0 Byte 1 Byte 2 Byte 3 00000000 00000000 00000111 01000100 The T register data is changed to Reg...

Page 216: ...data 0100 0000 Reg II 0000 0011 Byte 3 T register data 0100 0011 The next ROS word is at address 0132 ADDRESS 0132 The expression R O C DC transfers the data in the R register to the D register The D...

Page 217: ...adding a binary value as specified by D2 in our instruction to the data contained in two general purpose registers as speci fied by X2 and B2 in our instruction The U register and V register data is...

Page 218: ...S register is set to zero except for 52 which is set to a 1 d The R register data is zero 00 04B4 BIN D D t DC 5TORE I 57 I 57 A3 AA 10 0486 BIN 5TORE 00 0 52 52 0 A5 AA CONTROL FIELD MNEMONICS FUNCT...

Page 219: ...O ZERO ON ALU CARRY RESET LINE LATCH 1D50 SET LINE LATCH l050 FORCE ALU CHECK CHECK ASCII LATCH TEST INTERRUPT RESET MACHINE CHECK GATE UV REGISTER TO WX REGISTER RESET LOAD LATCH RESET F REGISTER SET...

Page 220: ...3 OR 4 OR CH F I E l D X6 Figure 3 30 Test Interrupts 3 46 X1 X6 Branch A Timer or External Selector Channel 1 Selector Channel 2 Multiplexor Channel o 1 o 1 o o 1 1 See Figure 3 30 This mnemonic is...

Page 221: ...condition can also occur on a 8k 16k or 32k unit This is detect ed by testing the high order positions of the M register l OE This mnemonic is used in diag nostic testing The first time this expressio...

Page 222: ...ine allows CF Sal 100 Stop T4 A Not S Reg FL Stop SW Process Stop S Reg Inst Add Load SW DLYD Stop SW OR Instr Step SW FL Figure 3 32 Stop Mnemonic 3 48 A A the CPU clock to be started until all ROS s...

Page 223: ...1 1 1 K2 1 3 Let s assume byte 27 has to be read The address in hexa decimal for byte 21 is BB This must appear in the N register BB in bit form looks like this 1011 1011 If the designations NO throug...

Page 224: ...NE BIT CARRY Z BUS TEST FOR ANY INTERRUPT ACTIVATED BY AS COL 64 1 0 I 2 3 4 5 6 7 8 9 A B C D E F MNEMONICS CS MNEMONIC DESCRIPTIO N LZ 55 LOW Z BUS EQUAL ZERO HIGH Z BUS EQUAL HZ S4 ZERO LZ 55 HZ 4...

Page 225: ...be executed is true used when the CV field is coded 51 A 1050 request will set S1 to 1 S2 52 is set to a 1 if there is a bit on the Z bus AN5NZ S2 53 Carryout from ALU This bit is used with the CC fie...

Page 226: ...s Figure 3 35 shows the fields and the parity bits used for each checking cir cuit REVIEW QUESTIONS CONTROL FIELD MNEMONICS 1 What mnemonic is used to gate the status of the I Wrap latch into the Wra...

Page 227: ...Only Add ress Register address selects two ROS words to read out The address in ROAR gates the proper ROS word to the sense areplifier latches Maximum storage is 8064 words A ROS board accomreodates...

Page 228: ...ON ROS BOARDS 0384 0448 0385 0449 0418 0419 0444 0445 0414 0478 0415 0479 0480 0481 0510 0511 f I 0 X REGISTER 6 8 it ii 1 i lii I 7 I 0 I I 0 0 I 0 0 0 2 I 4 2 I 8 4 2 I S OE A G L A A T DECODE T LIN...

Page 229: ...this figure ROAR consists of 15 latches The W portion consists of 5 latches the X portion 8 Two latches are used to maintain parity The darkened portion XO Xl and X2 positions of ROAR provide selectio...

Page 230: ...e selected Position X7 of ROAR was never used for address sel 3 56 ection This bit position provides a gate to the sense amplifier latches If as in the case of address 0712 position X7 is a 0 then the...

Page 231: ...one board The drivers are physical ly located On two small cards driver card A and driver card B attached to the ROS board There are 24 electrical ly connected drivers on each small card A X6 X5 X4 T...

Page 232: ...olled by the six lines for the X4 X5 and X6 posi tions of ROAR The other input is 3 58 1 I 1 I I I I 1 1 1 I I I 1 1 DRIVER T INPUTS 10 11 12 13 14 15 Ii DRIVER CARD B developed from the ANDed conditi...

Page 233: ...f 60 sense ampli fiers is gated to the sense latches depending on the setting of the X7 posi tion of ROA R If X1 is set to a one the word at the odd address is set into the sense latches The words loc...

Page 234: ...ount of ROS storage 3 4 5 3 60 A driver is selected by means of a line and a line ROAR consists of ________ latches How many drivers are used for each ROS board 6 How many sense amplifiers and sense...

Page 235: ...second 4R ROS module Acornplete description of 1401 mode operation is found in the Special Feature section The remaining posi tions of the register W4 through 7 CA I CK I GI lJ5 P 0 TI X Address Decod...

Page 236: ...next address to be executed in the program is 0225 what 3 62 positions of ROAR are changed and how might they be changed ADDRESS ROAR W Position X position Register Positions 3 4567 0123 4567 123 in h...

Page 237: ...nic CA W us used 2 What console switches are used to set ROAR 3 Which control field sets positions 0 5 of the X register 4 What address is set in RCAR as a result of a machine check 5 There are consol...

Page 238: ...a portion of T3 time The addressed ROS word contained in the SAL S is not gated to the control latches until T1 of the following cycle If the clock were to stop at T4 time the SAL s would contain the...

Page 239: ...ROAR This address is the first step of the alternate rricro pro gram to handle the interruption Also at this time the branch condi tions for address 0001 are set into backup X6 and X7 latches The bran...

Page 240: ...T4 time A control register check sets position 3 of the machine check register It also blocks the set of the indicator ROAR if the check stop switch is set to STOP The combination of the parity bits f...

Page 241: ...0 Left Side One side of a ROS board is pictured in Figure 3 48 The ROS documents are held to this board by means of an air bag_ There is a ground plane between adjacent boards as well as within the RC...

Page 242: ...Figure 3 47 ROS Module Front View 3 68...

Page 243: ...W I 0 1 ID t OL ottt Figure 3 48 ReS Board Layout 11111111 IIIIIIII1111...

Page 244: ...r 1 Document 1 is the upper most card on the right side of board O ROS Board ROS Board o o 0000 0001 I 8 0096 0097 9 0022 01fl 3 0118 0119 2 0024 00 5 3 10 0120 Ol I II 0046 00A7 I Console 0142 OlA 3...

Page 245: ...particular position of the machine check check register If the CPU is allowed to recognize error conditions an address is set in ROAR that is the start of a micro program to handle machine checks Thi...

Page 246: ...rror would occur which would stop the CPU clock The suppress A register check latch blocks further A register checks until the D register is gated to the A bus This does not occur in the micro program...

Page 247: ...riority Pulse Not Supr Malf Trap Not Priority lch Not Gt Switch WX Mach Chk Pulse First Mach lch Pigure 3 53 Me Regis er Allow A Reg Chk A Reg Chk T4 B Reg Chk T4 MN Reg Chk Allow Write T4 Ctrl Reg Ch...

Page 248: ...ctive when 1 The priority latch is off 2 Switches are not being used to set W and X 3 74 3 The first machine check latch is on 4 The suppress malfunction latch is off This latch determines whether err...

Page 249: ...in Location 80 2 Store 20 in Loc 81 if CPU Error 3 Store Old PSW 4 Set Registers to Good Parity 5 Allow A Reg Checks Load New MC PSW Perform Control Program for Handling Machine Checks Reset HI when...

Page 250: ...occur that would cause the CPU to execute a tight loop of ROS words without stopping Consider what would happen if a second error occurred before H1 is set ON A continuous branch would be forced to ad...

Page 251: ...o etc Figure 3 56 Priority Micro Program Entries Not Supr Malf Trap r N o tf p r io rii f ty La t ch L t A Not GT Switches to WX I X5 Mach Chk Pulse First Mach Chk Lat 2f L N o t P r io ri tY L a tc h...

Page 252: ...but only one can be handled Notice that to set tbe stacking latch for a MPX share request PH1 position 6 of the H 3 78 register must not be set Early in the MPX share request micro program this positi...

Page 253: ...H Reg 5 I PH Priority 6 Reset E CD 0101 H Control L ry T4 r Not H Reg 6 r t OR I MPX Share Req Mach Rst I PH PH 7 L Gate Switches to WX Gt Switches to WX Main First Trap PH Micro ROS Cyc fe 8 Program...

Page 254: ...ext CPU cycle In Figure 3 58 read call is develoF d and sent to the core storage unit as a result of the statem ent IJ MN Read call starts the 3 80 memory dock and specifies a memory read cycle While...

Page 255: ...2 T3 T4 T1 T2 T3 I I I T1 T4 T1 I I lA R1 R2 Op Code T2 I T3 T4 0100 I I 0109 I I I I I I I I I I I I I I Read Word 1 I I I I I IJ_MN I I J 0 l_J I I I I I Write I o 2 I 4 I 6 1 8 1 0 I P I 4 I 6 2 8...

Page 256: ......

Page 257: ...to all I O units is dropped simultaneously All data in core storage remains unchanged If the allow write latch is on at the time the power off switch is SECTION 4 POWER SUPPLY pressed a memory write i...

Page 258: ...RY2 6V DC All Supplies in Series All Thermal RY3 RY3 RY5 K3 4 ct Y_3 _O Figure 4 1 Power On Off Control 4 2 RY2 6V Sense Convenience Outlet Overcurrent Trip ThermoI Trip Overcurrent Sense Thermal Sens...

Page 259: ...CHECKING Marginal checking consists of varying certain supply voltages so that inter mittent failures become solid failures permitting more rapid trouble diagnosis Marginal checking has two basic appl...

Page 260: ...8 V AC 3 Phase 208 V AC I Phase Transformer 7 25 V AC Ferro Supp Iy DC Dist R W Storage R W Storage CCROS Console R W Storage CCROS Gate A Gate B System Gate A Console R W Storage CCROS R W Storage Ga...

Page 261: ...IJ performs the functions of the I star and UV performs the functions of B star Hardware is provided so that the Land T registers may be gated as a pair into the MN register when the T register is na...

Page 262: ...byte on If a word mark is associated with the character it is represented by having the bit 1 of the byte off The charac ter A without a word mark is represented as 11000001 in EBCDI code while the c...

Page 263: ...d in the 2030 for the compatibility feature is the EECDI code Because the 2030 is basi cally a binary system occasionally a translation of character codes from EBCDI to BCD and tack again is necessary...

Page 264: ...a conversion table in the local storage and MPX 1 areas of core storage to con vert 1401 BCD addresses to 2030 binary addresses This table also includes a storage bias constant to cause IBM 1401 addr...

Page 265: ...ress In this case the address is 02 HEX Addressing local storage with 02 brings out 02 which is added to 30C4 already stored giving new value of 30C6 Finally the icro program processes the tens posi t...

Page 266: ...Figure 5 5 Auxiliary Storage Map for Address Conversion 5 6...

Page 267: ...eds position brings out the binary equivalent of 500 plus bias When the tens digit addresses local storage for conversion the units position is assumed to be zero Since the tens and hundreds digits ex...

Page 268: ...able in the local storage first refer back to the EBCDI code of 1400 system character configurations Figure 5 1 Notice that if the bit 0 of all 1400 system Cp codes that did not have bit 0 on are forc...

Page 269: ...the use of the Cp code table assume that the Op code read out of the 1400 system program is an edit Ope The hexadecimal bit con figuration of an E with a WM in EBcnI is 85 Forcing on the bits 0 and 1...

Page 270: ...Figure 5 8 Auxiliary Storage Map for Op Code Conversion 5 10...

Page 271: ...ocations Place LT Regs in UV Regs Set 57 0 and 50 1 All Other Ops L No 56 0 MLU I o Op Word Mark Invalid Digit Hundred Zones Read Out Tens Digit Place Digit in U Reg High Set 56 0 Yes I O A Address Ro...

Page 272: ...t in V Reg Save Carry Tens Digit Address Invalid Completed I O A Address Completed Indexing Address Completed Read Out Hundreds Digit Of BAddress or Passible d Modifier Yes S2 0 _______ Address Inva l...

Page 273: ...M L Q or H Figure 5 9 Branch On 54 54 0 Branch On 50 4 Character Instruction I E Change Routine Yes 50 0 I Cycles Part 3 of 3 C No Branch On 54 54 1 Is Digit A Blank 4 Character B Instruction Ended B...

Page 274: ...No Yes Correct for WM Return to I Cyc les Figure 5 10 Move Op 5 14...

Page 275: ...Field Sign Analysis Was It A Special Ch Test Add B Field Sign Analysis R2 R3 RO No Add the Numeric Portion of A Field Reg D and B Field Reg R and Store the Result in Reg J R2 R3 Add Cp Part 1 of 5 S2...

Page 276: ...or Neg Neg Add The Zone Bits Of The Standard Neg Form A WM to The Numeric Resultant Reg J Put The Result in Reg R Z O No Set The Zane Bits Of The Resu It to Be The Same As B Field Put The Result Add...

Page 277: ...HE CARRY OUT A A STORE RESULT IN REG CARRY Our J I J AND SAVE THE CARRY l 1 l I OUT B FIELD IS AIS A FIELD S A I j I S I ADD THE CARRY IN F NUMERIC RESULT ICHANGE IT TO A ZERO ICHANGE IT TO A ZERO I T...

Page 278: ...e Numeric Result Reg G and Put The Result in Reg R Take 9 s Compl Of The Numeric Portion Put It Rl Was There A WM Is It The Unit s Position Negative Insert Plus Sign to The Numeric Result Reg G and Pu...

Page 279: ...toroge Add The Zone Bits Reg D to The Numeric Reg G Put The Resu It In Reg J Add The Zone Bits Of B Field Reg R to The Numeric Result Reg G Put 11 in Reg J Translate The Result Reg J From BCD Bock to...

Page 280: ...ead command A stacker select command for the 1402 must be given within 6 millise conds after a read command End of file occurs with channel end of the last card read Character representation to and fr...

Page 281: ...a read command causes the buffer to transmit data to the CPU but no card movement takes place TO make the 1402 on a 2030 act like a 1402 on a 1401 a circuit is added to Select Out OR Select Out 1 __F...

Page 282: ...ster Another modification of the 1402 circuitry on the 2030 changes the end of file condition When the 1402 is operating in 2030 mode an extra Read command must be issued after the last card is read i...

Page 283: ...Set Command and Address of Unit in UV Yes Reset Sense I O Command 1 Yes Yes Figure 5 14 1402 1403 Compatibility Part 1 of 2 Restore L T and S Regs test Branch and Return to I Cycles In from Forms or S...

Page 284: ...No 40p Yes r C Status in Service in PFR Op Figure 5 14 1402 1403 Compatibility Part 2 of 2 5 24...

Page 285: ...es for the nex t Op code Notice the micro program does not use Device End at all The micro program will accept Device End to get it off the line but does not use it because Chan nel End indicates the...

Page 286: ...racter in storage to be printed is an A the micro program sends a J to the 1443 N1 The 1443 N1 circuits fire the hammer when it 5 26 thinks there is a J in front of the hatrlTler Actually since the ty...

Page 287: ...Figure 5 16 Forms or Stacker Select Op Set Up K3 for a Control Command Check Address Validity Decode d modifier Form Command Set S6 for Command Immediate Iy B Reset Errors in K10 if Any Yes 1442 1443...

Page 288: ...Yes Stacker Sel Yes Unit Exception Unit Check Channel End Send Character Update UV Yes Yes B Field GMWM Set SO to 0 Yes SO On Stop in Error Tag On _Y e s Char Invalid Yes 1 11 1 Set Error in KIO Set S...

Page 289: ...0 2 3 4 5 6 R W X X X X 0 0 0 No Special Character 1442 Sense X X X X 0 0 Stacker Se I X X X X 0 0 Print Control After 0 X X 0 0 0 1443 Sense 0 0 X X 0 0 Forms Op 0 0 X X 0 0 13 39 Char Bar X X X X X...

Page 290: ...U2 TU3 TU3 Control Address Control Address 4 5 TU4 TU4 TU5 TU5 Control Address Control Address 6 7 TU6 TU6 Last Status Control Address from TCU 5 30 The TCU bit 0 on indicates an initial program load...

Page 291: ...If it Does Recycle the Program Yes Yes Yes Control Immediate Go to I O Common End Routine A egaI Response Go to Errar Stop Routine Figure 5 17 Tape Compatibility Part 1 of 2 Read GMWM Issue Test I o t...

Page 292: ...Figure 5 11 Tape Compatibility Part 2 of 2 5 32...

Page 293: ...tion displaced from the disk unit address such as disk 0 unit address is in MPX1 storage location 9 0 and 0 cylinder is in MPX1 storage location 9 1 As previously mentioned the disk address in AD thro...

Page 294: ...Figure 5 18 Auxiliary Storage Map for Disk Operation 5 34...

Page 295: ...the C E in his trouble analysis B9 Sense 0 byte BA Sense 1 byte BB Sense 2 byte BC Sense 3 byte BD File Address BE File Conmand BF Scan Condition Same bit significance as 2030 errors Current or last...

Page 296: ...t Cylinder _____ Y e s Test for Write Addr Op Generate Write Count and Data Command G4 1 SO 0 S2 0 OK A S7 1 No Generate Head Seek Command S2 1 SO 1 Test Status NG Normal Norma I Status End Operation...

Page 297: ...ty Kll CPU Sector Zero End Operation Write Address Op Yes Decode First Address t __ N o Test for Sector Count 000 Generate Search ID Ro O G O SO O S2 0 S O S5 0 Norma I Status Yes Generate Read Write...

Page 298: ...Seek to Alt Track 0 Seek to Dep Track 0 Search Id 0 Search Id Head Sw 0 Read 0 0 R W Count and Data 0 R W Data Record 0 AbnormaI Status Set Parity in KII CPU Yes Sector Count Zero End Operation COMMA...

Page 299: ...g from the 1050 in accordance with the chart in Figure 5 20 To illustrate this conversion if a 11000000 is sent to the 1050 it is first converted by the micro program to 11000111 to comply with the sp...

Page 300: ...I Op Is This Load Mode No No Is This A Reod Op Yes s This Alter or Displa A I te r _____________ J No Is This A Reod Op Is Attention On in TT Is It At Req 51 1 Yes Is Addr in Up No Figure 5 21 Compat...

Page 301: ...ay No G Yes Is 1050 Operationa I Is This Read Write Display Alter Read Write Is This A Read Op Is This An End No Alter Good Char No Quad 11 Yes C Is This A Good Char C a n ce l Cance I or Data Ck Data...

Page 302: ...o 6 Figure 5 21 5 42 Yes Set low Order Bits to 12 01 Encode High Order Bits to 4 No 01 Encode b Set R O Yes Yes Reset 57 0 Set S6 1 Reset T A Reg Set CR LF Compatibility Feature Console Inquiry Part 3...

Page 303: ...Is There A Data Check or Set Error Bit in K10 UCW Is Character GMWM Y es Is This Disp loy Mode Yes Is This Load Mode Yes 01 No Is Zone 1111 Yes Use Character As Is J Figure 5 21 Compatibility Feature...

Page 304: ...han Load No 1 _____ 10 _1_1 115 It Zones 0001 or 101 A Option 11 Is Low Byte 1100 No Encode 11000101 Encode 11010 110 Use Character As Is Start Tronsfer to 1051 Yes Figure 5 21 Compatibility Feature C...

Page 305: ...the thousands posi of a 1400 system address in binary Where 2 denotes the hundreds posi tion of a 1400 system address in decimal Where 3 denotes the tens position of a 1400 system address in decimal W...

Page 306: ...IFIER HALT BRANCH TAPE ERROR ON rPL 42 43 NO GMWM ALTER DISPLAY STOP INY CHNL STAT FOR BR ON SXER 42 ERR ON RD OR PCH 1402 READER E ROR STI SVI ON READ LOAD 5X OP IN DISC ON READ MPX PREMATURE END ON...

Page 307: ...mode can occur due to any of the following conditions Mode Switch on Invalid Op code Mode Switch on Halt Ope Mode Switch on Error stops Mode Switch on Invalid I O Ops Mode Switch on Console Ops Mode...

Page 308: ...interval timer feature the customer in effect can tell System 360 to stop working on Job 11 and start on Job 2 at 2 P M If the customer knows that Job 12 is usually completed in 15 minutes he might th...

Page 309: ...s the highest value it can contain is 15 1111 all positions set All positions of the C counter are set in 25 of a second Therefore the full value in the counter 15 multiplied by 5 gives the value 75 t...

Page 310: ...at it may again start counting the timed pulses A flow chart of the timer No Enter I Cycles interrupt routine is shown in Figure 5 24 50 CYCLE OPERATION The C counter is driven at a 50 cycle rate The...

Page 311: ...y 6 This is necessary because on a 50 cycle machine the counter is full every 3 seconds instead of every 25 seconds We still want the value 300 to be subtracted from the timer each second By using a m...

Page 312: ......

Page 313: ...6 1...

Page 314: ...2 4 0 3 1 0 0 6 1 0 1 5 0 9 1 5 2 4 2 05 1 4 1 9 3 05 3 65 900 300 2 350 2 990 2 840 2 100 2 700 o o 50 o o 300 600 2 210 2 210 50 310 350 280 320 575 575 400 575 575 o 50 50 180 350 480 320 320 100 8...

Page 315: ...ng this unit provision be made for lowering the lighting level to provide good image resolution 7 Powered from control unit 8 Minimum clearance for two 7340 units is 7 inches clearances should alterna...

Page 316: ...R SS EGI TE Ig 1 I I I I I MAIN STORAGE OA A REGISTER I ALU OUTPUT PU STATUS PU CHECKS I t I I II MATCH L STOR STOR AOR DATA B REGISTER I A R GISTER I 1050 A I g q I I I M m COMP 03 0 i CHNl CHNL MODE...

Page 317: ...UNf REGISTER I 4 2 I 2 I I 4 2 0 2 5 6 2 HANNEl NUMBE E OAT REGIS ER KEY I I 4 2 i I 4 2 I I 4 2 2 4 5 6 0 2 FLAGS TAGS CD CC Sll SKIP PC I STAT RV I IN IN IN m AOI CMND IV 0 0 0 OUT 0 Figure 6 2 UpP...

Page 318: ...ed I O unit is ready to transmit or receive data SEL OUT When this light is on the several I O units are being polled to determine which unit requested service ADDR OUT Indicates that the infor mation...

Page 319: ...2 I I 4 2 I 4 2 B REGISTER I A REGISTER i I I 4 2 I 4 2 I 4 2 11 4 2 2 6 2 6 7 Figure 6 3 Lower Indicator Panel 2 2 tus or address information sent from a control unit to the channel In addition to th...

Page 320: ...d process stop the instruction counter is displayed in 6 8 the B and A registers The current operation code is not displayed CPU STATUS These indicators Signal the actual operating status of the CPU a...

Page 321: ...ster In the ALU a dupli cate check is made COMPARE ADDRESS MAIN STORAGE ADDRESS DC I I 3 I Figure 6 4 Operator Panel OPERATOR PANEL FIGURE 6 4 SYS SYSTE INDICATOR This indicator is on whenever the cus...

Page 322: ...parity Th first four switches labeled A B C and D are used to set up the address for manual operations of the core stor age or to set up a compare address The switches labeled F G H and J are used to...

Page 323: ...ey on the con sole initiates the power off sequence in the CPU and the remainder of the system INTERRUPT KEY PreSSing the Interrupt Key gene rates a console interrupt which the system will recognize i...

Page 324: ...et key turns on the gate switches to WX stacking latch When the clock is re started and traps are allowed to take place according to their aSSigned priority the gate switches to WX stacking latch forc...

Page 325: ...check register as well as several machine check control latches to the no error state Check reset may occur with the CPU clock running or stopped Check reset key is located on logic page PA 111 Descr...

Page 326: ...e A register then both U and V are transferred to and displayed by the M and N registers Note this transfer of IJ or UV to MN during dis play takes place only if the allow write latch is off and the C...

Page 327: ...ElAYED ROARSTOP SARSTOP EARLY JI SARRESTART ROAR STOP ROAR RESTART ROAR ROAR RESTART WITHOUT RESET RESTART STOR BYPASS RATE INSTR PROCESS SINGLE STEP I CYCLE CHECK CONTROL DISABLE PROCESS STOP DIAGNO...

Page 328: ...reset and a fixed address is forced into the ROAR The resulting microprogram loads the contents of Switches F G H and J into the instruction counter Registers I and J and then starts an instruction c...

Page 329: ...in SAR Restart position except that no reset is initiated PROCESS POSITION This position is the position in which problem programs are processed Upon detection of a parity check with the switch in thi...

Page 330: ...________ _ J r T T T T l e 5S lOp CodeJL11L21B11Dl1B2JD21 l _______ _4 _ __ _ _J 13 1st 14 7 APPENDIX 3 ANSWERS TO REVIEW QUESTIONS 15 The Instruction Byte 16 RX 11 SS 18 The number of Bytes in the da...

Page 331: ...ove the area for new PSW s r T 6 ISystem1 IAMWPI Interruption 1 lMask 1 1 1Code I I 1 I I I l ______i ___i_ i __ J o 7 12 1 IS 16 31 r T T T I I I C IProg lInstructionl I L J C IMask IAddress I l ___i...

Page 332: ...rage Keys 2 Protection Key 3 A p ivileged instruction called Set Storage Rey 4 1 A privileged instruction called Load PSW 2 An Interrupt 5 a Modify type main storage cycles 6 a All blocks storage prot...

Page 333: ...register 0 and 1 bits The emitter of the decode switch is conditioned by the M register 3 4 and 5 bits 5 Coincidence of current flow in an X band and Y line the flipping of a core strobing of the pul...

Page 334: ...of the S register is zero There is no carryout as a result of the addition to set 53 D D C DC A source 0001 0001 B source 0001 0001 D register 0010 0010 Position 7 of the S register is set to zero 0 S...

Page 335: ...th no carry insert A source 1000 1000 B source 1000 1000 D register 0001 0000 with a carryout Because of the C to the right of the arrow the carry out sets position 3 of the S register Even though S7...

Page 336: ...added to itself There is no carry insert as S3 is a zero No carryout results The resul tant data is 0000 1000 in the R register Core address XXXX is read UV MN MS S6 is set to a one lS6 but not befor...

Page 337: ...check is further controlled by the CPU Check switch ANSWERS ROS TIMINGS 1 e d b a c 2 The SALs are set by the ROS word as specified by the address in ROAR The control register latches con tain the da...

Page 338: ...y mode and possibly destroy a con trol byte in local storage 7 The 2030 comes to a program halt with a coded byte in the R register showing an invalid stacker select command because a stacker select c...

Page 339: ...S Reg to Zero Except S3 Lacal Storage Clear 01 LS Bytes CIeared SI S2 00 SI S2 01 SI S2 10 MPX o I 2 No 00 Set T Reg to 01 Set XH XL Latches from SI 52 Figure 6 8 System Reset 6 28 In This Order K9 1...

Page 340: ...ags Wait Yes Build the UCW Wait for Request in From Device Request In Yes Load IPL Unit Address from Switches into 0003 Load IPL Channel Address from Switch G into 0002 Load New IPL PSW from 0000 0007...

Page 341: ...10 6 30 Floating Poinrt _ Fixed Point Start 01 RX 10 R5 11 55 Store R Reg Data in 1st Operand Read From 2nd Operand Decrement T Register Address Ignore Overflow Micro Program Program Interrupt Regener...

Page 342: ...Update J Reg All ow Carryout to Set 1 53 Update I Reg if 53 is I On I Reset 53 STOP I Figure 6 11 Manual Traps to Display or Alter MANUAL TRAPS to DISPLAY or ALTER PROCEDURE 1 System Reset 2 Store De...

Page 343: ...Destination is H to Allow Traps Turn On As Many SALs as Possible Gate UV to WX Take MPX Trap Loop Test MPX Trap Hardware Control ROS SCAN Position Yes Update U Reg if Carryout of V Reg Update Yes PROC...

Page 344: ...LU Add Operation 2 16 Console Inquiry 1050 5 39 ALU AND Operation 2 17 Core Control CU 3 20 ALU and Source Registers 1 33 Core Planes 2 37 ALU OR Operation 2 18 Core Storage 1 33 Allow Low Priority 3...

Page 345: ...Control 2 62 Memory CPU Interface 2 53 Memory Sense Bit Lines 2 54 Memory Wrap 2 63 7 2 Meter P nel 6 17 Micro Program Examples 3 23 Micro Programming Introduction Multiplexor Channels 1 20 Multiprogr...

Page 346: ...ntrol CM CU Storage Control Mnemonics Storage Keys 1 69 Storage Protection Store Bit Lines Store Key 6 13 Supervisor 1 49 1 69 2 54 Supervisor Call Instruction System Indicator 6 9 System Concepts 1 5...

Page 347: ...l 0 Which of the following terms best describes your job Customer Engineer 0 Instructor 0 Sales Representative 0 Systems Engineer 0 Trainee 0 Field Stock Personnel 0 Manufacturing Engineering 0 Manufa...

Page 348: ...ublications Dept 171 Fold l rn POSTAGE WILL BE PAID BY IBM Corporation P O Box 6 Endicott N Y 13764 International Business Machines Corporation Data Processing Division 112 East Post Road White Plains...

Page 349: ...s supplement Form 825 0030 pertains to the 1 5 microsecond core storage unit for the IBM 2030 Processing Unit This mater ial should be inserted after the 2 0 microsecond storage unit write up in the I...

Page 350: ...225 3360 0 International Business Mechines Corporation Field Engineering Division 112 East Post Road White Plains N Y 10601...

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