IBM 1 GB Microdrive Storage Card Manual Download Page 129

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Summary of Contents for 1 GB Microdrive Storage Card

Page 1: ...Series 1 GA34 0033 3 File No S1 01 IBM Series 1 User s Attachment Manual...

Page 2: ...GA34 0033 3 File No 1 01 IBM Series 1 User s Attachment Manual...

Page 3: ...ces which are not announced in your country Such references or information must not be construed to mean that IBM intends to announce such IBM products programming or services in your country Publicat...

Page 4: ...and initial program load IPL Chapter 3 Timer Feature describes the timer feature including signal lines interrupts electrical characteristics and physical characteristics Chapter 4 Teletypewriter Ada...

Page 5: ...iv GA34 0033...

Page 6: ...siderations 3 7 Application Sequences 3 7 Interval Timer 3 7 Pulse Counter 3 8 Contents Pulse Duration Counter 3 8 Timer Feature Operational Characteristics 3 8 Interrupts 3 8 Interrupt Presentation 3...

Page 7: ...6 6 Halt or MCHK 6 7 System Reset 6 7 Power On Reset 6 7 Diagnostic Mode and Diagnostic Mode Modifier 6 7 DPC Adapter Operational Characteristics 6 8 Output Sequence 6 8 Input Sequence 6 9 Interrupt S...

Page 8: ...ribed in subsequent sections of this chapter rsT4 Oo 4 ooo FF User s time l Users or count instrument s User S dependen device s device i Signals __ To yO Integrated Timer digital I O Teletypewriter f...

Page 9: ...that plugs into the backpanel of an IBM Series 1 processor or the IBM 4959 I O Expansion Unit The top edge of the IBM printedcircuit card has an industry standard connector that accepts the user s I O...

Page 10: ...face circuits are TTL compatible The adapteris designed to perform direct program control functions only The feature card can be configured to accommodate 4 8 or 16 I O device addresses The adapter al...

Page 11: ...1 4 GA34 0033...

Page 12: ...ilitate device service The device interrupt level is assignable by the program and the device interrupt capability can be masked under program control e Initial program load IPL operations a record co...

Page 13: ...nnel repower feature this feature is a logic card that repowers and isolates the channel signal lines This card can be installed in any I O socket as the last series element on the channel to allow co...

Page 14: ...e return Service gate Service gate return Condition code in bus Cycle input indicator Cycle byte indicator Status bus Data strobe Initiate IPL IPL Halt or MCHK machine check System reset Poweron reset...

Page 15: ...return Condition code in bus 3 Data strobe s Halt or MCHK ae System reset p Poweron reset esp Poll group signal lines Poll Note 3 _ Poll prime Note 3 _ _ p Poll propagate Note 3 en Notes 1 Address bus...

Page 16: ...subset in conjunction with the basic subset supports DPC devices that are interrupting sources The I O signal lines in the interrupt subset are shown in Figure 2 4 Service group signal lines Signal na...

Page 17: ...al IPL subset are shown in Figure 2 5 Service group signal lines Signal Number name Direction of lines Address bus bits 0 15 Note 1 Ge 6 Cycle input indicator Cycle byte indicator S Status bus mente I...

Page 18: ...the byte is transferred from bits 24 31 of the IDCB bits 16 23 should all be 0 s DPC write sequences are specified by address bus bit 1 IDCB bit 1 equal to a logical 1 Parity isalways maintained for...

Page 19: ...to the storage address being presented If the storage address is even data bus bits 0 7 are driven by the device and correspond to the byte to be placed at the storage address If the storage address i...

Page 20: ...n bus corresponds to the condition code indicators in the level status register LSR as follows Condition LSR codein bit indicator 0 Even 1 Carry 2 Overflow On cycle steal service sequences the conditi...

Page 21: ...l to accomplish this selection Only one device can be configured as a primary IPL source and only one device can be configured as an alternate IPL source at any one time on the I O channel attached to...

Page 22: ...selection block poll propagation and clear any status states requests registers and interface control logic with the following exceptions e Residual address e DI DO AI and AOsettings e Timer values e...

Page 23: ...ag and holdsit valid until a poll return or burst return is received The significance of the poll identifier bits is as follows poll ID bits are shown using logical representation for active inactive...

Page 24: ...erial nature of the poll mechanism the relative physical position of I O attachments on the channel is a major determinant of the priority for servicing contending cycle steal requests and for servici...

Page 25: ...t a poll capture for an interrupt poll or for a non burst cycle steal service poll has taken place It is not used to signify that a burst transfer is required Burst Return This is an inbound tag sent...

Page 26: ...active Poll sequence poll group initiated by either an interrupt request or a cycle steal request The poll is either propagated or captured by an I O device If the poll is captured the I O device retu...

Page 27: ...steal request is generated by I O devices on the channelitself 2 A processor DPC request to the service group which is done inline with the execution of an Operate I O instruction Although the poll g...

Page 28: ...signer needs to adhere to or be aware of when designing an I O attachment for the I O channel The designer has no control over but must be aware of channel times CT The designer does have contro of th...

Page 29: ...ce G SA State of Burst return drop channel A I anne B Wait SA G for G Gate enables sequences service Cycle steal SA I Inhibit prevents sequences from starting I burst sequences SA Sequence active show...

Page 30: ...the device interface Address gate is deskewed and activated on the channel The deskew time CT1 between the last valid signal of address bus and data bus on write sequences and the activation of addres...

Page 31: ...read sequences must be deactivated prior to the deactivation of address gate return The permissible delay T5 from the deactivation of both address gate and data strobe to the deactivation of address...

Page 32: ...8 T attachment controlled times 0 T1 T2 3 us LVS last valid signal occurring in time of a group of 0 T4 TS 3 us signals being activated on the channel The group 200 ns CT1 is shown linked by short dot...

Page 33: ...t As denoted by the relationship of CT2 and CT3 in Figure 2 9 data strobe may extend beyondthe active envelope of service gate by 100 nanoseconds maximum but the overlap of data strobe and service gat...

Page 34: ...T1 T2 3 us LVS last valid signal occurring in time of a group ofsignals 0 T3 T4 3 us being activated on the channel The group is shown 100 ns CT1 linked by short dotted lines on the timing diagram 200...

Page 35: ...activated by the channel Data strobe is activated The duration of data strobe CT3 is 200 nanoseconds minimum as seen at the device interface As denoted by the relationship of CT1 and CT2 in Figure 2...

Page 36: ...l times snINgS T attachment controlled times 0 T1 T2 3 us LVS last valid signal occurring in time of a group of 0 T3 T4 3 us signals being activated on the channel The group 100 ns CT1 is shownlinked...

Page 37: ...has control the total duration of the cycle steal sequence is within the channel time out under normal operation The sequence described here applies to cycle steal servicing in burst mode also however...

Page 38: ...t mode the dummy transfer must appear as the last transfer of the burst mode Because the channel is unaware that these are dummytransfers no device held parameters are to be updated norare any status...

Page 39: ...rface The processor channelinterface will deactivate the poll when it sees the active poll return tag For interrupt service sequences the activation of poll return causes the normal service gate seque...

Page 40: ...or the last transfer T5 This allows time for the processor to start a new polling sequence and to service a different request if one is present In both sequences 1 with poll return and 2 with burst re...

Page 41: ...CT1 Poll Poll return Service gate AY CT4 a l CTS CT2 va Ye TS 7 AN CT3 Service gate return Cle cycle steal request in or request in bus of capturing device is lagging poll ID and did not cause poll I...

Page 42: ...oe Poll identifier Poll CT1 CT4 Burst return T3 iY TS Service sequences CT3 Last transfer service gate return n w cycle steal request in or request in bus of capturing device is lagging poll ID and di...

Page 43: ...s may be present Cycle stealrequestinor Tl request in bus Poll identifier CT1 Poll T2 Poll propagate n Timings T1 100 ns T2 100 ns CT1 180 ns Figure 2 13 Poll propagate timing diagram Nw Key CT channe...

Page 44: ...se the leading edge transition of the first system reset This is because thefirst system reset could also lead the initiate IPL and status bus at the device interface The first system reset is deactiv...

Page 45: ...her respects When the interrupt is accepted the device presents the device end interrupt condition code If a system reset occurs after the device has enabled cycle steal requests and transfers the dev...

Page 46: ...ns T2 0 T3 0 T4 0 CT1 4 8 us CT2 0 CT3 200 ns CT4 500 us Figure 2 14 Processor initiated IPL sequence timing diagram Normal cycle steal usage CT3 am aeSC USE q x CT1 DS Crs T3 T4 Key CT channel times...

Page 47: ...IPL tag is activated This system reset is activated for a duration CT1 of 4 8 microseconds minimum and is analogous to the second system reset of the processor initiated IPL sequence it has a similar...

Page 48: ...her respects When the interrupt is accepted the device presents the device end interrupt condition code Initial Sequence to Normal End AsynchronousI O activity i NA Host IPL command IPL CT2 CT1 System...

Page 49: ...essentially a restatement that the device may activate the IPL tag only once for each host IPL command successfully executed After execution of the host IPL commandfor retry the device must reactivat...

Page 50: ...resented should not be taken in the context of a total design when other considerations would result in added function to a logic area These logic diagrams are intended only to aid in explanation of c...

Page 51: ...ate can occur randomly outside of a DPC sequence when address bus bit 16 DPC sequence is not active This is because of the presence of main storage physically attached to the channel for the 4952 and...

Page 52: ...m other logic on same device G _ Inverter Address gate envelope __ Address TH AND p _ gate AND OR Delay inverter return ___ Inverter Co Service e gate i return Address L e Service gate Fig 2 18 AND en...

Page 53: ...election and degating of return tags with any of the three synchronous channel directed resets Note that Device Reset which is a DPC command is not included in these resets because its action is diffe...

Page 54: ...uest Poll ID bit 0 Poll ID bit 1 Poll ID bit 2 Poll ID bit 3 Poll ID bit 4 request Fig 2 18 Clock interrupt request Fig 2 18 Inverter Inverter Inverter Request in bus bits 0O 15 4 to 16 decode Gate In...

Page 55: ...oll tag is activated it holds the value of the poll decision latch and gates the appropriate poll propagate or poll return tag If a decision to capture has been made the poll capture latch is also set...

Page 56: ...vel compare Fig 2 17 Poll I Poll prime 1 AND AND inverter Poll capture Set CaS Q Flip latch OR Reset Q Channelresets e Fig 2 16 Service gate return Fig 2 16 Service gate capture Fig 2 16 7 O O device...

Page 57: ...ch is set and the IPL tag is activated However before the flip latch changes state due to delays a logical O is set into the enable IPL D trigger Therefore IPL cycle steal requests and transfers are n...

Page 58: ...latch OR Reset Alternate Inverter AND inverter Initiate IPL AND inverter Enable IPL System reset Data Inverter Clock Power on reset D trigger IPL complete ad OR Reset Key 1 device interface with chann...

Page 59: ...y this signal If I O processing is taking place at the time of the power loss an error may occur Indications of the errorare e An unexpected condition code to an Operate I O instruction e An TJ O inte...

Page 60: ...Cc I O cable and connector showing power on reset POR __ Outboard POR through cable to channel repower card 5 Channel repowercard POR power on reset BBU IBM 4999 Battery Backup Unit optional Figure 2...

Page 61: ...dentifier bits and status bus bits these levels correspond to activation of tags and requests The quiescent levels are defined for the following conditions e The processor and I O deviceare in the sta...

Page 62: ...9 G10 G12 JO2 J04 JO5 J06 J07 JO9 J10 Jil J12 Proc essor driver receiver type C A C B C B C B C B C B C B C B C B C B C B C B C B C B C B C B C D C D C E C E C E C E C E C E Note 2 C E Note 2 C E C C...

Page 63: ...09 U10 Vil U12 U13 POS P06 J13 G13 M03 P02 M05 Proc essor driver receiver type C D C D C D C E C D C D Unused Unused C D C D C D Note 4 C E Note 5 C E C E C E C E Unused Unused Unused Unused Unused Un...

Page 64: ...Driver active collector 7 Output input Type C E Receiver Output 5 V 10 0 39 kQ 2 5 Input 0 6 kQ 2 5 Figure 2 22 I O channel driver receiver classification Driver open collector Driver open collector 5...

Page 65: ...0 0 V 0 0 V 4952 4953 Driver 5 5 V 2 4 V 0 6 V 0 0 V 4952 4953 Receiver 5 5 V 2 0 V 0 8 V 0 0 V MPUL most positive up level LPUL least positive up level MPDL most positive down level LPDL least posit...

Page 66: ...n of any of the driver receiver specifications constitutes a violation of the unit load requirement Proper operation of the channel under these circumstances would then be dependent on the particular...

Page 67: ...0 Data busbit 1 Data bus bit 2 Data bus bit 3 Data busbit 4 Data busbit 5 Data busbit 6 Data bus bit 7 Data bus bit PO Data busbit 8 Data bus bit 9 Data busbit 10 Data bus bit 11 Data bus bit 12 Data...

Page 68: ...est in bus bit 11 Request in bus bit 12 Request in bus bit 13 Request in bus bit 14 Request in bus bit 15 Service gate Service gate return Status bus bit 0 Status bus bit 1 Status bus bit 2 Status bus...

Page 69: ...2 25 Driver open l collector Receiver conditioned _ 7 Receiver T Driver open Ny a l _ collector Driver active we collector P 5 V 10 2k 10 Receiver NS Lae Unit load driver receiver classification Open...

Page 70: ...High level input Low level input conditioned inactive Low level input conditioned active Test condition volts at node 2 4 0 45 Note 1 2 4 0 2 Note 2 0 4 Note 3 0 2 4 0 45 Note 1 2 4 0 2 Note 2 0 4 No...

Page 71: ...For example two half unit load receivers should not be used in lieu of a one unit load receiver Test conditions assumethat the supply voltage Voc is at maximum or minimum value to produce worst case c...

Page 72: ...L 0 0 V 0 0 V Receiver switching characteristics Levels Input MPUL 5 5 V LPUL 2 0 V MPDL 0 8 V LPDL 0 0 V Key MPUL most positive up level LPUL least positive up level MPDL most positive down level LPD...

Page 73: ...s driver thus making V V In this state current I is greater than I and the receiver does not present a current load as large as it normally would to the bus Therefore the receiveris said to be conditi...

Page 74: ...y Va Conditioned receiver Vy oo Signal Conditi Conditioning _T conditioning oneon signal driver receivers active Pn ep meg 7 1 Current sharing with receiver inactive V at low level b Figure 2 27 Recei...

Page 75: ...oads channel repower 21 where No of TTL unit loads 8 Given a unit of available locations for case 1 for all models of 4952 and 4953 No of general loads 2 No of TTL unit loads channel repower 14 where...

Page 76: ...wer from the I O socket Otherwise this may preclude the capability of the device to execute a processor initiated IPL in auto IPL mode For attachments to devices that are capable of executing processo...

Page 77: ...g method can be used Assume that for substrate biasing purposes V 5 0 V and V t8 5 V if V is more positive than 3 5 V V must not remain above 5 0 V for more than 500 ms Although no true sequencing occ...

Page 78: ...Sa D10 D10 Address bus bit 16 sooner D11 D1i1 Address gate os M08 B08 Address gate return Gmemme V 9 B09 Burst return Gee P14 D04 Condition code in bitO Di12 D1i2 Condition codein bit 1 G e 13 D13 Co...

Page 79: ...est in bus bit 8 _ U05 DO5 Request in bus bit 9 _ _ s sdOWU06 D06 Request in bus bit 10 07 D07 Request in bus bit 11 U09 DO09 Request in bus bit 12 _ Ul0 D10 Request in bus bit 13 _ UI D11 Request in...

Page 80: ...nd Gnd D08 M06 Res Gnd Gnd B06 M11 Poll propagate Gnd Gnd B11 P03 5 V 5 V NC D03 P08 Gnd Gnd Gnd D08 S06 Res Gnd Gnd B06 S11 Res Gnd Gnd B11 U03 5 V 5 V NC D03 U08 Gnd Gnd Gnd D08 Key Gnd ground NC no...

Page 81: ...ots is 15 88 mm 0 625 in The dimensions of a standard IBM card are 178 mm by 229 mm 7 in by 9 in The clearance on the wiring side left side as viewed from the front of the card file is 5 6 mm 0 220 in...

Page 82: ...E OOO00 Card column Card row OS OSO 2 CO eLeO 3 Subcolumn Se Subrow OBO WS 4 O 06O S O 0OBO 6 OSB0BO 7 O 0 0 8 A 2B 0 3 OS808O 9 Addressing scheme OS08BO 10 OGOSBO 11 OS 0SBO 12 Weer Jer Johann ooooo...

Page 83: ...socket of 495 2B 12 B06 4953 Model Bor D or 4955 boards Componentside Contact assignments are shown as viewed whenfacing the endofthe card Standard IBM printed circuit card Shroud 24 pin connectors 24...

Page 84: ...n I O card files The processor I O channelis received at the bottom of the channel repower feature card and the redriven signal lines are available at four top card connectors Figure 2 32 In normal co...

Page 85: ...ile is required to sink at 0 45 V most positive down level when powered downoractively signalling power on reset The pin assignments for the repower feature are listed in Figure 2 33 The top card conn...

Page 86: ...ta bus bit 2 Data busbit 3 Data bus bit 4 Data bus bit 5 Data bus bit 6 Data busbit 7 Data bus bit PO Data busbit 8 Data bus bit 9 Data bus bit 10 Data bus bit 11 Data bus bit 12 Data bus bit 13 Data...

Page 87: ...Request in bus bit 7 _ U04 Z04 Request in bus bit 8 __ U05 Z05 Request in bus bit 9 _ U06 Z06 Request in bus bit 10 _ U07 Z07 Request in bus bit 11 _ U09 Z09 Request in bus bit 12 _ _ U10 Z10 Request...

Page 88: ...cifications described in Processor I O Channel Electrical Characteristics in this chapter The poll and poll prime signals must be propagated as described in Poll Sequence Description in this chapter A...

Page 89: ...ic voltages should be used less than 24 volts dc to avoid safety problems The customeris responsible to evaluate the exposure to the vibrational forces or translational forces caused by any customer c...

Page 90: ...ring side 146 0 25 mm 5 75 0 01 in 8 9 1 3 mm ae 0 35 0 05 in _ Wiring A Maximum 4 83 mm 183 0 13 mm 7 21 0 005 in 1 52 0 15 mm 0 190 in ra 0 060 0 006 in Component side fi 8 9mm Maximum 0 350 in oan...

Page 91: ...busbit 1 Data bus bit 2 Data busbit 3 Data busbit 4 Data bus bit 5 Data busbit 6 Data busbit 7 Data bus bit PO Data bus bit 8 Data busbit 9 Data bus bit 10 Data busbit 11 Data busbit 12 Data busbit 1...

Page 92: ...n bus bit 13 Request in bus bit 14 Request in bus bit 15 Service gate Service gate return Status bus bit 0 Status bus bit 1 Status bus bit 2 Status bus bit 3 System reset Note Customercard socket pin...

Page 93: ...2 82 GA34 0033...

Page 94: ...ernal time base is provided by the user and must be equal to or greater than 20 microseconds whenthe inputis filtered or 1 microsecond when notfiltered The timer value is decremented with the selected...

Page 95: ...unstate External gate enable User signal ground Frame ground Figure 3 1 Block diagram of timer feature Address jumpers 7 Drivers and receivers Timer 0 Timer 1 Timer feature I O channel Receivers a Add...

Page 96: ...d to denote a DPC device command andto gate receivers active e Request in bus 16 bits wide driving only Relationship to Other Features The timer card is plugged into any I O position of an IBM 4955 or...

Page 97: ...external gate DI TTL Filtered jumpers TTL jumpers 4949 to V 5 V 1502 One TTL load 3309 400 pf Timer X signal ground 5 V 7502 Timer X external gate enable or __ __ _ _ _ Timer X run state DO oN Oo Fra...

Page 98: ...ow of pins o O O eo O O o O oO C O O Oo oO Oo GO oO C O oO O Timer 0 digital input illustrates jumpers for TTL input oa Timer 1 digital input illustrates jumpers for filtered TTL input illustrates jum...

Page 99: ...ected to the timer X customer clock input The timer mode controls should be set to arm the external gate and to select the time base desired The measure of the pulse duration is a function of 1 the in...

Page 100: ...as active Timer X external gate is the input for the user supplied gate signal It is only effective when the external gate control is enabled This input uses the down level and not the downtransition...

Page 101: ...th of the expected pulse Set timer mode for external gate control bit 15 of the IDCB data word set to 1 Start timer Run state to customer interface becomesactive External gate active starts the timer...

Page 102: ...ate or the activation of external gate This uncertainty must be taken into account only once each time a timeris started There is also an uncertainty associated with the value of the timers when measu...

Page 103: ...driver If an active collector driver is used to drive the input points the maximum repetition rate increases substantially to approach 500 kHz This is determined by the charging time of the filter sho...

Page 104: ...AO7 A08 BOI BO2 BO3 B04 BO5 B06 BO7 BO8 Signal Timer 0 clock Timer 0 external gate Timer 0 run state Timer O external gate enable Timer O customer signal ground Not used Not used Frame ground strap N...

Page 105: ...ard connector must be via twisted pair wires The signal ground wires from all sources associated with a particular timer must be soldered together at the connector card and brought into timer O or tim...

Page 106: ...for transmit Operationis full duplex that is data may be transmitted and received concurrently The input options offered are Isolated contact sense Open circuit mark logical 1 closed circuit mark Non...

Page 107: ...rent space Frame ground Key TTL transistor transistor logic Receivers and drivers Teletypewriter adapter feature A EIA Electronic Industries Association SSS solid state switch IPL initial program load...

Page 108: ...all 0 characters followed by one unpredictable character The data exchange over the interface is not checked for parity or device dependent control characters The adapter can be configured to perform...

Page 109: ...y I O position that has 5 volts available at the card slot on the 4955 or 4953 card files or the I O expansion unit card file Refer to the prerequisite publications listed in the Preface of this manua...

Page 110: ...card The output signals to the device are nonisolated solid state switches current drivers and EIA drivers The output options are as follows Type name Data mark convention Current driver Current out m...

Page 111: ...interface and an EIA voltage level interface as switch selectable options that are included in the basic price of the device Some devices are manufactured with 1 only the EIA interface 2 only the cur...

Page 112: ...ted current loops A separate power supply and current limiting resistor must be placed in the transmit loop and the receive loop Refer to Teletypewriter Device Information in this chapter for connecti...

Page 113: ...oop interface AOl 180 Q 360 2 Isolated _ T contact __ sense Receiver a Optical l A03 O o e isolation Nonisolated contact a _ sense Bol O O 5 V 455 2 150 2 B04 chev TTL O Receiver 300 2 A04 EIA C O Rec...

Page 114: ...ial I O device Top card connector pin AQT SSS closed data mark or TTL minus data mark SSS solid state switch O BO SSS open data mark or TTL plus data mark A08 CO SSS TTL write control BO8 O SSS TTL re...

Page 115: ...purchase OEM powersupplies to drive current loops Simple cabling from card to device Most OEM devices support EIA interface Simple cabling from card to device High noise immunity Customer does not hav...

Page 116: ...ured for full duplex operation No error checking is done on transmitted or received data The teletypewriter adapter is code transparent All 256 combinations of 8 bit characters can be transmitted or r...

Page 117: ...signal the completion of the current character transmission This interrupt must be serviced and another transmit operation initiated by the end of the second stop bit time if maximum transmission rate...

Page 118: ...ters are lost e An Overrun Receive Operation This is a receive operation that results in the posting of an exception overrun interrupt A second character was received and the leading edge of the first...

Page 119: ...rupt presentation the exception code takes precedence over the device end code at interrupt presentation time if both interrupts have been posted The presentation and acceptance of the exception code...

Page 120: ...ted as a part of the interrupt service program The receive buffer register is then free to be used to hold another character If the receive control logic attempts to transfer a second received charact...

Page 121: ...ng that is a new transmit operation is not initiated in less than time T from the posting of the device end interrupt The adapter however is write busy upon successful execution of the Write command I...

Page 122: ...he first stop bit time of the next character to prevent overrun T is equal to the maximum permissible time the processor can delay in performing an interrupt accept and read after an attention interru...

Page 123: ...1RO milliseconds for one stop bit for two stop bits 9600 0 936 1 01 1 12 4800 1 87 2 05 2 26 2400 3 74 4 14 4 55 1200 7 49 8 30 9 14 600 14 98 16 6 18 3 300 29 96 33 3 36 6 Key 200 44 94 49 9 54 9 A e...

Page 124: ...t stop bit time of another character is detected by the attachment before the IA R occurs to clear the interrupt and read the first character line 7 is an example of this Even though IA R1 did not occ...

Page 125: ...changethe state of the read control output onlyif the Operate I O IO condition code response to the commandis condition code 7 command accepted A Read command cannot change the state of the read contr...

Page 126: ...Write command cannot change the state of the write control output if the IO condition code response to the commandis condition code O device not attached 1 write busy 3 commandreject or 5 interface da...

Page 127: ...32 C voltage level Input options are selected e By connecting to the appropriate pins and e By a 3 bit coded jumper pin selection on the card See Jumper Selections in this section for a detailed expla...

Page 128: ...for control and EIA RS232 C voltage level The outputs are selected by utilizing the appropriate top card connector pins All outputs are driven in parallel jumpering on the card is not necessary for s...

Page 129: ...ates jumper for TTL minus data mark schection LSB illustrates jumpers for 1200 bits per second MSB a Bit rate oo selection Oo Oo illustrates jumper for device address hex 80 LSB O O MSB MSHD o 9 O O I...

Page 130: ...data mark 0 1 1 Internal True data out 1 0 O Contact sense Open data mark 1 0 1 TTL Plus data mark 1 1 O EIA Plus data mark 1 1 1 Internal True data out The contact sense input closed data mark is the...

Page 131: ...he receive inputs is 24 volts 10 Whenthe driving source switch is closed a current flows out of the receive plus input and back into the receive minus input The current flow is I 18 5 V 910 R where I...

Page 132: ...witch can withstand is 52 8 volts With this voltage the maximum current through the switch is 500 uA orless In the closed or on state the maximum permissible current through the switch is 100 mA The v...

Page 133: ...es not require any external power supplies All power required by the teletypewriter adapter is obtained from the I O card file in which the card is inserted The only exception to this is when the user...

Page 134: ...or equivalent Figure 4 9 shows the cable connections for the teletypewriter adapter card The following table is a list of the signals and their pin assignments Pm Signal Pin Signal Al Isolated receive...

Page 135: ...ey on the processor console Cable Connection to the Teletypewriter Adapter EIA 4 30 GA34 0033 The tables in the following sections indicate how pins on the top card connector should be connected to pi...

Page 136: ...Signal ground transmit Receive A7 SSS closed data mark Receive Two external power supplies are required for the current loop interface one for the transmit loop and one for the receive loop Both power...

Page 137: ...the receive input and 24 volts across the transmit output of the attached device Teletype Models ASR 33 ASR 35 and KSR 33 require 24 volts across their transmit outputs for reliable operation For devi...

Page 138: ...e card connector to the CAPis built in and the teletypewriter customer access cable feature 2059 provides the cable from the CAP to the device If the CAP feature is not ordered the teletypewriter cabl...

Page 139: ...4 34 GA34 0033...

Page 140: ...digital input process interrupt Each group of digital input has e User input points 16 that sense the value of nonisolated voltage input e One 16 position DI data register for reading unlatched data O...

Page 141: ...ated digital I O feature Group 0 DI data reg Channel Ext sync interrupt PI data reg Process interrupt Group 1 pee cme ee een ee eee eee S77 DI data reg Ext sync interrupt PI data reg Process interrupt...

Page 142: ...l lines an external sync input line and a ready output line A DI groupis set to external sync mode by execution of the Arm DI External Sync command When external sync mode is armed and the system is r...

Page 143: ...a Write DO commandis executed in external sync mode and the data on the DO output is good an active level on the external sync input line causes the ready line to become active The user signifies rece...

Page 144: ...an interrupt to the channel indicating that the external equipment has received the data 6 After the interrupt has been serviced another Write DO commandis performed to set up the group for the next d...

Page 145: ...terrupt is serviced a Read PI With Reset commandreads the latching register and resetsit allowing a new interrupt to be generated on the next transition of any input point of that group If the interru...

Page 146: ...s nonisolated andis designed to operate with TTL compatible voltage levels Voltage inputs up to 24 volts may be used with this feature Figure 5 4 shows a representative input point For voltages above...

Page 147: ...during this time result in unpredictable data in the DI register Digital Output DO Characteristics 5 8 GA34 0033 Each digital output point is a nonisolated solid state current sink point as represente...

Page 148: ...rce minimum On state 0 8 Vdc maximum Current input On state 100 mA maximum per point with user source Off state 500 wa maximum per point at 52 8 Vdc user source Digital outputs meet and maintain speci...

Page 149: ...i A side Group J1 B side Group 20 DI 0 0 DI 1 0 19 DI 2 0 DI 3 0 18 DI 4 0 DI 5 0 17 Common DI 6 0 16 Common DI 7 0 15 Common DI 8 0 14 Common DI 9 0 13 Common DI 10 0 12 Common DI 11 0 11 Common DI 1...

Page 150: ...eady 2 Ready 1 Ready Figure 5 9 Group NO Group 2 2 2 ow mn J2 B side Group DI 10 DI 12 DI 14 DI 15 Ext sync in Ext sync in Ext sync in Ext sync in Spare Spare Spare DO 0 DO 1 DO 2 DO 3 DO 4 DO 5 DO 6...

Page 151: ...ss panel CAP feature Figure 5 11 showsthe relationship between the integrated digital I O feature and the customer access panel feature Figures 5 12 through 5 15 show the connections for both the top...

Page 152: ...Frame J1B19 JI1A16 Frame JIA18 J1A7 Frame J1B18 J1A15 Frame J1B17 Chassis Frame J1B16 J1A13 Frame J2B16 J2A15 Frame CAP pin D3 B2 F8 C9 D2 Abo F7 C8 D1 B6 F6 C7 F4 F5 F3 C4 L7 H8 Name 8 8 Shield 9 9...

Page 153: ...is Frame CAP pin E2 B3 D9 C5 D8 B7 D6 B5 D5 A2 Bl AS A9 A8 D4 B9 L6 J9 Name 8 Q Shield 9 9 Shield 10 10 Shield 11 l1 Shield 12 12 Shield 134 13 Shield 144 14 Shield 15 15 Shield Ready Ready Shield TCC...

Page 154: ...6 G5 K5 H7 K4 H6 K3 K2 H2 Kl H1 G3 G7 L5 Jl Name 8 Q Shield 9 Q Shield 10 10 Shield 11 11 Shield 12 12 Shield 13 13 Shield 144 14 Shield 15 15 Shield Ready Ready Shield TCC pin J2A2 J2A11 Frame J2B1 J...

Page 155: ...Frame J2B13 J2A12 Frame CAP pin T3 T9 T2 S5 TI V2 S9 V3 S8 S2 S7 N8 S6 Vi S4 T8 L4 H5 Name 8 Shield 94 Q Shield 10 10 Shield 11 11 Shield 12 12 Shield 13 13 Shield 144 14 Shield 15 15 Shield Ready Rea...

Page 156: ...umperable LSB 15 Not jumperable La y YvyyY nN O expandedforclarity _ J2 oe Integrated digital I O card aS a J3 User s connectors Key MSB most significant bit LSB least significant bit MSHD most signif...

Page 157: ...ched to these common pins The reference lines must be doubled up because there are not enough commons to supply one pin per signal pair After all the reference halves are connected there should be at...

Page 158: ...y is not generated by an I O device on the input data bus internal circuitry on the feature card generates odd parity All the devices attached to the DPC adapter share a commonpreparefield interrupt l...

Page 159: ...e card provides a convenient means of attaching customer equipmentto the processor I O channel Block diagram of the customer direct program control adapter feature OO To facilitate attachment of vario...

Page 160: ...attached devices Signal Direction Number name adapter device of lines I O active cece 1 Function bits a 3 Modifier bits ea 4 Device address TS 4 Data bus out ae 18 16 Interrupt service active NN 1 Str...

Page 161: ...performed Certain modifier values when used with read status or write control have system functions and must be implemented byall attached devices These commandsare defined as follows Function Modifie...

Page 162: ...esponse tag measured at the output of the DPC adapter card Strobe Strobe is an outbound line to the I O device presently being selected device address equivalent to the preassigned address of an I O d...

Page 163: ...he device receives Device Reset halt or MCHK system reset or power onreset Condition code in is a three bit binary encoded bus used by an I O device to pass status information to the processor during...

Page 164: ...tem reset is detected an I O device mustreset and clear any status states requests registers and interface control logic Power on reset is an outbound control line from the power supplyto all system c...

Page 165: ...ion of an address compare and I O active the device raises the select response tag Onceraised this tag must be held active at least until the fall of the I O active tag Condition code in must be activ...

Page 166: ...is tag must be held active at least until the fall of the I O active tag Data bus in and condition code in must be active until strobe becomesactive or until I O active becomesinactive for the duratio...

Page 167: ...data bus in must be active for the duration of the select response tag or at least remain active until strobe becomes active 4 Strobe is activated and dropped The I O device must reset its interrupt r...

Page 168: ...llector Output voltage Up level 2 4 volts leakage current minimum I 40 pa at 2 4 V maximum Down level 0 7 volt at 175 mA maximum Input current Maximum current sinking capacity 175 mA at 0 7 volt Recom...

Page 169: ...nput current 42 mA at 0 6 volt Input impedance 100 ohms Logical 1 1 0 volt Logical 0 2 5 volts DPC adapter input Recommended termination customerdriver 5 V 10 150 ohms 10 Twisted pair TTL open 300 ohm...

Page 170: ...pin assignments for each of the connectors Customer direct program control adapter card _ A B 0O 0 0 0 O 0O O10 O10 O 0 O O O 0 0 0 0 0 O O 0 0 O7 O O O O O O O 0O 0 O O0 Pred ek eke pet COorwpwwh On...

Page 171: ...it 3 B08 Ground AO09 Data bus in bit 4 BO9 Data bus out bit 4 A10 Ground B10 Data bus out bit 5 All Data busin bit 5 Bll Ground Al2 Data bus in bit 6 B12 Data bus out bit 6 Al3 Ground B13 Data bus out...

Page 172: ...Data bus out bit 12 Al10 Ground B10 Data bus outbit 13 All Data bus in bit 13 Bll Ground Al12 Data bus in bit 14 B12 Data bus out bit 14 Al13 Ground B13 Data bus outbit 15 Al4 Data bus in bit 15 B14...

Page 173: ...O09 Interrupt request 10 BO9 Interrupt request 11 Al10 Ground B10 Interrupt request 12 All Interrupt request 13 B11 Ground Al2 Interrupt request 14 B12 Interrupt request 15 Al3 Ground B13 Device addre...

Page 174: ...a bus in bit 10 Data bus in bit 11 Data bus in bit 12 Data bus in bit 13 Data bus in bit 14 Data bus in bit 15 Data busin parity 0 7 Data busin parity 8 15 Figure 6 12 Part 1 of 4 Customer Direct Prog...

Page 175: ...bus out bit 15 Data bus out parity 0 7 Data bus out parity 8 15 Figure 6 12 Part 2 of 4 f lo trti ttl t ttt t l tt ott t I ot et It Ot TCC pin JiB3 Chassis J1B4 J1A2 J1B6 Chassis JiB7 JIBS JiB9 Chassi...

Page 176: ...mode modifier Interrupt service active I O active Strobe Figure 6 12 Part 3 of 4 Customer Direct Program Control DPC Adapter Feature ee f ltl TCC pin JIAI5 Chassis J1B15 J1B14 J1B16 Chassis JIA17 Ji1...

Page 177: ...request 15 Halt or MCHK System reset Power on reset Figure 6 12 Part 4 of 4 f i ti tl tt tte tri rtrd ttt dette te tt i t ttt t i td t TCC pin J3Al1 J3A2 J3B1 Chassis J3A3 Chassis J3B3 Chassis J3B4 C...

Page 178: ...y interrupts from devices during external diagnostic mode These jumpers represent the high order address range assigned to the adapter devices When the adapter is configured for four devices the devic...

Page 179: ...the OEM device being attached and the card file that contains the DPC adapter feature card If there is not a good ground connection a large common modevoltage may be developed and damage to the devic...

Page 180: ...unctionally into three component buses Figure A 1 1 the management group five lines which provides overall bus control 2 the transfer group three lines which provides an asynchronous three wire handsh...

Page 181: ...apter and the first OEM device on the interface is accomplished via a 4 meter 13 1 ft cable RPQ D02119 whichprovides an IEEE Standard 488 24 pin stackable connector as the user interface Additional OE...

Page 182: ...programming information or data on the bus for those devices addressed as listeners Allows data to be transferred from a device on the bus into Series 1 main storage Allows data to be transferred moni...

Page 183: ...in the data area from participating in a parallel poll sequence Causesall devices that are currently able to respond to a parallel poll to be forced into a parallel poll idle state Conducts a parallel...

Page 184: ...ously to an active service request SRQ and generates an attention interrupt to the processor if the adapter is not busy C25 This interface function allows the GPIB adapter to send interface messages c...

Page 185: ...from responding to a device clear message the GPIB adapteris the only permitted active controller Device trigger DTO interface function inhibits the GPIB adapter from responding to a group execute tr...

Page 186: ...to the teletypewriter adapter EIA 4 30 TTL 4 31 Index cable connections teletypewriter adapter card 4 29 CAP see customeraccess panel channel driver receiver classification 2 53 channel drivers receiv...

Page 187: ...DO 5 4 characteristics 5 8 external sync line 5 4 general 1 3 X 2 GA34 0033 digital output DO continued operation modes diagnostic 5 5 external sync 5 5 non interrupting 5 4 direct program control DPC...

Page 188: ...ace Bus see GPIB adapter feature GPIB adapter feature applications A 5 command groups A 2 bus initialization A 3 information exchange A 3 polling and status A 4 universal A 3 data transfer rate A 2 ge...

Page 189: ...4 13 receive 4 17 transmit 4 16 X4 GA34 0033 output byte transfer 2 8 circuits teletypewriter adapter 4 23 levels DO 5 9 sequence DPC adapter 6 8 word transfer 2 8 output circuits teletypewriter adapt...

Page 190: ...3 request in bus I O channel 2 12 cycle steal 2 12 reset power on 2 11 sequences description 2 39 reset continued system signal line 2 11 resets status after timers 3 9 response time digital input 5 8...

Page 191: ...6 write control 4 21 optimuminterface selection 4 6 4 10 X 6 GA34 0033 teletypewriter adapter feature continued options input 4 1 4 5 output 4 1 4 5 physical characteristics 4 29 components descriptio...

Page 192: ...put options 4 1 receiver inputs 4 26 rise time 4 28 unit load current processor I O channel 2 59 voltage level interface 4 6 4 10 transmit operations 4 16 transmitted character frame format 4 11 TTL s...

Page 193: ...X 8 GA34 0033...

Page 194: ...obligation whatever You may of course continue to use the information you supply Please do not use this form for technical questions about the system or for requests for additional publications this o...

Page 195: ...SSARY IF MAILED IN THE women emer eee UNITED STATES BUSINESS REPLY MAIL FIRST CLASS PERMIT NO 40 ARMONK NEW YORK POSTAGE WILL BE PAID BY ADDRESSEE IBM Corporation a Systems Publications Dept 27T TS P...

Page 196: ...not use this form for technical questions about the system or for requests for additional publications this only delays the response Instead direct your inquiries or requests to your BM representative...

Page 197: ...TAGE NECESSARY IF MAILED IN THE a UMS 0 ete ememmemes teeneem mmmnni eemetie elemgain UNITED STATES BUSINESS REPLY MAIL FIRST CLASS PERMIT NO 40 ARMONK NEW YORK POSTAGE WILL BE PAID BY ADDRESSEE IBM C...

Page 198: ...I j i l l i y A 4 i ae z i ky a i onalBusiness MachinesCorporation j GA34 0033 3 Printed in U S A...

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