Manual
ibaFOB-SDexp
32
Issue 1.1
The table can be structured hierarchically by moving column headers per drag & drop to
the free section above.
Figure 24:
Channels, grouped by columns
8.2.6
“Memory view” tab
The memory region “1: FPGA registers” of the ibaFOB-SDexp card is shown in the
“Memory view” tab.
For more details, please refer to chapter 8.1.3 “Memory view” tab.
