Hytera MD78X, Service Manual

Page: 34 / 519

UHF1 (400
–
470 MHz)
Circuit Description
27
Receiver Back-end
Σ
-
Δ
ADC
DECIMATION
FILTER
FORMATTING/SSI
CONTROL LOGIC
DAC AGC
SPI
VOLTAGE
REFERENCE
CLK SYN
LO
SYN
LN A
LO VCO AND LOOP
FILTER
LOOP FILTER
16dB
IOUTL
LOP LON IOUTC CLKP CLKN VREFP VCM VREFN PC PD PE SYNCB
DOUTA
DOUTB
FS
CLKOUT
MXOP MXON IF2P IF2N
GCP GCN
IFIN
FREF
SSI TO OMAP
The first IF signal (73.35 MHz) output by the IF amplifier goes into IF IC via Pin 47, where the signal is
converted to the second IF signal (2.25 MHz). Then the un-demodulated digital I/Q signal output from
the SSI is sent to U302 for demodulation. IF IC employs a reference frequency of 19.2 MHz and shares
the crystal with U302. The second LO VCO consists of the external transistor, varactor and relevant
components, to provide the second LO signal. The clock frequency is 18 MHz, which is generated by the
external LC (D702, L715 and C745) resonance loop.
DSP (U302) acquires the audio signal from IF IC. Then this signal goes through U302 to output data
signal, which is sent to U231 and PIN44 (SSI_DI) for digital-to-analog conversion. Finally, the output
analog audio signal will be subjected to gain control, and then fed to the speaker.
5.3.3
FGU Circuit
PLL Synthesizer
The PLL synthesizer that consists of the crystal oscillator (X100), PLL IC (U100) and VCO, is used to
supply excitation signal source to the transmitter, and LO signal to the receiver.
Crystal Oscillator
Crystal oscillator (X100) employs a 19.2 MHz Temperature Compensated Crystal Oscillator (TCXO),
and its reference frequency is calibrated by the digital-to-analog converter IC (U500) for accuracy.
PLL IC
The PLL IC (U100) is a fractional frequency divider IC. The logic switch ICs (U101 and U102) work with
the PLL IC (U100) to achieve locking.