Hypercom IEN 1000, Hardware Reference Manual

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CHASSIS
940043-002 INTEGRATED ENTERPRISE NETWORK 2-21
B
US
A
RCHITECTURE
The IEN 2000, IEN 3000, IEN 4000 and IEN 5000 chassis backplanes use the same bus
architecture. This allows each chassis to accommodate all the port processors. Each
chassis supports the following buses:
n High-Speed
n Standard
n Time Division Multiplexed (TDM)
Figure 2-15 illustrates the three bus types used by the IEN 2000, IEN 3000, IEN 4000 and
IEN 5000 chassis.
Figure 2-15 Bus Architecture
High-Speed Bus
The high-speed bus is a parallel bus used to transport data frames between the 32-bit port
processors. The data may contain LAN, Legacy, or packetized voice. Figure 2-16 illustrates
the high-speed bus.
Figure 2-16 High-Speed Bus
The high-speed bus is used by the Hypercom second generation port processors, LET61,
LTR61, CID61, and CID63 port processors. These second generation port processors use
the Motorola 68340 or 68302 microprocessors. Refer to Chapter 3, Port Processors/
Modules for more information about these, and other Hypercom port processors.