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1 HP Vectra 500 Series
Principal Components and Features
Dynamic Branch Prediction
The Pentium processor uses dynamic branch prediction. To dynamically
predict instruction branches, the processor uses two prefetch buffers. One
buffer is used to prefetch code in a linear way, and one to prefetch code
depending on the contents of the Branch Target Buffer (BTB). The BTB is a
small cache which keeps a record of the last instruction and address used. It
uses this information to predict the way that the instruction will branch the
next time it is used. When it has made a correct prediction, the branch is
executed without delay, thereby enhancing performance.
Instruction and Data Cache
The Pentium processor has separate code and data caches on-chip. Each
cache is 8 KB in size with a 32-bit line. The cache acts as temporary storage
for data and instructions from the main memory. As the system is likely to
use the same data several times, it is faster to get it from the on-chip cache
than from the main memory.
Each cache has a dedicated Translation Lookaside Buffer (TLB). The TLB is
a cache of the most recently accessed memory pages. The data cache is
configured to be Write-Back on a line-by-line basis (a line is an area of
memory of a fixed size).
The data cache tags (directory entries used to reference cached memory
pages) are triple ported to support two data transfers and an inquire cycle in
the same clock cycle. The code cache tags are also triple ported to support
snooping (a way of tracking accesses to main memory by other devices) and
split line accesses.
Individual pages of memory can be configured as cacheable or non-
cacheable by software or hardware. They can also be enabled and disabled
by hardware or software.