Number of processor modules
Number of processor modules
Number of processor modules
Number of processor modules
Average Memory Latency
Average Memory Latency
Average Memory Latency
Average Memory Latency
4-dual core processor module
241 ns
8-dual core processor module
324 ns
16-dual core processor module
366 ns
I/O Architecture
I/O Architecture
I/O Architecture
I/O Architecture
Components within the I/O subsystem are the I/O controllers, internal peripheral bay, and multifunction
Core I/O. The figure below shows the basic block diagram of the I/O subsystem. The HP 9000 I/O
architecture utilizes industry standard PCI buses in a unique design for maximum performance,
scalability and reliability.
The HP 9000 rp8420 Server contains two master I/O controller chips located on the PCI-X backplane.
Each I/O controller contains sixteen high-performance 12-bit wide links, which connect to sixteen slave
I/O controller chips supporting the PCI-X card slots and core I/O. Two links, one from each master
controller is routed through the crossbar backplane and is dedicated to core I/O. The remaining thirty
links are divided among the sixteen I/O card slots. This one card per link architecture leads to greater
I/O performance and higher availability. Each controller chip is also directly linked to a host cell board.
This means that at least two cell boards, located in cell slots 0 and 1, must be purchased in order to
access all sixteen I/O card slots. With one cell board, access to eight slots is enabled.
The HP 9000 rp8420 Server can be purchased with either one or two core I/O boards (If an SEU is
added, then 4 core I/O boards with 2 Core I/O in the SEU). Both core I/O boards are identical and
provides console, SCSI, serial, and Management Processor (MP) functionality. The second core is used to
enable the dual partitioning in the HP 9000 rp8420 Server and provide access to a second set of disk
drives.
The internal peripheral bay is divided into two identical halves. Each half supports up to two low-profile
disks and one removable media device. A SCSI controller chip located on each core I/O board supports
each half of the internal peripheral bay. This means that both core I/O boards must be purchased to
access both halves of the peripheral bay.
PCI-X Backplane
PCI-X Backplane
PCI-X Backplane
PCI-X Backplane
Fourteen of the sixteen I/O card slots are supported by dual high-performance links. Each link is capable
of providing 530 MB/s of bandwidth. This means that most HP 9000 rp8420 Server I/O slots are
capable of sustained 1.06 GB/s. Aggregate I/O slot bandwidth is 15.9 GB/s. In addition, because each
I/O slot has a dedicated bus, any slot can be "hot-plugged" or serviced without affecting other slots. The
hot-plug operation is very easy, and can be done with minimal training and effort.
The HP 9000 rp8420 Server supports a number of PCI and PCI-X HBA (I/O) cards for I/O expansion
(see Table below). Note that the PCI-X backplane is backward compatible with the older PCI backplane
and can support many PCI HBA (I/O) cards.
When HP 9000 rp8400 servers are upgraded to HP 9000 rp8420 servers using the chassis upgrade kit
A9785A, the older and slower PCI backplanes in the HP 9000 rp8400 server are upgraded to the newer
and faster PCI-X backplanes of the HP 9000 rp8420 Server.
When the rp84xx/px86xx Server Expansion Unit is connected to the HP 9000 rp8420 Server, its I/O
backplanes act as PCI-X I/O backplanes. See the rp84xx/px86xx Server Expansion Unit section for more
details.
Supported I/O Cards
Supported I/O Cards
Supported I/O Cards
Supported I/O Cards (HBAs)
QuickSpecs
HP 9000 rp8420 Server
HP 9000 rp8420 Server
HP 9000 rp8420 Server
HP 9000 rp8420 Server
Configuration
DA - 11894 Worldwide — Version 25 — March 1, 2007
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