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17

2   System Board

Architectural View

Architectural View

Level-2 

cache

Main

memory

Hard 

disk

Pentium 

processor

Processor-Local Bus
(64 bit, 66 MHz)

PCI Bus
(32 bit, 33 MHz)

ISA Bus
(16 bit, 8.25 MHz)

Interrupt 

controller

Graphics

controller

System 

ROM

Serial 

EEPROM

X Ben 

(HP ASIC)

DMA

controller

ISA bus 

interface

2

✕

USB 

controller

NS87317

Super I/O

FDD 

controller

Keyboard 

controller

Parallel 

controller

Mouse

controller

ISA bus 

interface

2

✕

serial 

controller

SiS5581

PL/PCI bridge 

PCI/ISA bridge

Memory 

controller

Data path

PCI bus 

interface

Cache

controller

2

✕

IDE

controller

PL bus

interface

1book.bk : 1ch02.fb4  Page 17  Wednesday, July 23, 1997  10:17 AM

Summary of Contents for Net Vectra

Page 1: ...Technical Reference Manual Hardware and BIOS HP Net Vectra PC ...

Page 2: ...or reliability of its software on equipment that is not furnished by Hewlett Packard This document contains proprietary information that is protected by copyright All rights are reserved No part of this document may be photocopied reproduced or translated to another language without the prior written consent of Hewlett Packard Company AdobeTM is a trademark of Adobe Systems Incorporated which may ...

Page 3: ...vailable from other sources such as manufacturer s proprietary publications has not been reproduced This manual contains summary information only For additional reference material refer to the bibliography on the next page Conventions The following conventions are used throughout this manual to identify specific numeric elements Hexadecimal numbers are identified by a lower case h For example 0FFF...

Page 4: ...0901 HP Net Vectra Online User s Guide online Exploring your HP Net Vectra PC online HP Network Administrator s Guide online HP Vectra Accessories Service Handbook 7th edition 5965 4074 HP Vectra PC Service Handbook Volume 1 12th edition to be announced HP Support Assistant CD ROM by subscription The following Intel publication provides more detailed information Pentium Microprocessor Data Sheet 2...

Page 5: ...stem Board 16 Architectural View 17 Chip Set 18 Bridge Chip SiS5581 18 Super I O Chip NS87317 20 Devices on the Processor Local Bus 24 The Intel Pentium Microprocessor 24 Cache Memory 25 Main Memory 25 Devices on the PCI Bus 26 Integrated Drive Electronics IDE 26 Universal Serial Bus USB Controller 28 Devices on the ISA Bus 29 Super I O Controller 29 ...

Page 6: ...ectors and Sockets 40 4 Summary of the HP Phoenix BIOS HP Phoenix BIOS Summary 44 Setup Program 46 Main Menu 46 Configuration Menu 46 Security Menu 47 Power Menu 47 Power Saving and Ergonometry 48 Desktop Management Interface DMI 48 HP Lock 48 Power On from Space Bar 49 Soft Power Down 49 HP Off 49 Remote Power On RPO 50 Advanced Power Management APM 52 BIOS Addresses 55 System Memory Map 55 ...

Page 7: ... Identification 55 HP I O Port Map I O Addresses Used by the System 56 5 Power On Self Test and Error Messages Order in Which the Tests are Performed 62 Error Message Summary 65 Beep Codes 66 Lights on the Status Panel 66 ...

Page 8: ...Contents viii ...

Page 9: ... 1 System Overview This manual describes the HP Net Vectra PC and provides detailed system specifications This chapter introduces the external features and summarizes the documentation which is available ...

Page 10: ...t necessarily appear on the PC Activity light Status light Front view Activity light On off button Pause button Cover lock System board switches Processor Heat pipe and Heat sink Main memory Hard disk drive Front view with cover removed USB Serial Parallel Mouse Keyboard Display Rear view ...

Page 11: ...s printed on the page and the page number that Acrobat Reader indicates because of the presence of the front matter pages Preloaded on Hard Disk Division Support Server Support Assistant CD ROM Paper based HP Net Vectra User s Guide no PDF file PDF file D5470 90901 HP Net Vectra Upgrading and Maintaining the PC no PDF file PDF file no HP Net Vectra Recovery Guide no PDF file PDF file no HP Net Vec...

Page 12: ...Online Exploring Your PC Network Admin Guide Familiar ization Guide Service Hand book Tech Ref Manual Introducing the computer Product features Key features Exploring New features Exploded view Parts list x x x x x x x x Product model numbers Product range CPL dates x x Using the computer Setting Up the PC Connecting cables Turning on x x Finding information READ MEs On line documentation Environm...

Page 13: ...Detailed Advanced x x x x System board Jumpers Switches Connectors Replacement Chip set x x x x x x x x x x BIOS Basic details Technical details Memory maps Upgrading x x x x x Power On Self Test Key error conditions Order of tests x x x User Documentation Online Documentation Support Documentation User s Guide Upgrade Guide Recovery Guide User Online Exploring Your PC Network Admin Guide Familiar...

Page 14: ...14 1 System Overview Documentation ...

Page 15: ...and network devices which are supplied with the computer This chapter describes the components of the system board taking in turn the components of the Processor Local Bus the Peripheral Component Interconnect PCI bus and the Industry Standard Architecture ISA bus ...

Page 16: ...ideo Memory Parallel Port Serial Port Display Kbd Mou VESA Connector Graphics Controller Chip Ext Start External Speaker Connector Internal Speaker PCI wake up 3 3 V Conn 2 USB 1 2 3 4 5 6 7 8 9 10 Connector Pentium Processor Heat Pipe Socket 7 SiS 5581 NS87317 PL PCI bridge PCI ISA bridge DRAM controller IDE USB cntlr Super I O controller CR2032 System ROM Ext Batt 210 mm 280 mm L2 cache L2 cache...

Page 17: ...Interrupt controller Graphics controller System ROM Serial EEPROM X Ben HP ASIC DMA controller ISA bus interface 2 USB controller NS87317 Super I O FDD controller Keyboard controller Parallel controller Mouse controller ISA bus interface 2 serial controller SiS5581 PL PCI bridge PCI ISA bridge Memory controller Data path PCI bus interface Cache controller 2 IDE controller PL bus interface ...

Page 18: ...It translates PL bus cycles into PCI bus cycles The chip supports the SMM mode of the Pentium processor the CPU stop clock hardware function and the keyboard lock function These are used by the X Ben chip as described on page 51 PCI Bus Interface The chip is PCI 2 1 compliant and provides for PCI Concurrency Concurrent data transfers that do not contest for the same resources such as processor to ...

Page 19: ...volve a full cache line and so require four back to back cycles on the bus Since they involve accesses to related addresses they do not need four independent accesses to main memory but can be organized as a pipelined burst The second third and fourth cycles in each burst require less time to complete than the first the first cycle having included the addressing phase and memory pre charge timing ...

Page 20: ...o 3 are for 8 bit DMA devices while channels 5 to 7 are for 16 bit devices as described on page 57 The channels can be programmed for any of the four transfer modes the three active modes single demand block can perform three different types of transfer read write and verify The address generation circuitry can only support a 24 bit address for DMA devices Interrupt Controller The sixteen channel ...

Page 21: ...igh speed mode MS HP extended capabilities port ECP compatible FDC The integrated flexible drive controller FDC supports any combination of two from the following tape drives 3 5 inch flexible disk drives 5 25 inch flexible disk drives It is software and register compatible with the 82077AA and 100 IBM compatible It has an A and B drive swapping capability and a non burst DMA option Keyboard and M...

Page 22: ...ly active to respond immediately to user and network requests General Purpose I O There are several general purpose I O pins Some of these are used on the HP Net Vectra to sense the current settings of system board switches as described on page 24 and page 31 Description GPIO number Cache sleep GPIO0 Screen blank GPIO1 Error light GPIO2 MA12 GPIO3 MA13 GPIO4 not connected GPIO5 Low power mode GPIO...

Page 23: ...s core frequency BCF0 connected to SW 3 open 1 closed 0 GPIO26 Bus core frequency BCF1 connected to SW 4 open 1 closed 0 GPIO27 Host bus request detect 60 66 MHz connected to SW 1 always 0 GPIO30 Serial EEPROM data GPIO31 FDD write protect not used GPIO32 Password enable connected to SW 7 open 1 closed 0 GPIO33 Clear CMOS connected to SW 8 open 1 closed 0 GPIO34 Serial EEPROM chip select GPIO35 Se...

Page 24: ...s of the processor are critical Bus Frequencies The location of the system board switches is shown in the diagram on page 16 Five of these switches SW 1 2 3 4 and 5 determine the working frequencies of the PC as summarized in the table below The uses of the other switches are summarized on page 31 There is a 14 318 MHz crystal oscillator on the system board This frequency is multiplied to 66 MHz b...

Page 25: ...a PC 256 KB of direct mapped write back synchronous pipelined burst 8 5 ns static random access memory SRAM is integrated on the system board Main Memory There are three main memory module sockets arranged in three banks A to C One bank is already occupied by the double interline memory module DIMM that contains the 16 MB or 32 MB of memory that is supplied with the computer Different banks can ha...

Page 26: ...ster and one slave to the secondary channel A cable is supplied that provides a single connector for one device to one channel Transfer Rates Versus Modes of Operation The controller supports 32 bit Windows I O transfers Five PIO modes three DMA modes and three Ultra ATA 33 modes are supported The five supported PIO modes allow the following transfer rates PCI Device Device Name Device Number Func...

Page 27: ... physical size of the hard disk the addressing limit of the IDE hardware and the addressing limit of the BIOS By performing a translation the Extended CHS addressing scheme allows larger disk capacities to be addressed than under CHS Mode 0 1 2 Cycle time ns 480 150 120 Transfer rate MB s 4 2 13 3 16 7 Mode 0 1 2 Cycle time ns 144 75 60 Transfer rate MB s 13 9 26 7 33 3 Cylinders per Device Heads ...

Page 28: ...per second transfer rate Supports up to 127 devices maximum Isochronous and asynchronous data transfer support Up to 5 m per cable segment Built in power distribution Supports daisy chaining through a tiered star multi drop topology up to 6 tiers USB works only if the USB interface has been enabled within the HP Setup program Currently only the Microsoft Windows 95 operating system provides suppor...

Page 29: ...ght mouse button Serial EEPROM The computer uses 4 Kbit of Serial EEPROM implemented within a single 512 K 8 bit ROM chip Serial EEPROM is ROM in which one byte at a time can be returned to its unprogrammed state by the application of appropriate electrical signals In effect it can be made to behave like very slow non volatile RAM It is used for storing the tatoo string the serial number and the p...

Page 30: ...OS This can be downloaded as a compressed file from the HP Electronic Services http www hp com go vectrasupport You must specify the model of the computer since the utility which is supplied for a different model cannot be used with this one More information is given in the Hewlett Packard Support and Information Services chapter in the User s Guide that was supplied with the computer Since the PC...

Page 31: ...nd clear CMOS switches SW 7 and SW 8 on the system board reconnect the PC and turn it on This forces the PC to re boot from the flexible disk drive Once the recovery program has completed the BIOS can be flashed by running the PHLASH EXE program Once completed return the system board switches to their original positions and disconnect the flexible disk drive System Board Switches Five of the syste...

Page 32: ...t correctly after replacing a defective system board by a new one the BIOS is able to tailor itself for the particular product and to enable the appropriate features Updating the BIOS Before Considering Replacing the System Board If the computer is faulty but it starts up correctly and the fault is not clearly due to the system board hardware then it is advisable to check the BIOS version number T...

Page 33: ...Devices and Mass Storage Drives This chapter describes the graphics mass storage and network devices which are supplied with the computer It also summarizes the pin connec tions on the internal and external connectors ...

Page 34: ...z clock for video memory fast linear addressing with full software relocation green power saving features playback acceleration continuous interpolation on X continuous interpo lation on Y DDC 2B compliant Video Modes Standard and Enhanced Video Graphics Array VGA modes are available Hardware acceleration of graphical user interface GUI operations is provided and acceleration for 8 16 and 32 bit p...

Page 35: ...0 x 25 chars b w 70 31 5 25 175 02h VGA text 80 x 25 chars b w 70 31 5 25 175 02h VGA text 80 x 25 chars b w 70 31 5 28 322 03h VGA text 80 x 25 chars 16 70 31 5 25 175 03h VGA text 80 x 25 chars 16 70 31 5 25 175 03h VGA text 80 x 25 chars 16 70 31 5 28 322 04h VGA graphics 320 x 200 4 70 31 5 25 175 05h VGA graphics 320 x 200 4 70 31 5 25 175 06h VGA graphics 640 x 200 2 70 31 5 25 175 07h VGA t...

Page 36: ...600 16 60 37 9 40 000 6Ah 102h graphics 800 x 600 16 72 48 1 50 000 6Ah 102h graphics 800 x 600 16 75 47 5 49 500 6Ah 102h graphics 800 x 600 16 85 53 6 56 000 6Bh 103h graphics 800 x 600 256 60 37 9 40 000 6Bh 103h graphics 800 x 600 256 72 48 1 50 000 6Bh 103h graphics 800 x 600 256 75 46 8 49 500 6Bh 103h graphics 800 x 600 256 85 53 6 56 000 6Ch 104h graphics 1024 x 768 16 60 48 4 65 000 6Ch 1...

Page 37: ...h 114h graphics 800 x 600 65 536 72 48 1 50 000 74h 114h graphics 800 x 600 65 536 75 46 8 49 500 74h 114h graphics 800 x 600 65 536 85 53 6 57 000 75h 115h graphics 800 x 600 16 7 M 60 37 9 40 000 75h 115h graphics 800 x 600 16 7 M 72 41 8 50 000 75h 115h graphics 800 x 600 16 7 M 75 46 8 49 500 75h 115h graphics 800 x 600 16 7 M 85 53 6 57 000 76h 116h graphics 1024 x 768 32 768 60 48 9 65 000 7...

Page 38: ... VGA socket is depicted on page 42 The Video Electronics Standards Association VESA defines a standard video connector variously known as the VESA feature connector auxiliary connector or pass through connector This connector whose pin names are listed in a table on page 40 is integrated on the system board and is connected directly to the pixel data bus and the synchronization signals The graphic...

Page 39: ...rives Mass Storage Drives Mass Storage Drives A 3 5 inch hard disk drive is supplied on an internal shelf in all models The IDE controller is described on page 26 1 6 GB IDE 1 GB IDE HP product number D2679A D5190A Manufacturer Quantum Quantum ...

Page 40: ...ey 19 Ground 20 STP 21 DMARQ 22 Ground 21 Ground 22 WRDATA 23 DIOW 24 Ground 23 Ground 24 WREN 25 DIOR 26 Ground 25 Ground 26 TRK0 27 IORDY 28 SPSYNC CSEL 27 Ground 28 WRPRDT 29 DMACK 30 Ground 29 Ground 30 RDDATA 31 INTRQ 32 IOCS16 31 Ground 32 HDSEL1 33 DA1 34 PDIAG 33 Ground 34 DSKCHG 35 DA0 36 DA2 37 CS0 38 CS1 39 DASP 40 Ground Status Panel Connector Pin Signal Pin Signal 1 LCK_LED_K 2 LCK_LE...

Page 41: ...d A65 PAR64 B20 Ground A20 AD 28 B66 AD 63 A66 AD 62 B21 AD 27 A21 AD 26 B67 AD 61 A67 Ground B22 AD 25 A22 3 3 V B68 3 3 V A68 AD 60 B23 Ground A23 AD 24 B69 AD 59 A69 AD 58 B24 C BE 3 A24 IDSEL B70 AD 57 A70 Ground B25 AD 23 A25 Ground B71 Ground A71 AD 56 B26 3 3 V A26 AD 22 B72 AD 55 A72 AD 54 B27 AD 21 A27 AD 20 B73 AD 53 A73 3 3 V B28 AD 19 A28 Ground B74 Ground A74 AD 52 B29 Ground A29 AD 1...

Page 42: ...entation key 9 5 V supply 2 Ground 5 3 3 V supply 3 Remote_On 10 5 V supply 3 Ground 6 3 3 V supply 4 Ground 11 5 V supply 5 Ground 12 12 V supply 6 Ground 13 5 V supply 7 12 V supply USB Connector Pin Signal Battery Pack Connector 1 Vcc Pin Signal Pin Signal 2 Data 1 VBATT 3 not connected 3 Data 2 orientation key 4 Ground 4 Ground Keyboard and Mouse Connector Serial Port Connector VGA Connector P...

Page 43: ...43 4 Summary of the HP Phoenix BIOS The Setup program and HP Phoenix BIOS are summarized in this chapter The POST routines are described in the next chapter ...

Page 44: ...rom the network described later in this chapter The Power On Self Test or POST which is the sequence of tests the com puter performs to ensure that the system is functioning correctly de scribed in the next chapter The system BIOS is identified by a version number of the form HE 07 xx The procedure for updating the System ROM firmware is described on page 30 Press to run the Setup program while th...

Page 45: ...stem RAM 32 MB Processor type Pentium Bank A 32 MB SDRAM COM1 3F8H Serial Bank B None COM2 None Bank C None COM3 None Video RAM 2 MB COM4 None System Cache 256KB Synchronous LPT1 378H Video Device S3 Trio 64V2 LPT2 None 1st IDE Device HDD 1600 MB LPT3 None 2nd IDE Device None Flexible Disk A None 3rd IDE Device None Flexible Disk B None 4th IDE Device None Display type Not Available ISA PnP Not In...

Page 46: ...ons are Some fields are not changeable Examples include fields that are for information only and fields whose contents become frozen by the setting of a value in some other field Such fields are displayed in a different color without the and brackets When the user moves the cursor with the up and down arrow keys these fields are skipped Some fields disappear completely when a choice in another fie...

Page 47: ...and network connections using the Start Up Center sub menu Locking a device in the Security Menu frees the resources such as IRQs and peripheral addresses Power Menu The Power menu allows the user to set the standby delay It also allows the system administrator to decide whether the network serial port mouse or space bar are enabled as a means of reactivating the system from Standby or Suspend It ...

Page 48: ... PC Facilities are provided for Passwords Lock options such as screen hiding and screen saving Start up protection Disk drive access enabled or disabled Communications port access enabled or disabled Fully On Standby Suspend Off but plugged in Processor Normal speed Clock throttled divided by 8 Halted Halted Display Normal operation Blanked 30 W Blanked 5 W typical Blanked 5 W typical Hard disk dr...

Page 49: ...e operating system to shutdown the environment is cleared and the computer is powered off The hardware to do this and the complementary function HP Off as described in the next section is contained within the HP ASIC chip X Ben This chip is described on page 51 HP Off If the user attempts to turn the PC off at the status panel the PC logic will delay the shutting down of the power supply until it ...

Page 50: ...edia Access Control MAC address which it has stored in an EEPROM on the network board repeated 16 times and encoded in a valid network packet Any Magic Packet compatible management application such as HP Open View Workgroup Node Manager can send a Magic Packet frame An administrator can do this manually or can incorporate it into a management script The packet travels over any type of Ethernet LAN...

Page 51: ...he RPO feature RPO is intended for resource management such as virus cleaners nightly backups etc not for crisis management thunderstorm recovery power failure etc X Ben X Ben is an HP application specific integrated circuit ASIC designed to be a companion to the Super I O chip It interfaces between the chip set and the processor and contains the following BIOS timer hardware wired 50 ms long 880 ...

Page 52: ...er If the computer hangs the power button on the status panel should be held pressed for about 6 seconds A watch dog timer will detect that the BIOS is inactive and not reloading the timer once every 6 seconds thereby forcing the computer to turn itself off without further BIOS acknowledgment Advanced Power Management APM The BIOS is APM 1 2 compliant providing it with facilities for advanced powe...

Page 53: ...53 4 Summary of the HP Phoenix BIOS Power Saving and Ergonometry ...

Page 54: ...54 4 Summary of the HP Phoenix BIOS Power Saving and Ergonometry The following diagram gives a more accurate more detailed account of the valid state changes ...

Page 55: ...on and BIOS identification strings are no longer accessed directly Instead the information is obtained from utilities in the Desk Management Interface DMI 0 3FFh Interrupt vector table 640 KB The addresses 0 9FFFFh are collectively known as the Base memory area 400h 4FFh BIOS data area 500h 9EFFFh 9F000h 9FFFFh Extended BIOS data area A0000h BFFFFh 128 KB Video memory area C0000h C7FFFh 32 KB Vide...

Page 56: ...ss map is not completely BIOS dependent but is determined partly by the operating system Beware that some of the I O addresses are allocated dynamically 1 If configured legacy resources only I O Address Ports Function 0000h 000Fh DMA controller 1 0020h 0021h Interrupt controller 1 0040h 0043h Interval timer 1 0060h 0064h Keyboard controller 0061h System speaker or NMI status and control 0070h NMI ...

Page 57: ...available if not used 02F8h 02FFh Serial port 2 available if not used 0370h 0371h Super I O controller 0372h 0375h Secondary flexible disk drive controller 0376h IDE hard disk drive controller secondary channel 0377h Secondary flexible disk drive controller 0378h 037Ah Parallel port 1 available if not used 03B0h 03DFh Graphics controller S3 Trio 64V2 03E8h 03EFh Serial port 3 03F0h 03F5h Primary f...

Page 58: ...roller and followed by the slave First DMA controller used for 8 bit transfers Channel Function 0 Available 1 ECP mode for parallel port available if not used 2 Flexible disk controller 3 ECP mode for parallel port available if not used Second DMA controller used for 16 bit transfers Channel Function 4 Cascade from first DMA controller 5 Available 6 Available 7 Available IRQ Interrupt Vector Inter...

Page 59: ...irected to the system interrupt controller The interrupt request will be re directed to one of the IRQ lines made available for PCI devices The PCI interrupt lines A B C and D are spread across the four inputs of the interrupt router which is part of the PCI ISA bridge in the Bridge chip Since most PCI devices are single function this allows for an even distribution of the lines The distribution i...

Page 60: ...ting of interrupts when enabled this bit routes the PCI interrupt signal to the PC compatible interrupt signal specified in bits 3 0 At reset this bit is disabled set to 1 6 4 Reserved read as 000 3 0 IRQx Routing Bits these bits specify which IRQ signal to generate Possible values are 3 4 5 6 7 9 10 11 12 14 15 A A B C D PCI ISA Bridge Integrated A B C D Slot 2 A B C D Slot 1 graphics ...

Page 61: ...er On Self Test and Error Messages This chapter describes the Power On Self Test POST routines which are contained in the System BIOS the error messages that can result and the suggestions for corrective action ...

Page 62: ...does not detect when a hard disk drive has been otherwise changed During the POST the BIOS and other ROM data is copied into high speed shadow RAM The shadow RAM is addressed at the same physical location as the original ROM in a manner which is completely transparent to applications It therefore appears to behave as very fast ROM This technique provides faster access to the system BIOS firmware T...

Page 63: ... code to display DMA Subsystem Test Checks the DMA controller registers Test failure causes an error code to display Interrupt Controller Test Tests the Interrupt masks the master controller interrupt path by forcing an IRQ0 and the industry standard slave controller by forcing an IRQ8 Test failure causes an error code to display Real Time Clock Test Checks the real time clock registers and perfor...

Page 64: ... an error code to display Coprocessor Tests Internal Numeric Coprocessor Test Checks for proper operation of the numeric coprocessor part of the processor Test failure causes an error code to display Communication Port Tests Parallel Port Test Tests the integrated parallel port registers as well as any other parallel ports Test failure causes an error code to display Serial Port Test Tests the int...

Page 65: ... is detected in POST Check that boot on the hard disk drive is enabled in Setup System battery is dead You may get this message if the computer is disconnected for a few days When you Power on the computer run Setup to update the configuration information The message should no longer be displayed Should the problem persist replace the battery Keyboard error Check that the keyboard is connected Res...

Page 66: ...essor or the System ROM in the instruction fetch process Check that the processor is correctly seated in its socket 1 Where digits 1 2 3 4 represent the number of short beeps and 0 represents the occurrence of a single long beep Beep Pattern Beep Code1 Numeric Code Description 1 B4h This does not indicate an error There is one short beep before system startup 02 98h Video configuration failure or ...

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