System Information
System Board
Appendix B
128
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Non-volatile memory
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Scratch RAM
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Real Time Clock
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UARTs
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External Registers
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Firmware read/writable registers
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Two general purpose 32-bit registers
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Semaphore registers
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Monarch selection registers
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Test and Reset register
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Reset and INIT generation
Dual Serial Controller
The dual serial controller is a dual universal asynchronous receiver and transmitter (DUART). This chip
provides enhanced UART functions with 16-byte FIFOs, a modem control interface. Registers on this chip
provide onboard error indications and operation status. An internal loopback capability provides onboard
diagnostics.
Features include:
•
Data rates up to 115.2kbps
•
16550A fully compatible controller
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A 16-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
•
A 16-byte receive FIFO with four selectable interrupt trigger levels and error flags to reduce the
bandwidth requirement of the external CPU
•
UART control that provides independent transmit and receive
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Modem control signals (-CTS, -RTS, -DSR, -DTR, -RI, -CD, and software controllable line break)
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Programmable character lengths (5, 6, 7, 8) with Even, Odd or No Parity
•
A status report register
Field Programmable Gate Array
The field programmable gate array (FPGA) provides ACPI and low pin count (LPC) support for HP Intel
Itanium 2 platforms based on HP chipsets. This controller is connected to the PDH bus and provides these
features:
•
ACPI 2.0 interface
•
LPC bus interface to support BMC
•
Decoding logic for PDH devices
