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SIGNAL
NAME

E2470A STATE
CONNECTOR PIN

ANALYZER
BIT

STATE
LABEL

STATE
SUBLABEL

STATE
SUBLABEL

FC2/~CS5

4- 9

4-14

ADDR_B

FCx

CSx

unused

4- 7

4-15

~SHOW_CYCLE

2-37

2- 0

STAT

ShoCyc

R/~W

2-35

2- 1

STAT

R/~W

~INST_FETCH

2-33

2- 2

STAT

IFetch

~PIPE_FLUSH

2-31

2- 3

STAT

PFlush

SIZ0

2-29

2- 4

STAT

SIZx

SIZ1

2-27

2- 5

STAT

SIZx

~SIZE0_VALID

2-25

2- 6

STAT

~SIZE1_VALID

2-23

2- 7

STAT

QUALIFIED_
DSACK0

2-21

2- 8

STAT

DSACKx

QUALIFIED_
DSACK1

2-19

2- 9

STAT

DSACKx

~BERR

2-17

2-10

STAT

BErr

~BUS_ARB_
INVALID

2-15

2-11

STAT

~FCx_INVALID

2-13

2-12

STAT

~A19-A23_
INVALID

2-11

2-13

STAT

FREEZE/QUOT

2- 9

2-14

STAT

Freeze

~BKPT/DSCLK

2- 7

2-15

STAT

Bkpt

Preprocessor Interface Hardware Reference

State Connector Signal Definition

3–9

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Summary of Contents for E2470A

Page 1: ...ble You will find any other available product information on the Agilent Test Measurement website www tm agilent com HP References in this Manual This manual may contain references to HP or Hewlett Packard Please note that Hewlett Packard s former test and measurement semiconductor products and chemical analysis businesses are now part of Agilent Technologies We have made no changes to this manual...

Page 2: ...7001 First Edition February 1996 For Safety Information Warranties and Regulatory Information see the pages at the end of this manual Copyright Hewlett Packard Company 1995 1996 All Rights Reserved HP E2470A MC68HC16Y1 Preprocessor Interface ...

Page 3: ...ents an inverse assembler converts captured microcontroller instruction cycles into MC68HC16Y1 assembly language mnemonics The slide switches are used to inform the inverse assembler about the microcontroller configuration The user must set these switches appropriately before making a state measurement The interface contains 13 connectors 7 for timing measurements 4 for state measurements and 2 fo...

Page 4: ...HP E2470A Preprocessor Interface Introduction The HP E2470A Preprocessor Interface At a Glance iii ...

Page 5: ... or timing analysis Chapter 2 provides reference information on the format specification and symbols configured by the preprocessor interface software and information about the inverse assemblers and status encoding Chapter 3 contains reference information on the preprocessor interface hardware including the characteristics and signal mapping for the preprocessor interface For more information on ...

Page 6: ... 55A 56A analyzer 1 11 To connect to the HP 1660A AS analyzer 1 11 To connect to the HP 1661A AS analyzer 1 12 To connect to the HP 1662A AS analyzer 1 12 Loading the Preprocessor Interface Software 1 13 To load the configuration and inverse assembler 1 13 To connect to the Background Debug Monitor interface 1 14 2 Analyzing the Motorola MC68HC16Y1 Displaying Information 2 3 To display the format ...

Page 7: ...ata errors A 3 Unwanted triggers A 3 No activity on activity indicators A 4 No trace list display A 4 Target system will not boot up A 5 Erratic trace measurements A 6 Capacitive loading A 6 No inverse assembly or incorrect inverse assembly A 7 Inverse assembler will not load or run A 8 An event wasn t captured by one of the modules A 9 Messages A 10 Inverse Assembler Not Found A 10 Measurement In...

Page 8: ...1 Setting Up the Preprocessor Interface ...

Page 9: ... the Preprocessor Interface This chapter explains how to set up the HP E2470A Preprocessor Interface hardware and software configure the preprocessor and connect the preprocessor to supported logic analyzers 1 2 ...

Page 10: ... interface The HP E5335A probe adapter The configuration and inverse assembler software on a 3 5 inch disk One of the logic analyzers listed in the following table Logic Analyzers Supported Logic Analyzer Channel Count State Speed Timing Speed Memory Depth 16550A one card 102 100 MHz 250 MHz 4 k states 16554A one card 68 70 MHz 125 MHz 512 k states 16555A one card 68 110 MHz 250 MHz 1 M states 165...

Page 11: ...ould always be powered up before the target system when powering down power down the target system first and then power down the logic analyzer Set the slide switches on the top of the preprocessor interface according to the configuration of the MC68HC16Y1 Attach the HP E5335A probe to the target system Attach the preprocessor interface to the HP E5335A probe Connect the logic analyzer pods to the...

Page 12: ...ect the delicate gold plated pins of the assembly from damage due to impact Covering the pins and properly storing the preprocessor interface also protects the active circuitry on the preprocessor interface from electrostatic discharge To set the slide switches The slide switches are used to inform the inverse assembler about the MCU configuration when making state measurements The switches perfor...

Page 13: ...NVALID position Six switches are used to validate control signals from the MCU They are SIZ0 SIZ1 DSACK0 DSACK1 AS and DS In order to distinguish between internal and external bus cycles the preprocessor must have one of the following combinations DS and AS must be valid or DS and at least one CS must be valid If DS is the only valid control signal all cycles will be interpreted as internal cycles...

Page 14: ...ocontroller Ensure that pin 1 is properly aligned C AU TI O N Serious damage to the target system or preprocessor interface can result from incorrect connection Note the position of pin 1 and pin A1 on the preprocessor interface probe adapter assembly and microcontroller prior to making any connection Also take care to align the preprocessor interface connector with the pins on the probe adapter a...

Page 15: ...ale end of the termination adapter with the slot on the connector of one of the logic analyzer cables Push the termination adapter into the connector Connect the female end of the termination adapter to the preprocessor interface Connecting the Termination Adapter Using the flex adapter The HP E3445A flex adapter is designed to relieve mechanical stress and to provide a degree of freedom between t...

Page 16: ... and attach the preprocessor to the flex adapter aligning preprocessor pin A1 directly above the microcontroller pin 1 Flex Adapter Diagram The flex adapter contains a 15 x 15 array of pins while the preprocessor contains only 14 x 14 When the flex adapter is folded over there is a 1 1 correspondence between vertical pins Be sure to attach the preprocessor to the appropriate set of pins attached t...

Page 17: ...nect the logic analyzer to the preprocessor interface To connect to the HP 16550A one card analyzer 1 Connect the pod cables to the preprocessor interface according to the pod diagram below 2 For state load configuration file F68HC16S For timing load configuration file F68HC16T 1 10 ...

Page 18: ...tion file M68HC16S For timing load configuration file M68HC16T To connect to the HP 1660A AS analyzer 1 Connect the pod cables to the preprocessor interface according to the pod diagram below 2 For state load configuration file F68HC16S For timing load configuration file F68HC16T Connecting to the Logic Analyzer To connect to the HP 16554A 55A 56A analyzer 1 11 ...

Page 19: ...tion file F68HC16S For timing load configuration file F68HC16T To connect to the HP 1662A AS analyzer 1 Connect the pod cables to the preprocessor interface according to the pod diagram below 2 For state load configuration file F68HC16S For timing load configuration file F68HC16T Connecting to the Logic Analyzer To connect to the HP 1661A AS analyzer 1 12 ...

Page 20: ...HP 1660 series logic analyzers select the System Disk menu For the HP 16500A mainframe select the System Front Disk menu For the HP 16500B mainframe select the System Flexible Disk menu 4 Configure the menu to Load the analyzer configuration from disk 5 Select the appropriate module such as 100 500 MHz LA or Analyzer for the load 6 Use the knob to select the appropriate configuration file Choosing...

Page 21: ...nector J2 allows the user to select the supply voltage sent to the BDM interface If the 2 pin jumper is connected between pins 1 and 2 5V is connected If the jumper is connected between pins 2 and 3 the voltage of the MC68HC16Y1 is connected It is assumed that if the BDM hardware is operating at 3 3V the MC68HC16Y1 is also a 3 3V device If however the MC68HC16Y1 is a 5V device and the BDM hardware...

Page 22: ...2 Analyzing the Motorola MC68HC16Y1 ...

Page 23: ...Analyzing the Motorola MC68HC16Y1 This chapter describes preprocessor interface data symbol encodings and information about the available inverse assemblers 2 2 ...

Page 24: ...ations include all labels for monitoring the microcontroller and any coprocessors connected directly to the microcontroller The figure below shows the Format specification for state analysis The figure on the following page shows the Format specification for timing analysis Chapter 3 of this guide contains a table that lists the signals for the MC68HC16Y1 processor and on which pod and probe bit t...

Page 25: ...alyzer front panel to view additional signals Select the Pods field and rotate the knob to view other pod bit assignments There may be some slight differences in the display shown by your particular analyzer Do you want any screen shots Figure 6 Analyzing the Motorola MC68HC16Y1 To display the format specification 2 4 ...

Page 26: ... 2 INST_FETCH Indicates an instruction fetch 3 PIPE_FLUSH Indicates an instruction caused an instruction pipeline flush 4 5 SIZE0 1 Indicates the number of bytes in a transfer 6 SIZE0_VALID Indicates that the MCU is configured to supply SIZE0 7 SIZE1_VALID Indicates that the MCU is configured to supply SIZE1 8 9 DSACK0 1 Indicates the number of bytes accepted provided in a transfer 10 BERR Indicat...

Page 27: ...bit x x 3 x H Long Word Transfer 32 bit x x 0 x H The logic analyzer captures prefetches even if they are not executed Care must be taken when specifying a trigger condition or a storage qualification that follows an instruction that may cause branching An unused prefetch may generate an unwanted trigger Since the microcontroller only prefetches at most two words one technique to avoid unwanted tr...

Page 28: ...in a format that closely resembles the assembly source code for your processor Example The following figure shows the Listing Menu display for the HP 16550A logic analyzer Figure 7 Top line of display Synchronization begins here Unexecuted prefetch Missing opcodes caused by unexecuted prefetch Cursor position Don t care bytes Analyzing the Motorola MC68HC16Y1 To display captured state data 2 7 ...

Page 29: ... are primarily due to microcontroller prefetch activity Storage qualification or the use of storage windows can also lead to such occurrences Don t Care Bytes The MC68HC16Y1 microcontroller can perform 3 byte transfers During operand reads and writes 16 bit word values appear on the microcontroller data bus lines The inverse assembler will attempt to display xx for any byte in a transfer that is i...

Page 30: ... MC68HC16Y1 inverse assembler is capable of suppressing certain acquired bus cycles from the display thus allowing the user to focus on and display cycles of interest The filter softkeys are part of the Invasm Options submenu Invasm Options must be pressed to display the submenu Cycle suppression is broken down into the following categories extension words unexecuted prefetches branches calls and ...

Page 31: ...nt settings for different analysis requirements This function allows faster analysis in two ways First unneeded information can be filtered out of the display Second particular operations can be isolated by suppressing all other operations For example I O branches can be shown with all other operations suppressed allowing quick analysis of I O branch flow No t e If the X or O pattern markers are t...

Page 32: ... appear on the bottom of the screen If you jump to another area of the listing by entering a new line number or by rolling the screen down you may have to re synchronize the inverse assembler by repeating the described steps Each time you inverse assemble a block of memory the analyzer will keep the alignment information for that block Pressing the Align key clears the alignment information from t...

Page 33: ... code Displayed if the inverse assembler encounters an illegal instruction Reserved Opcode Displayed if the inverse assembler encounters a reserved coprocessor instruction Incomplete Opcode Displayed if the inverse assembler cannot acquire all words of a multi word instruction s Displayed if the inverse assembler cannot find a complete operand field for an instruction Prefetch activity or storage ...

Page 34: ...3 Preprocessor Interface Hardware Reference ...

Page 35: ...ference This chapter contains reference information on the HP E2470A hardware including product electrical and environmental characteristics signal mapping a brief theory of operation circuit board dimensions and repair information 3 2 ...

Page 36: ...for each pod used for timing measurements or the GP General Purpose probes supplied with your logic analyzer Electrical Characteristics Power Requirements 250 mA typical 5 V supplied by logic analyzer Signal Line Loading 8 pF maximum on all signals except CLKOUT which has 40 pF maximum Environmental Characteristics Temperature Operating 0 to 55 degrees C 32 to 131 degrees F Nonoperating 40 to 75 d...

Page 37: ...e delayed until a clock after any bus cycle completes In turn all state information must be latched Signals that could be used in address calculations including address chip selects and function codes are latched at the same time Although bus control signals could be active and latched with this group BGACK is the only signal of importance and if asserted prevents the microcontroller from controll...

Page 38: ...Block Diagram Preprocessor Interface Hardware Reference Theory of Operation and Clocking 3 5 ...

Page 39: ...The following timing diagram shows the time at which address and data are sampled Timing Diagram Preprocessor Interface Hardware Reference Theory of Operation and Clocking 3 6 ...

Page 40: ...Definition The following table defines the state connectors the logic analyzer bit assignments and the label sublabel s to which a signal belongs This table aids in reconfiguring the logic analyzer to match a particular microcontroller configuration TABLE 3 1 E2470A State Connector Signal List SIGNAL NAME E2470A STATE CONNECTOR PIN ANALYZER BIT STATE LABEL STATE SUBLABEL STATE SUBLABEL DATA0 1 37 ...

Page 41: ... ADDR ADDR12 3 13 3 12 ADDR ADDR13 3 11 3 13 ADDR ADDR14 3 9 3 14 ADDR ADDR15 3 7 3 15 ADDR ADDR16 4 37 4 0 ADDR ADDR17 4 35 4 1 ADDR ADDR18 4 33 4 2 ADDR ADDR19 CS6 4 31 4 3 ADDR CSx ADDR20 CS7 4 29 4 4 ADDR CSx ADDR21 CS8 4 27 4 5 ADDR CSx ADDR22 CS9 4 25 4 6 ADDR CSx ADDR23 CS10 4 23 4 7 ADDR CSx CSBOOT 4 21 4 8 ADDR_B CSx BR CS0 4 19 4 9 ADDR_B BusArb CSx BG CSM 4 17 4 10 ADDR_B BusArb CSx BGA...

Page 42: ... STAT PFlush SIZ0 2 29 2 4 STAT SIZx SIZ1 2 27 2 5 STAT SIZx SIZE0_VALID 2 25 2 6 STAT SIZE1_VALID 2 23 2 7 STAT QUALIFIED_ DSACK0 2 21 2 8 STAT DSACKx QUALIFIED_ DSACK1 2 19 2 9 STAT DSACKx BERR 2 17 2 10 STAT BErr BUS_ARB_ INVALID 2 15 2 11 STAT FCx_INVALID 2 13 2 12 STAT A19 A23_ INVALID 2 11 2 13 STAT FREEZE QUOT 2 9 2 14 STAT Freeze BKPT DSCLK 2 7 2 15 STAT Bkpt Preprocessor Interface Hardwar...

Page 43: ... 16 1 3 DATA DATA4 1 15 1 4 DATA DATA5 1 14 1 5 DATA DATA6 1 13 1 6 DATA DATA7 1 12 1 7 DATA DATA8 1 11 1 8 DATA DATA9 1 10 1 9 DATA DATA10 1 9 1 10 DATA DATA11 1 8 1 11 DATA DATA12 1 7 1 12 DATA DATA13 1 6 1 13 DATA DATA14 1 5 1 14 DATA DATA15 1 4 1 15 DATA ADDR0 2 19 2 0 ADDR ADDR1 2 18 2 1 ADDR ADDR2 2 17 2 2 ADDR ADDR3 2 16 2 3 ADDR ADDR4 2 15 2 4 ADDR ADDR5 2 14 2 5 ADDR ADDR6 2 13 2 6 ADDR A...

Page 44: ... 3 5 ADDR ADDR22 CS9 3 13 3 6 ADDR ADDR23 CS10 3 12 3 7 ADDR CSBOOT 3 11 3 8 CSX BR CS0 3 10 3 9 BUSARB BG CSM 3 9 3 10 BUSARB BGACK CSE 3 8 3 11 BUSARB FC0 CS3 3 7 3 12 FCX FC1 3 6 3 13 FCX FC2 CS5 3 5 3 14 FCX unused 3 4 3 15 AVEC 4 19 4 0 AVEC R W 4 18 4 1 R W PIPE1 DSI 4 17 4 2 IPIPEx PIPE0 DSO 4 16 4 3 IPIPEx SIZ0 4 15 4 4 SIZx SIZ1 4 14 4 5 SIZx RESET 4 13 4 6 RESET HALT 4 12 4 7 HALT DSACK0...

Page 45: ...C TXDA 5 12 5 7 IRQ IntReq7 5 11 5 8 IRQ IntReq6 5 10 5 9 IRQ IntReq5 5 9 5 10 IRQ IntReq4 5 8 5 11 IRQ IntReq3 5 7 5 12 IRQ IntReq2 5 6 5 13 IRQ IntReq1 5 5 5 14 IRQ ModClk 5 4 5 15 ModClk PGP0 IC1 6 19 6 0 PGP PGP1 IC2 6 18 6 1 PGP PGP2 IC3 6 17 6 2 PGP PGP3 OC1 6 16 6 3 PGP PGP4 OC2 OC1 6 15 6 4 PGP PGP5 OC3 OC1 6 14 6 5 PGP PGP6 OC4 OC1 6 13 6 6 PGP PGP7 IC4 OC5 OC1 6 12 6 7 PGP not used 6 11 ...

Page 46: ... 6 15 ClkOut TP0 5 19 5 0 TPU TP1 5 18 5 1 TPU TP2 5 17 5 2 TPU TP3 5 16 5 3 TPU TP4 5 15 5 4 TPU TP5 5 14 5 5 TPU TP6 5 13 5 6 TPU TP7 5 12 5 7 TPU TP8 5 11 5 8 TPU TP9 5 10 5 9 TPU TP10 5 9 5 10 TPU TP11 5 8 5 11 TPU TP12 5 7 5 12 TPU TP13 5 6 5 13 TPU TP14 5 5 5 14 TPU TP15 5 4 5 15 TPU Preprocessor Interface Hardware Reference Timing Connector Signal Definition 3 13 ...

Page 47: ...D E2470A PGA PIN E2470A TIMING POD 1 VRH C2 2 PADA5 AN5 D1 3 PADA4 AN4 D2 4 PADA3 AN3 D3 5 PADA2 AN2 D4 6 PADA1 AN0 D5 7 PADA0 AN1 E1 8 VSSA E2 9 VDDA E3 10 VDDE1 E4 11 VSSE1 X E5 12 ADDR1 F1 2 13 ADDR2 F2 2 14 ADDR3 PB0 F3 2 15 ADDR4 PB1 F4 2 16 ADDR5 PB2 F5 2 17 ADDR6 PB3 G1 2 18 ADDR7 PB4 G2 2 19 ADDR8 PB5 G3 2 20 ADDR9 PB6 G4 2 21 VSSI G5 22 ADDR10 PB10 G6 2 23 ADDR11 PA0 H1 2 24 ADDR12 PA1 H2...

Page 48: ...6 5 35 SCK PMC0 K2 5 36 MISO PMC2 K1 5 37 TXDA PMC7 K3 5 38 RXDA PMC6 L1 5 39 TXDB PMC5 L2 5 40 VDDE4 41 VSSE4 X 42 RXDB PMC4 P4 5 47 TPUCH0 N4 7 48 TPUCH1 M4 7 45 TPUCH2 L 4 7 46 TPUCH3 K 4 7 47 VDDE L3 48 VSSE X N 3 49 TPUCH4 M 5 7 50 TPUCH5 L 5 7 51 TPUCH6 K5 7 52 TPUCH7 P 6 7 53 TPUCH8 N 6 7 54 TPUCH9 M 6 7 55 TPUCH10 L 6 7 56 TPUCH11 K 6 7 Preprocessor Interface Hardware Reference PQFP to PGA...

Page 49: ...7 VDOSYN K 8 68 EXTAL J 8 69 VSSI X P 9 70 VDDI 71 XFC M9 72 VDDE P 5 73 VSSI P9 74 CLKOUT J9 75 VSSE X P10 76 RESET N10 4 77 HALT M10 4 78 BERR P11 4 79 FREEZ QUOT N11 4 80 TSC M11 6 81 IRQ7 PF7 M13 5 82 IRQ6 PF6 L14 5 83 IRQ5 PF5 L13 5 84 IRQ4 PF4 L12 5 85 IRQ3 PF3 L11 5 86 IRQ2 PF2 L10 5 87 IRQ1 PF1 K14 5 88 MODCLK PF0 K13 5 Preprocessor Interface Hardware Reference PQFP to PGA Connector Signal...

Page 50: ...H10 102 DATA15 PG7 H9 1 103 DATA14 PG6 G14 1 104 DATA13 PG5 G13 1 105 DATA12 PG4 G12 1 106 DATA11 PG3 G11 1 107 VSSE7 X G10 108 VDDE7 G9 109 DATA10 PG2 F14 1 110 DATA9 PG1 F13 1 111 DATA8 PG0 F12 1 112 DATA7 PH7 F11 1 113 DATA6 PH6 F10 1 114 DATA5 PH5 F9 1 115 DATA4 PH4 E14 1 116 DATA3 PH3 E13 1 117 DATA2 PH2 E12 1 118 DATA1 PH1 D14 1 119 DATA0 PH0 D13 1 120 VDDE11 D12 121 VSSE11 X 122 CSBOOT A11 ...

Page 51: ...C5 B9 3 134 ADDR22 CS9 PC6 C9 3 135 ADDR23 CS10 PC7 D9 3 136 VDDI 137 VSSI 138 nc 139 BKPT DSCLK C8 4 140 PIPE0 DSO E8 4 141 PIPE1 DSI D8 4 142 VDDE11 143 VSSE11 X 144 PCLK B7 6 145 PWMB C7 6 146 PWMA D7 6 147 PAI E 7 6 148 IC4 OC5 OC1 PGP7 F 7 6 149 OC4 OC1 PGP6 A6 6 150 OC3 OC1 PGP5 B6 6 151 OC4 OC1 PGP4 C6 6 152 OC1 PGP3 D6 6 153 IC3 PGP2 E6 6 154 IC2P GP1 F 6 6 155 IC1P GP0 A5 6 156 VDDE12 Pre...

Page 52: ...d A12 shield A13 shield A14 shield B 1 shield B 2 shield B 3 shield B13 shield B14 shield C 1 shield C 3 shield C12 shield C13 shield C14 shield M 1 shield M 2 shield M 3 shield M12 shield M14 shield N 1 shield N 2 shield N12 shield N13 shield N14 shield P 1 shield P 2 shield P 3 shield P12 Preprocessor Interface Hardware Reference PQFP to PGA Connector Signal Definition 3 19 ...

Page 53: ...68HC16Y1 PIN 68HC16Y1 SIGNAL NAME SYSTEM GROUND E2470A PGA PIN E2470A TIMING POD shield P13 shield P14 Preprocessor Interface Hardware Reference PQFP to PGA Connector Signal Definition 3 20 ...

Page 54: ...ions The following figure gives the dimensions for the preprocessor interface assembly The dimensions are listed in inches and millimeters Dimensions Preprocessor Interface Hardware Reference Circuit Board Dimensions 3 21 ...

Page 55: ...placed if they are damaged or lost Contact your nearest Hewlett Packard Sales Office for further information on servicing the board Table 3 3 Replaceable Parts HP Part Number Description E2470 69501 Circuit board assembly E2470 68701 Inverse assembler disk pouch E5335A 160 pin PQFP to generic PGA Preprocessor Interface Hardware Reference Repair Strategy 3 22 ...

Page 56: ...A If You Have a Problem ...

Page 57: ...along with some possible solutions If you still have difficulty using the analyzer after trying the suggestions in this chapter please contact your local Hewlett Packard service center C AU TI O N When you are working with the analyzer be sure to power down both the analyzer and the target system before disconnecting or connecting cables probes and preprocessors Otherwise you may damage circuitry ...

Page 58: ...ck signals for the state analyzer must meet particular pulse shape and timing requirements Data inputs for the analyzer must meet pulse shape and setup and hold time requirements See Also See Capacitive Loading in this chapter for information on other sources of intermittent data errors Unwanted triggers Unwanted triggers can be caused by instructions that were fetched but not executed Add the pre...

Page 59: ...play it may be that your analysis specification is not correct for the data you want to capture or that the trace memory is only partially filled Check your analysis trigger sequencer specification to ensure that it will capture the events of interest Try stopping the analyzer if the trace list is partially filled this should display the contents of trace memory If You Have a Problem No activity o...

Page 60: ...ted or the cables may not be installed properly or they may not be making electrical contact Ensure that you are following the correct power on sequence for the logic analyzer and target system 1 Power up the analyzer 2 Power up the target system If you power up the target system before you power up the logic analyzer interface circuitry may latch up and prevent proper target system operation Veri...

Page 61: ...re that you have sufficient cooling for the microprocessor Microprocessors such as the i486 Pentium and MC68040 generate substantial heat You should ensure that you have ambient temperature conditions and airflow that meet or exceed the requirements of the microprocessor manufacturer Capacitive loading Excessive capacitive loading can degrade signals resulting in incorrect capture by the logic ana...

Page 62: ... pressing the Invasm key The inverse assembler works from the first line of the trace display If you jump to the middle of a trace and select Invasm prior trace states may not be disassembled correctly If you move to several random places in the trace list and synchronize the disassembly each time the trace disassembly is only guaranteed to be correct for the portion of the trace list disassembled...

Page 63: ...gers remain enabled you should still get inverse assembly It may be incorrect because a portion of the execution trace was not visible to the logic analyzer Verify that storage qualification has not excluded storage of all the needed opcodes and operands Inverse assembler will not load or run You need to ensure that you have the correct system software loaded on your analyzer Ensure that the inver...

Page 64: ...capture a pulse that occurs right after the analyzer s trigger state If the pulse occurs too soon after the analyzer s trigger state the oscilloscope may miss the pulse Adjust the skew in the Intermodule menu You may be able to specify a skew value that enables the event to be captured Change the trigger specification for modules upstream of the one with the problem If you are using a logic analyz...

Page 65: ...nverse Assembler Not Found This error occurs if you rename or delete the inverse assembler file that is attached to the configuration file Ensure that the inverse assembler file is not renamed or deleted and that it is located on the smae flexible disk or in the same directory as the configuration file A 10 ...

Page 66: ...name in the HP 16500A B disk operation menu Selecting Load All will cause incorrect operation when loading most preprocessor interface configuration files See Also Chapter 1 describes how to load configuration files Selected File is Incompatible This occurs when you try to load a configuration file for the wrong module Ensure that you are loading the appropriate configuration file for your logic a...

Page 67: ...er pattern is specified this message indicates that the specified trigger pattern has not occurred Verify that the triggering pattern is correctly set When analyzing microprocessors that fetch only from word aligned addresses if the trigger condition is set to look for an opcode fetch at an address not corresponding to a word boundary the trigger will never be found If You Have a Problem Waiting f...

Page 68: ...cording to Internationaol Safety Requirements To ensure safe operation and to keep the product safe the information cautions and warnings in this user s guide must be heeded In addition note the external markings on the product that are described under Safety Symbols Safety Symbols Instruction manual symbol the product is marked with this symbol when it is necessary for you to refer to the instruc...

Page 69: ...sive remedies Hewlett Packard shall not be liable for any direct indirect special incidental or consequential damages whether based on contract tort or any other legal theory Assistance Product maintenance agreements and other customer assistance agreements are available for Hewlett Packard products For any assistance contact your nearest Hewlett Packard Sales Office Certification Hewlett Packard ...

Page 70: ...______________________________________ ______________________________________________________________________________________________________________ ______________________________________________________________________________________________________________ 8 Which manuals have you used User s Guide User s Reference Programmer s Guide Service Guide 9 Please rate the manuals on the following 4 E...

Page 71: ...Thank you BUSINESS REPLY CARD FIRST CLASS PERMIT NO 1303 COLORADO SPRINGS COLORADO POSTAGE WILL BE PAID BY ADDRESSEE HEWLETT PACKARD Colorado Springs Division Attn Publications Dept P O Box 2197 Colorado Springs Colorado 80901 9959 NO POSTAGE NECESSARY IF MAILED IN THE UNITED STATES FOLD HERE ...

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