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Chapter 5 Input/Output Interfaces

5-4

Compaq Deskpro EX Series of Personal Computers

First Edition – August 2000

5.3

DISKETTE DRIVE INTERFACE

The diskette drive interface supports up to two diskette drives, each of which use a common cable
connected to a standard 34-pin diskette drive connector. All models come standard with a 3.5-inch
1.44-MB diskette drive installed as drive A. The drive designation is determined by which
connector is used on the diskette drive cable. The drive attached to the end connector is drive A
while the drive attached to the second (next to the end) connector) is drive B.

On all models, the diskette drive interface function is integrated into the LPC47B357 super I/O
component. The internal logic of the I/O controller is software-compatible with standard 82077-
type logic. The diskette drive controller has three operational phases in the following order:

♦

Command phase - The controller receives the command from the system.

♦

Execution phase - The controller carries out the command.

♦

Results phase - Status and results data is read back from the controller to the system.

The Command phase consists of several bytes written in series from the CPU to the data register
(3F5h/375h). The first byte identifies the command and the remaining bytes define the parameters
of the command. The Main Status register (3F4h/374h) provides data flow control for the diskette
drive controller and must be polled between each byte transfer during the Command phase.

The Execution phase starts as soon as the last byte of the Command phase is received. An
Execution phase may involve the transfer of data to and from the diskette drive, a mechnical
control function of the drive, or an operation that remains internal to the diskette drive controller.
Data transfers (writes or reads) with the diskette drive controller are by DMA, using the DRQ2 and
DACK2- signals for control.

The Results phase consists of the CPU reading a series of status bytes (from the data register
(3F5h/375h)) that indicate the results of the command. Note that some commands do not have a
Result phase, in which case the Execution phase can be followed by a Command phase.

During periods of inactivity, the diskette drive controller is in a non-operation mode known as the
Idle phase.

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Summary of Contents for Deskpro EX

Page 1: ...Technical Reference Guide For the Compaq Deskpro EX EXS Series of Personal Computers Covering Models Featuring Intel Celeron and Pentium III Processors And the Intel 815 Chipset ...

Page 2: ......

Page 3: ...ll fit into a standard 3 ring binder Provided below is a title block that can be copied and or cut out and placed into a slip or taped onto the edge of the binder Deskpro EX Series Personal Computers Featuring Intel Celeron and Pentium III Processors and the Intel 815 Chipset TRG ...

Page 4: ......

Page 5: ...to send any questions suggestions corrections or comments regarding this document please to the following email address Desktop training feedback Compaq com When responding please state the title and edition of the referenced document ...

Page 6: ......

Page 7: ... described Compaq product no part of this document may be photocopied or reproduced in any form without prior written consent from Compaq Computer Corporation 2000 Compaq Computer Corporation All rights reserved Published in the USA Compaq Deskpro LTE Contura Presario ProLinea Registered U S Patent and Trademark Office Product names mentioned in this document may be trademarks and or registered tr...

Page 8: ...Technical Reference Guide Compaq Deskpro EX Series of Personal Computers First Edition August 2000 ii ...

Page 9: ...2 2 FEATURES AND OPTIONS 2 2 2 2 1 STANDARD FEATURES 2 2 2 2 2 OPTIONS 2 3 2 3 MECHANICAL DESIGN 2 4 2 3 1 CABINET LAYOUTS 2 5 2 3 2 CHASSIS LAYOUTS 2 7 2 3 3 BOARD LAYOUT 2 9 2 4 SYSTEM ARCHITECTURE 2 10 2 4 1 PROCESSORS 2 12 2 4 2 CHIPSET 2 14 2 4 3 SUPPORT COMPONENTS 2 14 2 4 4 SYSTEM MEMORY 2 15 2 4 5 MASS STORAGE 2 15 2 4 6 SERIAL AND PARALLEL INTERFACES 2 15 2 4 7 UNIVERSAL SERIAL BUS INTERF...

Page 10: ...BUTION 4 22 4 6 REAL TIME CLOCK AND CONFIGURATION MEMORY 4 23 4 6 1 CLEARING CMOS 4 23 4 6 2 CMOS ARCHIVE AND RESTORE 4 24 4 6 3 STANDARD CMOS LOCATIONS 4 24 4 7 SYSTEM MANAGEMENT 4 33 4 7 1 SECURITY FUNCTIONS 4 33 4 7 2 POWER MANAGEMENT 4 35 4 7 3 SYSTEM STATUS 4 35 4 7 4 TEMPERATURE SENSING 4 36 4 8 SYSTEM COOLING 4 37 4 9 REGISTER MAP AND MISCELLANEOUS FUNCTIONS 4 38 4 9 1 SYSTEM I O MAP 4 38 4...

Page 11: ...ATA 5 23 5 8 AUDIO SUBSYSTEM 5 24 5 8 1 FUNCTIONAL ANALYSIS 5 24 5 8 2 AC97 AUDIO CONTROLLER 5 26 5 8 3 AC97 LINK BUS 5 26 5 8 4 AUDIO CODEC 5 27 5 8 5 AUDIO PROGRAMMING 5 28 5 8 6 AUDIO SPECIFICATIONS 5 29 5 9 NETWORK SUPPORT 5 30 5 9 1 PCI VER 2 2 SUPPORT 5 30 5 9 2 ALERT ON LAN SUPPORT 5 30 5 9 3 REMOTE SYSTEM ALERT SUPPORT 5 32 CHAPTER 6 EMBEDDED GRAPHICS SUBSYSTEM 6 1 INTRODUCTION 6 1 6 1 1 F...

Page 12: ...EGACY SUPPORT 8 23 A APPENDIX A ERROR MESSAGES AND CODES A 1 INTRODUCTION A 1 A 2 BEEP KEYBOARD LED CODES A 1 A 3 POWER ON SELF TEST POST MESSAGES A 2 A 4 SYSTEM ERROR MESSAGES 1XX XX A 3 A 5 MEMORY ERROR MESSAGES 2XX XX A 4 A 6 KEYBOARD ERROR MESSAGES 30X XX A 4 A 7 PRINTER ERROR MESSAGES 4XX XX A 5 A 8 VIDEO GRAPHICS ERROR MESSAGES 5XX XX A 5 A 9 DISKETTE DRIVE ERROR MESSAGES 6XX XX A 6 A 10 SER...

Page 13: ...OMMANDS C 11 C 2 6 SCAN CODES C 11 C 3 CONNECTORS C 16 APPENDIX D COMPAQ NVIDIA VANTA LT AGP GRAPHICS CARD D 1 D 1 INTRODUCTION D 1 D 2 FUNCTIONAL DESCRIPTION D 2 D 3 DISPLAY MODES D 3 D 4 SOFTWARE SUPPORT INFORMATION D 4 D 5 POWER MANAGEMENT AND CONSUMPTION D 4 D 6 CONNECTORS D 5 D 6 1 MONITOR CONNECTOR D 5 APPENDIX E COMPAQ NVIDIA M64 GRAPHICS CARD E 1 INTRODUCTION E 1 E 2 FUNCTIONAL DESCRIPTION...

Page 14: ...E INTERRUPT PROCESSING BLOCK DIAGRAM 4 15 FIGURE 4 10 CONFIGURATION MEMORY MAP 4 23 FIGURE 4 11 FAN CONTROL BLOCK DIAGRAM 4 37 FIGURE 5 1 40 PIN PRIMARY IDE CONNECTOR ON SYSTEM BOARD 5 3 FIGURE 5 2 34 PIN DISKETTE DRIVE CONNECTOR 5 7 FIGURE 5 3 SERIAL INTERFACE CONNECTOR MALE DB 9 AS VIEWED FROM REAR OF CHASSIS 5 8 FIGURE 5 4 PARALLEL INTERFACE CONNECTOR FEMALE DB 25 AS VIEWED FROM REAR OF CHASSIS...

Page 15: ...SITIONS C 6 FIGURE C 7 7 BUTTON EASY ACCESS KEYBOARD LAYOUT C 7 FIGURE C 8 8 BUTTON EASY ACCESS KEYBOARD LAYOUT C 7 FIGURE C 9 PS 2 KEYBOARD CABLE CONNECTOR MALE C 16 FIGURE C 10 USB KEYBOARD CABLE CONNECTOR MALE C 16 FIGURE D 1 COMPAQ NVIDIA VANTA LT AGP GRAPHICS CARD P N 192174 002 LAYOUT D 1 FIGURE D 2 COMPAQ NVIDIA VANTA LT GRAPHICS CARD BLOCK DIAGRAM D 2 FIGURE D 3 VGA MONITOR CONNECTOR FEMAL...

Page 16: ... 4 13 TABLE 4 7 AGP BUS CONNECTOR PINOUT 4 14 TABLE 4 8 MASKABLE INTERRUPT PRIORITIES AND ASSIGNMENTS 4 16 TABLE 4 9 MASKABLE INTERRUPT CONTROL REGISTERS 4 17 TABLE 4 10 DEFAULT DMA CHANNEL ASSIGNMENTS 4 19 TABLE 4 11 DMA PAGE REGISTER ADDRESSES 4 20 TABLE 4 12 DMA CONTROLLER REGISTERS 4 21 TABLE 4 13 CLOCK GENERATION AND DISTRIBUTION 4 22 TABLE 4 14 CONFIGURATION MEMORY CMOS MAP 4 24 TABLE 4 15 S...

Page 17: ...3 SETUP UTILITY FUNCTIONS 8 6 TABLE 8 4 CLIENT MANAGEMENT FUNCTIONS INT15 8 12 TABLE 8 5 PNP BIOS FUNCTIONS 8 15 TABLE 8 6 APM BIOS FUNCTIONS 8 20 TABLE A 1 BEEP KEYBOARD LED CODES A 1 TABLE A 2 POWER ON SELF TEST POST MESSAGES A 2 TABLE A 3 SYSTEM ERROR MESSAGES A 3 TABLE A 4 MEMORY ERROR MESSAGES A 4 TABLE A 5 KEYBOARD ERROR MESSAGES A 4 TABLE A 6 PRINTER ERROR MESSAGES A 5 TABLE A 7 VIDEO GRAPH...

Page 18: ...s of Personal Computers First Edition August 2000 xii TABLE E 1 NVIDIA M64 2D GRAPHICS DISPLAY MODES E 3 TABLE E 2 MONITOR POWER MANAGEMENT CONDITIONS E 4 TABLE E 3 DB 15 MONITOR CONNECTOR PINOUT E 5 TABLE E 4 MULTIMEDIA INTERFACE CONNECTOR PINOUT E 6 ...

Page 19: ...e power supply assembly The appendices contain general information about standard peripheral devices such as the keyboard 1 1 2 ADDITIONAL INFORMATION SOURCES For more information on chipset components mentioned in this guide refer to the indicated manufacturers documentation which may be available at the following online sources Compaq Computer Corporation http www compaq com Intel Corporation ht...

Page 20: ...etters Signals that are meant to be active asserted low are indicated with a dash immediately following the name 1 3 4 REGISTER NOTATION AND USAGE This guide uses standard Intel naming conventions in discussing the microprocessor s CPU internal registers Registers that are accessed through programmable I O using an indexing scheme are indicated using the following format 03C5 17h Index port Data p...

Page 21: ...ocol ATAPI AT attachment w packet interface extensions AVI audio video interleaved AVGA Advanced VGA BAT Basic assurance test BCD binary coded decimal BIOS basic input output system bis second new revision BitBLT bit block transfer BNC Bayonet Neill Concelman connector bps or b s bits per second BSP Bootstrap processor BTO Built to order CAS column address strobe CD compact disk CD ROM compact dis...

Page 22: ...ental Variable data ExCA Exchangeable Card Architecture FIFO first in first out FL flag register FM frequency modulation FPM fast page mode RAM type FPU Floating point unit numeric or math coprocessor FPS Frames per second ft foot GB gigabyte GMCH Graphics memory controller hub GND ground GPIO general purpose I O GPOC general purpose open collector GART Graphics address re mapping table GUI graphi...

Page 23: ...ler NiCad nickel cadmium NiMH nickel metal hydride NMI non maskable interrupt NRZI Non return to zero inverted ns nanosecond NT nested task flag NTSC National Television Standards Committee NVRAM non volatile random access memory OEM original equipment manufacturer OS operating system PAL 1 programmable array logic 2 phase altering line PC Internet Device PCI peripheral component interconnect PCM ...

Page 24: ...standard parallel port SRAM static RAM SSE Streaming SIMD extensions STN super twist pneumatic SVGA super VGA SW software TAD telephone answering device TAFI Temperature sensing And Fan control Integrated circuit TAM telephone answering machine TCP tape carrier package TF trap flag TFT thin film transistor TIA Telecommunications Information Administration TPE twisted pair ethernet TPI track per in...

Page 25: ...rovide high performance for price conscious businesses This guide also covers Deskpro EXS models which are hardware software packages that provide ready to run solutions for small to medium businesses All models are easily upgradable and expandable to keep pace with the needs of the office enterprise Figure 2 1 Compaq Deskpro EX Series Personal Computers with Monitors This chapter includes the fol...

Page 26: ...skette drive 48x Max CD ROM drive IDE controllers with UATA 66 mode support Hard drive fault prediction One parallel two serial and two USB interfaces APM 1 2 power management support Plug n Play compatible with ESCD support Intelligent Manageability support Energy Star compliant Security features including Flash ROM Boot Block Diskette drive disable boot disable write protect Power on password Ad...

Page 27: ...m Memory PC133 64 MB DIMM non ECC PC133 128 MB DIMM non ECC PC133 256 MB DIMM non ECC Hard drives controllers 10 15 GB or 20 GB UATA 66 hard drive Removeable media drives 8x 4x 32x CD RW drive 10x 40x Max DVD ROM drive LS 120 Super Disk drive PCI DXR DVD Decoder kit Graphics Monitors Compaq P700 17 CRT Compaq P900 19 CRT Compaq P1100 21 CRT Compaq TFT5010 15 Flat Panel Compaq TFT8020 18 Flat Panel...

Page 28: ...ns describe the mechanical physical aspects of the Compaq Deskpro EX Series models CAUTION Voltages are present within the system unit whenever the unit is plugged into a live AC outlet regardless of the Power On condition Always disconnect the power cable from the power outlet and or from the system unit before handling the system unit in any way NOTE The following information is intended primari...

Page 29: ... button 2 Power LED 3 Hard drive activity LED 4 CD ROM drive headphone jack 5 CD ROM drive volume control 6 CD ROM drive activity LED 7 CD ROM drive door open close button 8 1 44 MB diskette drive activity LED 9 1 44 MB diskette drive eject button Figure 2 2 Compaq Deskpro EX Series Front Views 2 4 1 7 5 3 6 Desktop DT 5 2 1 3 6 4 7 8 8 9 Minitower MT 2 3 1 4 7 8 5 9 6 ...

Page 30: ...onnector 4 PS 2 mouse I F connector 5 USB I F connectors top port B bot port A 6 Parallel I F connector 7 Serial port A connector 8 Serial port B connector 9 Monitor connector 10 Monitor connector models w NVIDIA AGP card 11 Headphone Line Out jack 12 Line In jack 13 Microphone In jack Figure 2 3 Compaq Deskpro EX Series Rear Views Desktop DT 2 1 6 9 11 12 3 4 5 7 8 10 13 1 5 4 2 3 6 10 12 11 7 8 ...

Page 31: ...nd all socketed system board components Quick removal of drive and power supply assemblies Mounting space for a µATX type system board Two 5 inch drive bays and two 3 inch drive bays NOTES 1 May be populated with AGP graphics card or optional GPA AIMM card depending on configuration 2 Auxiliary chassis fan installed on systems with 933 MHz or faster processor Figure 2 4 Compaq Deskpro EX Desktop D...

Page 32: ...s and all socketed system board components Space for either a µATX or full ATX type system board NOTES 1 Auxiliary chassis fan installed on systems with 933 MHz or faster processor 2 May be populated with graphics card or optional GPA AIMM card depending on configuration Figure 2 5 Compaq Deskpro EX Minitower MT Chassis Layout Side View Front Back Power Supply Drive Bays System Board Auxiliary Cha...

Page 33: ... port B connector 18 Secondary IDE connector 6 Audio Mic In Line In HP Out connectors 19 CMOS clear memory button 7 Monitor connector 20 Power Button LED connector 1 8 Parallel port connector 21 Password jumper 2 9 Serial port A connector 22 Processor fan header 10 Top USB port B Bottom USB port A 23 AOL SOS connector 11 Top Mouse Bottom Kybd connector 24 PCI slot connectors 12 Processor socket 25...

Page 34: ... III or Celeron processor with an FSB speed of either 66 100 or 133 MHz The GMCH also includes an SDRAM controller supporting one or two PC133 DIMMs The 82815 GMCH includes a i740 equivalent AGP 4X graphics controller that is implemented in the embedded graphics configuration while enhanced performance configurations use an NVIDIA graphics controller AGP card All systems feature legacy PC audio su...

Page 35: ...47B357 I O Controller Serial I F 2 Parallel I F Keyboard Mouse I F Diskette I F 33 MHz 32 Bit PCI Bus IDE Hard Drive 815 Chipset LPC Bus Hub Link Bus PCI Slots Pentium III Or Celeron Processor 82815 GMCH SDRAM System Memory PC100 133 Memory Bus 66 100 133 MHz FSB SDRAM Cntlr Audio Subsystem AC 97 Audio Bus Beep Audio CD Audio RGB NVIDIA Graphics Cntlr Card AGP 4X I F Monitor Monitor Optional 4 MB ...

Page 36: ...GA370 socket allows easy changing upgrading of the processor Raising the Lock Unlock handle of the socket in the vertical position allows the processor package to be removed or inserted into the socket Lowering the Lock Unlock handle in the down horizontal position locks the processor package in place These systems support processors fitted with passive heat sink or processor fitted with a heat si...

Page 37: ...t level cache On die full speed 128 KB ECC second level cache 2 4 1 2 Pentium III Processor The Intel Pentium III processor offers maximum performance for select Compaq Deskpros The Pentium III processor is compatible with software written for Celeron Pentium II Pentium MMX Pentium and x86 processors Featuring a Pentium type core architecture with processing speeds of up to 933 MHz and a 133 MHz f...

Page 38: ... RTC CMOS IRQ controller Power management logic USB I F 8259 or I O APIC interrupt processing 82802 FWH Loaded with Compaq BIOS Random number generator 2 4 3 SUPPORT COMPONENTS Input output functions not provided by the chipset are handled by other support components Some of these components also provide housekeeping and various other functions as well Table 2 3 shows the functions provided by the...

Page 39: ...II technology that tests drive data during periods of drive inactivity for corruption All systems provide two one primary one secondary PCI bus mastering Enhanced IDE EIDE controllers integrated into the chipset Each controller provides UATA 66 support for two drives for a total of four IDE devices form factor limitations notwithstanding 2 4 6 SERIAL AND PARALLEL INTERFACES All models include two ...

Page 40: ... 4 Graphics Subsystem Comparison Table 2 4 Graphics Subsystem Comparison Integrated 815 Graphics Controller NVIDIA Vanta LT Graphics Card NVIDIA M64 Graphics Card Controller Type i740 equiv Vanta Cntlr M64 Bus Type AGP 4X AGP 2X AGP 4X Local Memory DVMT 1 8 MB SDRAM 16 or 32 MB SDRAM Memory Speed 100 MHz 100 MHz 133 MHz Maximum Res of colors 2 1600 x 1200 256 1600 x 1200 65K 16 MB 1600 x 1200 65K ...

Page 41: ...Table 2 5 Environmental Specifications Table 2 5 Environmental Specifications Factory Configuration Parameter Operating Nonoperating Ambient Air Temperature 50o to 95o F 10o to 35o C max rate of change 10 C Hr 24o to 140o F 30o to 60o C max rate of change 20 C Hr Shock w o damage 5 Gs 1 20 Gs 1 Vibration 0 000215 G2 Hz 10 300 Hz 0 0005 G2 Hz 10 500 Hz Humidity 10 90 Rh 28o C max wet bulb temperatu...

Page 42: ... A NOTES 1 System weight may vary depending on installed drives peripherals 2 Assumes reasonable article s such as a display monitor and or another system unit Table 2 8 Diskette Drive Specifications Table 2 8 Diskette Drive Specifications Compaq SP 179161 001 Parameter Measurement Media Type 3 5 in 1 44 MB 720 KB diskette Height 1 3 bay 1 in Bytes per Sector 512 Sectors per Track High Density Low...

Page 43: ... Time Random Full Stroke 100 ms 150 ms Audio Output Level 0 7 Vrms Cache Buffer 128 KB Table 2 10 Hard Drive Specifications Table 2 10 Hard Drive Specifications Parameter 10 0 GB 15 0 GB 20 0 GB Drive Size 3 5 3 5 5 25 Interface UATA 66 UATA 66 UATA 66 Drive Protection System Support Yes Yes Yes Transfer Rate max 66 6 MB s 66 6 MB s 100 MB s 1 Typical Seek Time w settling 1 Single Track Average Fu...

Page 44: ...Chapter 2 System Overview Compaq Deskpro EX Series of Personal Computers First Edition August 2000 2 20 This page is intentionally blank ...

Page 45: ...chipset Figure 3 1 Each system supports one or two SDRAM DIMMs and implements the 82815 GMCH s integrated i740 3D graphics controller covered in Chapter 6 Figure 3 1 Processor Memory Subsystem Architecture This chapter includes the following topics Processor 3 2 page 3 2 Memory subsystem 3 3 page 3 5 Subsystem configuration 3 4 page 3 8 Processor 64 Bit FSB Cntl 133 MHz Memory Bus DIMM In Socket X...

Page 46: ...omputing intensive loops that can take up as much as 90 percent of the CPU s execution time Using a parallel processing technique called single instruction multiple data SIMD MMX logic processes data 64 bits at a time Specific applications that can benefit from MMX technology include 2D 3D graphics audio speech recognition video codecs and data compression Celeron processors operating at 566 MHz a...

Page 47: ...Pentium III 733 1 733 MHz 133 MHz 1 65 Pentium III 800 1 800 MHz 133 MHz 1 65 Pentium III 866 1 866 MHz 133 MHz 1 65 Pentium III 933 1 933 MHz 133 MHz 1 65 NOTE 1 Standard configuration processor The Pentium III processor is software compatible with Celeron Pentium II Pentium MMX Pentium and x86 processors The Pentium III processor also features 70 FPU based streaming SIMD extensions SSE that when...

Page 48: ... heat sink will likely result in a thermal condition Although the system is designed to detect thermal conditions and automatically shut down such a condition could still result in damage to the processor component Refer to the applicable Maintenance and Service Guide for detailed processor installation instructions Upgrading the processor may require the connection of a power cable from the proce...

Page 49: ...cy CL 2 or 3 Data access time clock to data out of 9 0 ns The SPD format supported by these systems complies with the JEDEC specification for 128 byte EEPROMs This system also provides support for 256 byte EEPROMs to include additional Compaq added features such as part number and serial number The SPD format as supported in this system SPD rev 1 is shown in Table 3 3 The key SPD bytes that BIOS c...

Page 50: ...EM Specific Data 8 17 No of Banks For Each Mem Device 4 126 Intel frequency chk 18 CAS Latencies Supported 4 127 Reserved 19 CS Latency 4 128 131 Compaq header CPQ1 9 20 Write Latency 4 132 Header checksum 9 21 DIMM Attributes 133 145 Unit serial number 9 10 22 Memory Device Attributes 146 DIMM ID 9 11 23 Min CLK Cycle Time at CL X 1 7 147 Checksum 9 24 Max Acc Time From CLK CL X 1 7 Reserved 9 NO...

Page 51: ...st PCI Memory Expansion 496 MB FFFF FFFFh 1 MB Graphics SMRAM RAM 128 KB System BIOS Area 64 KB Fixed Mem Area 128 KB Base Memory 512 KB Extended BIOS Area 64 KB Extended Memory 15 MB FFE0 0000h 0100 0000h 00FF FFFFh 0010 0000h 000F 0000h 000E FFFFh 000F FFFFh 0000 0000h 0007 FFFFh 0008 0000h 0009 FFFFh 000B FFFFh 000A 0000h 512 KB 640 KB 16 MB 4 GB Host PCI ISA Area DOS Compatibility Area Option ...

Page 52: ...th 55h 04 05h Command 0006h 70h Multi Transaction Timer 00h 06 07h Status 1 71h CPU Latency Timer 10h 08h Revision ID 72h SMRAM Control 02h 0A 0Bh Class Code 90h Error Command 00h 0Dh Latency Timer 00h 91h Error Status Register 0 00h 0Eh Header Type 00h 92h Error Status Register 1 00h 10 13h Aperture Base Config 2 93h Reset Control 00h 50 51h PAC Config Reg 00h A0 A3h AGP Capability Identifier N A...

Page 53: ...stem resources 4 4 page 4 15 System clock distribution 4 5 page 4 22 Real time clock and configuration memory 4 6 page 4 23 System management 4 7 page 4 33 System cooling 4 8 page 4 37 Register map and miscellaneous functions 4 8 page 4 38 This chapter covers functions provided by off the shelf chipsets and therefore describes only basic aspects of these functions as well as information unique to ...

Page 54: ...nd ICH are organized as multiple devices A function is defined as the end source or target of the bus transaction A device may contain one or more functions In the standard configuration these systems use a hierarchy of three PCI buses Figure 4 1 The PCI bus 0 is internal to the 815 chipset components and is not physically accessible The AGP bus that services the AGP slot or resident AGP controlle...

Page 55: ...incrementing mode In burst mode subsequent data phases are conducted a dword at a time with addressing assumed to increment accordingly four bytes at a time 4 2 1 2 Configuration Cycles Devices on the PCI bus must comply with PCI protocol that allows configuration of that device by software In this system configuration mechanism 1 as described in the PCI Local Bus specification Rev 2 1 is employed...

Page 56: ...gure 4 2 Configuration Cycle Table 4 1 shows the standard configuration of device numbers and IDSEL connections for components and slots residing on a PCI bus Table 4 1 PCI Device Configuration Access Table 4 1 PCI Component Configuration Access PCI Component Function Device PCI Bus IDSEL Wired to 82815 GMCH Memory Controller AGP Bridge i740 Graphics Controller 0 0 0 0 00h 1 01h 2 02h 0 0 0 AGP sl...

Page 57: ...ontroller AC97 Audio Controller AC97 Modem Controller 8086h 8086h 8086h 8086h 8086h 8086h 8086h 2418h 2410h 2411h 2412h 2413h 2415h 2416h Data required by PCI protocol Configuration Space Header PCI Configuration Space Type 1 Class Code Command 31 24 23 16 15 8 7 0 Revision ID Vendor ID Status Device ID Expansion ROM Base Address Reserved Prefetchable Limit Upper 32 Bits Prefetch Mem Limit Prefetc...

Page 58: ...ss phase of the transaction with a target If the PCI device already owns the bus a request is not needed and the device can simply assert FRAME and conduct the transaction Table 4 3 shows the grant and request signals assignments for the devices on the PCI bus Table 4 3 PCI Bus Mastering Devices Table 4 3 PCI Bus Mastering Devices REQ GNT Line Device REQ0 GNT0 PCI Connector Slot 1 REQ1 GNT1 PCI Co...

Page 59: ...Interface Specification rev 1 0 The PCI Power Management Enable PME signal is supported by the chipset and allows compliant PCI and AGP peripherals to initiate the power management routine 4 2 6 PCI SUB BUSSES The chipset implements two data busses that are supplementary in operation to the PCI bus 4 2 6 1 Hub Link Bus The chipset implements a Hub Link bus between the GMCH and the ICH The Hub Link...

Page 60: ...Register Reset Value 00 01h Vendor ID 8086h 8Ah Device 31 Error Status 00h 02 03h Device ID 2410h 90 91h PCI DMA Configuration 0000h 04 05h Command 000Fh A0 CFh Power Management 06 07h Status 0280h D0 D3h General Control 0 s 08h Revision ID 00h D4 D7h General Status F00h 0A 0Bh Class Code 0106h D8h RTC Configuration 00h 0Eh Header Type 80h E0h LPC COM Port Dec Range 00h 40 43h ACPI Base Address 1 ...

Page 61: ...72 AD57 GND 11 PRSNT2 Reserved 42 SERR GND 73 GND AD56 12 GND GND 43 3 3 VDC PAR 74 AD55 AD54 13 GND GND 44 C BE1 AD15 75 AD53 5 VDC 14 RSVD 3 3 AUX 45 AD14 3 3 VDC 76 GND AD52 15 GND RST 46 GND AD13 77 AD51 AD50 16 CLK 5 VDC 47 AD12 AD11 78 AD49 GND 17 GND GNT 48 AD10 GND 79 5 VDC AD48 18 REQ GND 49 GND AD09 80 AD47 AD46 19 5 VDC PME 50 Key Key 81 AD45 GND 20 AD31 AD30 51 Key Key 82 GND AD44 21 A...

Page 62: ... handling operation is initiated AGP defined protocols take effect The AGP graphics adapter acts generally as the AGP master but can also behave as a PCI target during fast writes from the GMCH Key differences between the AGP interface and the PCI interface are as follows Address phase and associated data transfer phase are disconnected transactions Addressing and data transferring occur as contig...

Page 63: ... Transfers Data transfers use the AD lines and occur as the result of data requests described previously Each transaction resulting from a request involves at least eight bytes requiring the 32 AD lines to handle at least two transfers per request The 82815 GMCH supports three transfer rates 1X 2X and 4X Regardless of the rate used the speed of the bus clock is constant at 66 MHz The following sub...

Page 64: ...sfers may be 3 3 or 1 5 VDC Figure 4 6 AGP 2X Data Transfer Peak Transfer Rate 532 MB s AGP 4X Transfers The AGP 4X transfer rate allows sixteen bytes of data to be transferred in one clock cycle As in 2X transfers the 66 MHz CLK signal is used only for qualifying control signals while strobe signals are used to latch each 4 byte transfer on the AD lines As shown in Figure 4 7 4 byte block DnA is ...

Page 65: ... 6 PCI AGP Bridge Configuration Registers MCH Function 1 Table 4 6 PCI AGP Bridge Function Configuration Registers GMCH Function 1 PCI Config Addr Register Reset Value PCI Config Addr Register Reset Value 00 01h Vendor ID 8086h 1Bh Sec Master Latency Timer 00h 02 03h Device ID 1131h 1Ch I O Base Address F0h 04 05h Command 0000h 1Dh I O Limit Address 00h 06 07h Status 0020h 1E 1Fh Sec PCI PCI Statu...

Page 66: ... PAD15 CBE1 08 GNT REQ 30 PAD24 PAD25 52 VDDQ VDDQ 09 VDD3 VDD3 31 GND GND 53 PAD13 PAD14 10 ST1 ST0 32 AD_STB1 AD_STB1 54 PAD11 PAD12 11 NC ST2 33 CBE3 PAD23 55 GND GND 12 PIPE RBF 34 VDDQ VDDQ 56 PAD09 PAD10 13 GND GND 35 PAD22 PAD21 57 CBE0 PAD08 14 WBF NC 36 PAD20 PAD19 58 VDDQ VDDQ 15 SBA1 SBA0 37 GND GND 59 AD_STB0 AD_STB0 16 VDD3 VDD3 38 PAD18 PAD17 60 PAD06 PAD07 17 SBA3 SBA2 39 PAD16 CBE2...

Page 67: ...a hardware generated signal used by peripheral functions within the system to get the attention of the microprocessor Peripheral functions produce a unique INTA H PCI or IRQ0 15 ISA signal that is routed to interrupt processing logic that asserts the interrupt INTR input to the microprocessor The microprocessor halts execution to determine the source of the interrupt and then services the peripher...

Page 68: ...rt COM1 13 IRQ5 Unused 14 IRQ6 Diskette drive controller 15 IRQ7 Parallel port LPT1 IRQ2 NOT AVAILABLE Cascade from interrupt controller 2 APIC Mode The Advanced Programmable Interrupt Controller APIC mode enhances interrupt processing performance with the following advantages Eliminating the processor s interrupt acknowledge cycle by using a separate APIC bus Programmable interrupt priority Addit...

Page 69: ...rol registers follows standard AT type protocol 4 4 1 2 Non Maskable Interrupts Non maskable interrupts cannot be masked inhibited within the microprocessor itself but may be maskable by software using logic external to the microprocessor There are two non maskable interrupt signals the NMI and the SMI These signals have service priority over all maskable interrupts with the SMI having top priorit...

Page 70: ...Signal R W 0 Counter 2 disabled 1 Counter 2 enabled After the active NMI has been processed status bits 7 or 6 are cleared by pulsing bits 2 or 3 respectively The NMI Enable Register 070h 7 is used to enable disable the NMI signal Writing 80h to this register masks generation of the NMI Note that the lower six bits of register at I O port 70h affect RTC operation and should be considered when chan...

Page 71: ...els Table 4 10 Default DMA Channel Assignments Table 4 10 Default DMA Channel Assignments DMA Channel Device ID Controller 1 byte transfers 0 1 2 3 Spare Audio subsystem Diskette drive ECP LPT1 Controller 2 word transfers 4 5 6 7 Cascade for controller 1 Spare Spare Spare All channels in DMA controller 1 operate at a higher priority than those in controller 2 Note that channel 4 is not available f...

Page 72: ...ler 2 word transfers Ch 4 Ch 5 Ch 6 Ch 7 n a 08Bh 089h 08Ah Refresh 08Fh see note NOTE The DMA memory page register for the refresh channel must be programmed with 00h for proper operation The memory address is derived as follows 24 Bit Address Controller 1 Byte Transfers 8 Bit Page Register 8 Bit DMA Controller A23 A16 A15 A00 24 Bit Address Controller 2 Word Transfers 8 Bit Page Register 16 Bit ...

Page 73: ...egisters and their I O port addresses Note that there is a set of registers for each DMA controller Table 4 12 DMA Controller Registers Table 4 12 DMA Controller Registers Register Controller 1 Controller 2 R W Status 008h 0D0h R Command 008h 0D0h W Mode 00Bh 0D6h W Write Single Mask Bit 00Ah 0D4h W Write All Mask Bits 00Fh 0DEh W Software DRQx Request 009h 0D2h W Base and Current Address Ch 0 000...

Page 74: ...oard clock signals and how they are distributed Table 4 13 Clock Generation and Distribution Table 4 13 Clock Generation and Distribution Frequency Source Destination 66 100 or 133 MHz CK Processor GMCH 100 or 133 MHz CK DIMM sockets 66 MHz CK ICH AGP Graphics Cntlr 48 MHz CK ICH I O Cntlr 33 MHz CK Processor ICH PCI Slots 14 31818 MHz Crystal CK Certain clock outputs are turned off during reduced...

Page 75: ... configuration memory to draw power from the power supply The battery is located in a battery holder on the system board and has a life expectancy of four to eight years When the battery has expired it is replaced with a Renata CR2032 or equivalent 3 VDC lithium battery 4 6 1 CLEARING CMOS The contents of configuration memory including the Power On Password can be cleared by the following procedur...

Page 76: ...ation memory locations 0Ah 3Fh These locations are accessible using OUT IN assembly language instructions using port 70 71h or BIOS function INT15 AX E823h Table 4 14 Configuration Memory CMOS Map Table 4 14 Configuration Memory CMOS Map Location Function Location Function 00 0Dh Real time clock 24h System board ID 0Eh Diagnostic status 25h System architecture data 0Fh System reset code 26h Auxili...

Page 77: ...ation 1 Disable time updating for time set 6 Periodic Interrupt Enable Disable 0 Disable 1 Enable interval specified by Register A 5 Alarm Interrupt Enable disable 0 Disabled 1 Enabled 4 End of Update Interrupt Enable Disable 0 Disabled 1 Enabled 3 Reserved read 0 2 Time Date Format Select 0 BCD format 1 Binary format 1 Time Mode 0 12 hour mode 1 24 hour mode 0 Automatic Daylight Savings Time Enab...

Page 78: ...1 720 KB drive 0100 1 44 MB 1 25 MB drive 0110 2 88 MB drive all other values reserved Configuration Byte 12h Hard Drive Type Bit Function 7 4 Primary Controller 1 Hard Drive 1 Type 0000 none 1000 Type 8 0001 Type 1 1001 Type 9 0010 Type 2 1010 Type 10 0011 Type 3 1011 Type 11 0100 Type 4 1100 Type 12 0101 Type 5 1101 Type 13 0110 Type 6 1110 Type 14 0111 Type 7 1111 other use bytes 19h 3 0 Primar...

Page 79: ...nt Installed Default Value standard configuration 03h Bit Function 7 6 No of Diskette Drives Installed 00 1 drive 10 3 drives 01 2 drives 11 4 drives 5 2 Reserved 1 Coprocessor Present 0 Coprocessor not installed 1 Coprocessor installed 0 Diskette Drives Present 0 No diskette drives installed 1 Diskette drive s installed Configuration Bytes 15h and 16h Base Memory Size Default Value 280h Bytes 15h...

Page 80: ...e 1Fh Power Management Functions Default Value 00h Bit Function 7 4 Reserved 3 Slow Processor Clock for Low Power Mode 0 Processor runs at full speed 1 Processor runs at slow speed 2 Reserved 1 Monitor Off Mode 0 Turn monitor power off after 45 minutes in standby 1 Leave monitor power on 0 Energy Saver Mode Indicator Blinking LED 0 Disable 1 Enable Configuration Byte 24h System Board Identificatio...

Page 81: ...t 0 Primary 1 Secondary 0 Diskette I O Port Enable 0 Primary 1 Secondary Configuration Byte 27h Speed Control External Drive Default Value 00h Bit Function 7 Boot Speed 0 Max MHz 1 Fast speed 6 0 Reserved Configuration Byte 28h Expanded and Base Memory IRQ12 Select Default Value 00h Bit Function 7 IRQ12 Select 0 Mouse 1 Expansion bus 6 5 Base Memory Size 00 640 KB 01 512 KB 10 256 KB 11 Invalid 4 ...

Page 82: ...on Byte 2Bh System Inactivity Timeout Default Value 23h Bit Function 7 Reserved 6 5 Power Conservation Boot 00 Reserved 01 PC on 10 PC off 11 Reserved 4 0 System Inactive Timeout Index to SIT system timeout record 00000 Disabled Configuration Byte 2Ch ScreenSave and NUMLOCK Control Default Value 00h Bit Function 7 Reserved 6 Numlock Control 0 Numlock off at power on 1 Numlock on at power on 5 Scre...

Page 83: ...hold the checksum of bytes 10h to 2Dh Configuration Byte 30h 31h Total Extended Memory Tested This location holds the amount of system memory that checked good during the POST Configuration Byte 32h Century This location holds the Century value in a binary coded decimal BCD format Configuration Byte 33h Miscellaneous Flags Default Value 80h Bit Function 7 Memory Above 640 KB 0 No 1 Yes 6 Reserved ...

Page 84: ...sconnected 1 Connected 1 Real Mode Connection 0 Disconnected 1 Connected 0 Power Management Enable 0 Disabled 1 Enabled Configuration Byte 36h ECC POST Test Single Bit Errors Default Value 01h Bit Function 7 Row 7 Error Detect 6 Row 6 Error Detect 5 Row 5 Error Detect 4 Row 4 Error Detect 3 Row 3 Error Detect 2 Row 2 Error Detect 1 Row 1 Error Detect 0 Row 0 Error Detect 0 No single bit error dete...

Page 85: ...ory CMOS and if enabled and then forgotten by the user will require that either the password be cleared preferable solution and described below or the entire CMOS be cleared refer to section 4 6 To clear the password use the following procedure 1 Turn off the system and disconnect the AC power cord from the outlet and or system unit 2 Remove the cover hood as described in the appropriate User Guid...

Page 86: ...ecurity The serial parallel USB and diskette interfaces may be disabled individually through the Setup utility to guard against unauthorized access to a system In addition the ability to write to or boot from a removable media drive such as the diskette drive may be enabled through the Setup utility The disabling of the serial parallel and diskette interfaces are a function of the LPC47B357 I O co...

Page 87: ... in table 4 15 NOTE The LED indications listed in Table 4 15 are valid only for PS 2 type keyboards A USB keyboard will not provide LED status for the listed events although audible beep indications will occur Table 4 15 System Boot ROM Flash Status LED Indications Table 4 15 System Boot ROM Flash Status LED Indications Event NUM Lock LED CAPs Lock LED Scroll Lock LED System memory failure 1 Blink...

Page 88: ...ks green 1 Hz S3 Suspend to RAM Blinks green 1 Hz Blinks green 1 Hz S4 Suspend to disk Blinks green 0 5 Hz Blinks green 0 5 Hz S5 Soft off Off clear Off clear Processor not seated Off clear Steady red CPU thermal shutdown Off clear Blinks red 4 Hz ROM error Off clear Blinks red 1 Hz Power supply crowbar activated Off clear Blinks red 5 Hz System off Off clear Off 4 7 4 TEMPERATURE SENSING The micr...

Page 89: ...esigned to provide optimum cooling with the cover in place Operating the system without the cover may result in a thermal condition of system board components including the processor NOTE 1 R77 and R78 are 0 ohm resisters of which only one will be present Most system boards will have R78 in place to apply 12 VDC to the auxiliary chassis fan System boards in units designated for some European and A...

Page 90: ...oller 00C0 00DFh DMA Controller 2 00F0h Coprocessor error register 0170 0177h IDE Controller 2 active only if standard I O space is enabled for primary drive 01F0 01F7h IDE Controller 1 active only if standard I O space is enabled for secondary drive 0278 027Fh Parallel Port LPT2 02E8 02EFh Serial Port COM4 02F8 02FFh Serial Port COM2 0370 0377h Diskette Drive Controller Secondary Address 0376h ID...

Page 91: ... Bridge 82801 function 0 The GPIO ports are controlled through 64 bytes of I O space that is mapped during POST Table 4 18 lists the utilization of the ICH s GPIO ports in these systems Table 4 18 lists the GPIO registers for the LPC47B357 Table 4 18 82801 ICH GPIO Register Utilization Table 4 18 82801 ICH GPIO Register Utilization GPIO Port Function Direction 0 NC 1 NC 2 NC 3 NC 4 NC 5 NC 6 NC 7 ...

Page 92: ...ct 00h Diskette Drive I F 01h Reserved 02h Reserved 03h Parallel I F 04h Serial I F UART 1 Port A 05h Serial I F UART 2 Port B 06h Reserved 07h Keyboard I F 08h Reserved 09h Reserved 0Ah Runtime Registers GPIO Config 0Bh Reserved 00h 20h Super I O ID Register SID 56h 21h Revision 22h Logical Device Power Control 00h 23h Logical Device Power Management 00h 24h PLL Oscillator Control 04h 25h Reserve...

Page 93: ...GPIO Function Direction GPIO Function Direction 10 Board rev 1 I 42 ICH SCI O 11 Board rev 0 I 43 NC 12 NC 44 Hood Lock NC 13 PME I 45 Hood Unlock NC 14 WOL NC 46 ICH SMI O 15 System ID 4 1 I 60 PCI Slot Reset O 16 Processor Fan sense I 61 AGP Slot Reset O 17 NC 62 PWR Button In I 20 Pri IDE 80 pin Cable Detect I 63 SLP S3 I 21 Sec IDE 80 pin Cable Detect I 64 SLP S5 I 22 NC 65 CPU Changed Removed...

Page 94: ...ar activated Blinks red 0 5 Hz 1 Off System off Off Off NOTE 1 Minitower only Desktop LED will be Off clear I O security The parallel serial and diskette interfaces may be disabled individually by software and the LPC47B357 s disabling register locked If the disabling register is locked a system reset through a cold boot is required to gain access to the disabling Device Disable register Processor...

Page 95: ...page 5 24 Network support 5 9 page 5 30 5 2 ENHANCED IDE INTERFACE The enhanced IDE EIDE interface consists of primary and secondary controllers integrated into the 82801 ICH component of the chipset Two 40 pin IDE connectors one for each controller are included on the system board Each controller can be configured independently for the following modes of operation Programmed I O PIO mode CPU cont...

Page 96: ...0h 06 07h PCI Status 0280h 2E 2Fh Subsystem ID 0000h 08h Revision ID 00h 30 3Fh Reserved 0 s 09h Programming 80h 40 43h Pri Sec IDE Timing 0 s 0Ah Sub Class 01h 44h Slave IDE Timing 00h 0Bh Base Class Code 01h 48h Sync DMA Control 00h 0Dh Master Latency Timer 00h 4A 4Bh Sync DMA Timing 0000h 0Eh Header Type 00h 54h EIDE I O Config Register 00h NOTE Assume unmarked gaps are reserved and or not used...

Page 97: ...D9 Data Bit 9 26 GND Ground 7 DD5 Data Bit 5 27 IORDY I O Channel Ready 3 8 DD10 Data Bit 10 28 CSEL Cable Select 9 DD4 Data Bit 4 29 DAK DMA Acknowledge 10 DD11 Data Bit 11 30 GND Ground 11 DD3 Data Bit 3 31 IRQn Interrupt Request 4 12 DD12 Data Bit 12 32 IO16 16 bit I O 13 DD2 Data Bit 2 33 DA1 Address 1 14 DD13 Data Bit 13 34 DSKPDIAG Pass Diagnostics 15 DD1 Data Bit 1 35 DA0 Address 0 16 DD14 ...

Page 98: ...tus and results data is read back from the controller to the system The Command phase consists of several bytes written in series from the CPU to the data register 3F5h 375h The first byte identifies the command and the remaining bytes define the parameters of the command The Main Status register 3F4h 374h provides data flow control for the diskette drive controller and must be polled between each...

Page 99: ... O register 2Fh this selects the diskette drive I F 3 Write 30h to I O register 2Eh 4 Write 01h to I O register 2Fh this activates the interface Writing AAh to 2Eh deactivates the configuration phase The diskette drive I F configuration registers are listed in the following table Table 5 4 Diskette Drive Controller Configuration Registers Table 5 4 Diskette Drive Interface Configuration Registers ...

Page 100: ...e low 1 0 Drive select 00 Drive 1 01 Drive 2 10 Reserved 11 Tape drive R W 3F3h 373h Tape Drive Register available for compatibility R W 3F4h 374h Main Status Register MSR 7 Request for master host can transfer data active high 6 Transfer direction 0 write 1 read 5 non DMA execution active high 4 Command busy active high 3 2 Reserved 1 0 Drive 1 2 busy active high Data Rate Select Register DRSR 7 ...

Page 101: ...3 GND Ground 20 STEP Drive head track step control 4 MEDIA ID Media identification 21 GND Ground 5 Key 22 WR DATA Write data 6 DRV 4 SEL Drive 4 select 23 GND Ground 7 GND Ground 24 WR ENABLE Enable for WR DATA 8 INDEX Media index detect 25 GND Ground 9 GND Ground 26 TRK 00 Heads at track 00 indicator 10 MTR 1 ON Activates drive motor 27 GND Ground 11 GND Ground 28 WR PRTK Media write protect stat...

Page 102: ...60800 must be set during the configuration phase 5 4 1 RS 232 INTERFACE Each UART is associated with a DB 9 connector that complies with EIA standard RS 232 C The DB 9 connector is shown in the following figure and the pinout of the connector is listed in Table 5 5 Figure 5 3 Serial Interface Connector Male DB 9 as viewed from rear of chassis Table 5 7 DB 9 Serial Connector Pinout Table 5 7 DB 9 S...

Page 103: ...ddress Function R W 30h Activate R W 60h Base Address MSB R W 61h Base Address LSB R W 70h Interrupt Select R W F0h Mode Register R W NOTE Refer to LPC47B357 data sheet for detailed register information 5 4 2 2 Serial Interface Control The BIOS function INT 14 provides basic control of the serial interface The serial interface can be directly controlled by software through the I O mapped registers...

Page 104: ... KB s In the compatible mode CPU write data is simply presented on the eight data lines A CPU read of the parallel port yields the last data byte that was written The following steps define the standard procedure for communicating with a printing device 1 The system checks the Printer Status register If the Busy Paper Out or Printer Fault signals are indicated as being active the system either wai...

Page 105: ...atic generation of addresses and strobes as well as Run Length Encoding RLE decompression is supported by ECP mode The ECP mode includes a bi directional FIFO buffer that can be accessed by the CPU using DMA or programmed I O For the parallel interface to be initialized for ECP mode a negotiation phase is entered to detect whether or not the connected peripheral is compatible with ECP mode If comp...

Page 106: ... Mode Register 2 R W 00h 5 5 4 2 Parallel Interface Control The BIOS function INT 17 provides simplified control of the parallel interface Basic functions such as initialization character printing and printer status are provide by subfunctions of INT 17 The parallel interface is controllable by software through a set of I O mapped registers The number and type of registers available depends on the...

Page 107: ...n Pin Signal Function 1 STB Strobe Write 1 14 LF Line Feed 2 2 D0 Data 0 15 ERR Error 3 3 D1 Data 1 16 INIT Initialize Paper 4 4 D2 Data 2 17 SLCTIN Select In Address Strobe 1 5 D3 Data 3 18 GND Ground 6 D4 Data 4 19 GND Ground 7 D5 Data 5 20 GND Ground 8 D6 Data 6 21 GND Ground 9 D7 Data 7 22 GND Ground 10 ACK Acknowledge Interrupt 1 23 GND Ground 11 BSY Busy Wait 1 24 GND Ground 12 PE Paper End ...

Page 108: ...mmand can request an action or indicate status The keyboard interface uses IRQ1 to get the attention of the CPU The 8042 can send a command to the keyboard at any time When the 8042 wants to send a command the 8042 clamps the clock signal from the keyboard for a minimum of 60 us If the keyboard is transmitting data at that time the transmission is allowed to finish When the 8042 is ready to transm...

Page 109: ...ead ID F2h Instructs the keyboard to stop scanning and return two keyboard ID bytes Set Typematic Rate Display F3h Instructs the keyboard to change typematic rate and delay to specified values Bit 7 Reserved 0 Bits 6 5 Delay Time 00 250 ms 01 500 ms 10 750 ms 11 1000 ms Bits 4 0 Transmission Rate 00000 30 0 ms 00001 26 6 ms 00010 24 0 ms 00011 21 8 ms 11111 2 0 ms Enable F4h Instructs keyboard to ...

Page 110: ...OST and control which occurs during runtime 5 6 3 1 8042 Configuration The keyboard pointing device interface must be enabled and configured for a particular speed before it can be used Enabling and speed parameters of the 8042 logic are affected through the PnP configuration registers of the LPC47B357 I O controller Enabling and speed control are automatically set by the BIOS during POST but can ...

Page 111: ...commands to the 8042 and to receive responses from the 8042 for commands that require a response A read of 60h by the CPU yields the byte held in the output buffer The output buffer holds data that has been received from the keyboard and is to be transferred to the system A CPU write to 60h places a data byte in the input byte buffer and sets the CMD DATA bit of the Status register to DATA The inp...

Page 112: ...e stuck high 03h Data line stuck low 04h Data line stuck high ADh Disable keyboard command sets bit 4 of the 8042 command byte AEh Enable keyboard command clears bit 4 of the 8042 command byte C0h Read input port of the 8042 This command directs the 8042 to transfer the contents of the input port to the output buffer so that they can be read at port 60h C2h Poll Input Port High This command direct...

Page 113: ...ically Figure 5 6 and Table 5 16 show the connector and pinout of the keyboard pointing device interface connectors Figure 5 6 Keyboard or Pointing Device Interface Connector as viewed from rear of chassis Table 5 16 Keyboard Pointing Device Connector Pinout Table 5 16 Keyboard Pointing Device Connector Pinout Pin Signal Description Pin Signal Description 1 DATA Data 4 5 VDC Power 2 NC Not Connect...

Page 114: ... peripherals such as a modem and or a camera may operate satisfactorily As shown in Figure 5 7 the USB interface is provided by the 82801 ICH component and a USB hub component All models provide two front panel accessible series A USB ports For more information on the USB interface refer to the following web site http www usb org Figure 5 7 USB I F Block Diagram 5 7 1 USB DATA FORMATS The USB I F ...

Page 115: ... field that provides destination information required in token packets Frame Field 11 bit field sent in Start of Frame SOF packets that are incremented by the host and sent only at the start of each frame Data Field 0 1023 byte field of data Cyclic Redundancy Check CRC Field 5 or 16 bit field used to check transmission integrity Figure 5 8 USB Packet Formats Data is transferred LSb first A cyclic ...

Page 116: ... 00 01h Vender ID 8086h 0Eh Header Type 00h 02 03h Device ID 2412h 20 23h I O Space Base Address 1 04 05h PCI Command 0000h 2C 2Dh Sub Vender ID 00h 06 07h PCI Status 0280h 3Ch Interrupt Line 00h 08h Revision ID 00h 3Dh Interrupt Pin 03h 09h Programming I F 00h 60h Serial Bus Release No 10h 0Ah Sub Class Code 03h C0 C1h USB Leg Kybd Ms Cntrl 2000h 0Bh Base Class Code 0Ch C4h USB Resume Enable 00h ...

Page 117: ... sixteen feet for full channel 12 MB s operation depending on cable specification see following table Table 5 20 USB Cable Length Data Table 5 20 USB Cable Length Data Conductor Size Resistance Maximum Length 20 AWG 0 036 Ω 16 4 ft 5 00 m 22 AWG 0 057 Ω 9 94 ft 3 03 m 24 AWG 0 091 Ω 6 82 ft 2 08 m 26 AWG 0 145 Ω 4 30 ft 1 31 m 28 AWG 0 232 Ω 2 66 ft 0 81 m NOTE For sub channel 1 5 MB s operation a...

Page 118: ...CH component to access and control an Analog Devices AD1885 Audio Codec which provides the analog to digital ADC and digital to analog DAC conversions as well as the mixing functions All control functions such as volume audio source selection and sampling rate are controlled through software over the PCI bus through the AC97 Audio Controller of the 82801 ICH Control data and digital audio streams ...

Page 119: ... 5 10 Audio Subsystem Functional Block Diagram Headphones Line Out L R HP Out Audio L R AD1885 Audio Codec L R Line In Mic In Audio Bias PCB Piezo Speaker PC Beep Audio AC97 Link Bus 82801 ICH AC 97 Audio Cntlr PCI Bus CD Audio L CD Audio R CD ROM Input P701 1 2 3 4 Aux Audio R Aux Audio L Aux Input P11 1 2 3 4 ...

Page 120: ... transferred in frames synchronized by the 48 KHz SYNC signal which is derived from the clock signal and driven by the audio controller The SYNC signal is high during the frame s tag phase then falls during T17and remains low during the data phase A frame consists of one 16 bit tag slot followed by twelve 20 bit data slots When asserted typically during a power cycle the RESET signal not shown wil...

Page 121: ...d and playback of stereo left and right audio The Sample Rate Generator may be set for sampling frequencies up to 48 KHz Analog audio may then be routed through 3D stereo enhancement processor or bypassed to the output selector SEL The integrated analog mixer provides the computer control console functionality handling multiple audio inputs Figure 5 12 AD1885 Audio Codec Functional Block Diagram A...

Page 122: ... Base Class Code 04h 3Dh Interrupt Pin 02h 0Eh Header Type 00h 3E FFh Reserved 0 s 10 13h Native Audio Mixer Base Addr 1 5 8 5 2 Audio Control The audio subsystem is controlled through a set of indexed registers that physically reside in the audio codec The register addresses are decoded by the audio controller and forwarded to the audio codec over the AC97 Link Bus previously described The audio ...

Page 123: ...dio Subsystem Specifications Paramemter Measurement Sampling Rate 5 51 KHz to 44 KHz Resolution 16 bit Nominal Input Voltage Mic In w 20 db gain Line In 283 Vp p 2 83 Vp p Impedance Mic In Line In Headphone Line Out 1 K ohms nom 10 K ohms min 16 800 ohms min max Signal to Noise Ratio input to Line Out 90 db nom Max Power Output AD1885 codec into 16 ohms Input Gain Attenuation Range 46 5 db Master ...

Page 124: ...t or wake the system from a suspend state NOTE For auxiliary power to be available in a system off condition the system unit must be plugged into a live AC outlet Controlling unit power through a switchable power strip will with the strip turned off disable PME functionality 5 9 2 ALERT ON LAN SUPPORT Alert On LAN AOL support allows a network interface controller NIC card to communicate the occurr...

Page 125: ... and use the SDONEn SBOn signals lines for routing to a NIC card on the PCI bus The ICH s alert message will be the result of a signal from a sensor thermal or CPU state or from the ICH s detection of the system s running status Upon receiving the alert message from the ICH the NIC transmits the appropriate pre constructed message over the network The AOL implementation requirements are as follows...

Page 126: ...iary AOL SOS cable connection with the system board Figure 5 14 Figure 5 14 Remote Sense Alert Implementation Generic Representation In the Remote Sense Alert implementation a NIC card receives event notification directly from the system s thermal sensors and the LPC47B357 I O controller over an AOL SOS cable connection Figure 5 15 During system off conditions the NIC card receives auxiliary power...

Page 127: ...hutdown reported Heartbeat Indication of system s network presence sent approximately every 30 seconds in normal operation The current Remote System Alert implementation requirements are as follows 1 3Com Etherlink 3C905C TX NIC 2 7 pin AOL SOS cable 3 3Com EtherDisk Driver 5 x or later available from Compaq 4 Client side utility software included with driver 5 Server side utility software availab...

Page 128: ...Chapter 5 Input Output Interfaces 5 34 Compaq Deskpro EX Series of Personal Computers First Edition August 2000 This page is intentionally blank ...

Page 129: ...provided in some configurations refer to the appropriate appendix of this guide This chapter covers the following subjects 815 based graphics functional description 6 2 page 6 2 815 based graphics programming 6 3 page 6 5 Monitor power management 6 4 page 6 5 Monitor connector 6 5 page 6 6 Upgrading 815 based graphics 6 6 page 6 6 6 1 1 FEATURE SUMMARY The Intel 815 based graphics subsystem includ...

Page 130: ...a blending Gouraud shading and fogging Figure 6 1 815E Based Graphics Block diagram The controller uses the AGP 4X interface and supports Type 1 Type 2 and Type 3 sideband cycles for a peak transfer rate of 1 MB s The AGP interface also allows the Intel graphics controller to use a portion of system memory for instructions textures and frame display buffering Using a process called Dynamic Video M...

Page 131: ...em memory increasing 3D performance substantially The integrated i740 graphics controller uses through the AGP I F a specific amount of system memory This memory is allocated as follows Video BIOS 512 or 1024 kilobytes An OS report of available system memory will be the total amount installed LESS this amount Graphics Memory Prior to the PV 4 x driver being loaded the graphics memory will be one m...

Page 132: ...5 720 x 576 24 16 7M 60 75 85 800 x 600 8 256 60 70 72 75 85 800 x 600 16 65K 60 70 72 75 85 800 x 600 24 16 7M 60 70 72 75 85 1024 x 768 8 256 60 70 72 75 85 1024 x 768 16 65K 60 70 72 75 85 1024 x 768 24 16 7M 60 70 72 75 85 1152 x 864 8 256 60 70 72 75 85 1152 x 864 16 65K 60 70 72 75 85 1152 x 864 1 24 16 7M 60 70 72 75 85 1280 x 720 8 256 60 75 85 1280 x 720 16 65K 60 75 85 1280 x 720 1 24 16...

Page 133: ...escriptions The graphics controller is controlled through memory mapped registers by the appropriate software driver 6 4 MONITOR POWER MANAGEMENT CONTROL The controller provides monitor power control for monitors that conform to the VESA display power management signaling DPMS protocol This protocol defines different power consumption conditions and uses the HSYNC and VSYNC signals to select a mon...

Page 134: ...NC Not Connected 4 NC Not Connected 12 SDA DDC2 B Data 5 GND Ground 13 HSync Horizontal Sync 6 R GND Red Analog Ground 14 VSync Vertical Sync 7 G GND Blue Analog Ground 15 SCL DDC2 B Clock 8 B GND Green Analog Ground NOTES 1 Fuse automatically resets when excessive load is removed 6 6 UPGRADING 815 BASED GRAPHICS Upgrading the 815 based graphics is facilitated with either the addition of the GPA c...

Page 135: ... Topics covered in this chapter include Power supply assembly control 7 2 page 7 1 Power distribution 7 3 page 7 5 Signal distribution 7 4 page 7 8 7 1 POWER SUPPLY ASSEMBLY CONTROL This system features a power supply assembly that is controlled through programmable logic Figure 7 1 Figure 7 1 Power Distribution and Control Block Diagram Power Supply Assembly 5 VDC 5 VDC 12 VDC 12 VDC 5 AUX Slots ...

Page 136: ...ency 47 63 Hz Steady State Input VAC Current 4 0 A 3 3 VDC Output 5 0 00 A 10 0 A 10 0 A 50 mV 5 VDC Output 5 1 30 A 15 0 A 15 0 A 50 mV 5 AUX Output 4 0 00 A 2 00 A 2 00 A 50 mV 12 VDC Output 5 0 10 A 4 00 A 5 00 A 120 mV 12 VDC Output 10 0 00 A 0 30 A 0 40 A 200 mV NOTE Desktop units are specified as 120 watt systems even though a 145 watt power supply is used Table 7 2 200 Watt Power Supply Ass...

Page 137: ...o de assert the PS On signal ACPI four second counter is not active On ACPI Enabled Pressed and Released Under Four Seconds Negative pulse of which the falling edge causes power control logic to generate SMI set a bit in the SMI source register set a bit for button status and start four second counter Software should clear the button status bit within four seconds and the Suspend state is entered ...

Page 138: ...ion Using an AC power strip to control system unit power will disable wake up event functionality The wake up sequence for each event occurs as follows Wake On LAN The network interface controller NIC can be configured for detection of a Magic Packet and wake the system up from sleep mode through the assertion of the PME signal on the PCI bus Refer to Chapter 5 Network Support for more information...

Page 139: ...bling for the Deskpro EX desktop DT models Conn Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 P1 3 3 3 3 RTN 5 RTN 5 RTN 5 AUX 12 P1 1 3 3 12 RTN PS On RTN RTN RTN 5 5 P5 5 GND GND 12 P2 4 12 GND GND 5 NOTES 1 This row represents pins 11 20 of connector P1 All and values are VDC RTN Return signal ground GND Power ground RS Remote sense FO Fan off Not connected Figure 7 2 Deskpro EX ...

Page 140: ...3 3 RTN 5 RTN 5 RTN Pwr Gd 5 AUX 12 P1 1 3 3 12 RTN PS On RTN RTN RTN 5 5 5 P7 5 GND GND 12 P2 6 12 GND GND 5 NOTES 1 This row represents pins 11 20 of connector P1 All and values are VDC RTN Return signal ground Pwr Gd Power good GND Power ground Not connected Figure 7 3 Deskpro EX MT Power Cable Diagram 1 2 3 4 P2 P6 P7 4 3 2 1 P1 1 2 5 4 3 7 6 12 10 11 8 9 13 14 15 16 17 18 19 20 Power Supply A...

Page 141: ...he processor The possible voltages available are listed as follows VID 3 0 VccP VID 3 0 VccP 0000 2 05 VDC 1000 1 65 VDC 0001 2 00 VDC 1001 1 60 VDC 0010 1 95 VDC 1010 1 55 VDC 0011 1 90 VDC 1011 1 50 VDC 0100 1 85 VDC 1100 1 45 VDC 0101 1 80 VDC 1101 1 40 VDC 0110 1 75 VDC 1110 1 35 VDC 0111 1 70 VDC 1111 1 30 VDC Refer to Chapter 3 for a listing of the core voltages set by the Celeron Table 3 1 ...

Page 142: ...controller 1 See Figure 7 8 for header pinout Figure 7 5 Signal Distribution Diagram Typical Configuration System Board PCA 010833 Power Supply Assembly 3 5 12 VDC IDE Data Cntl IDE Hard Drive 5 12 VDC Conn P1 Pri IDE Conn P20 Sec IDE Conn P21 IDE I F CD ROM Keyboard Mouse Dsk Conn P10 Diskette Drive Conn P5 1 5 12 VDC 5 12 VDC Mouse Kybd Conn J68 AGP Conn J40 Dskt Data Cntl AGP Bus Graphics Contr...

Page 143: ... 4 Audio right channel 2 Ground BIOS Fail 1 Pwr Alert 5 Ground 7 Intrusion 3 2 OS Fail 6 Thermal Alert 4 Fan Alert AOL SOS Header P12 2 PS LED Anode 6 PWR BTN 8 PWR BTN GND 10 System ID 12 GND HD LED Anode 1 16 5 VDC 18 Not connected Power Button LED Header P5 4 PS LED Cathode HD LED Cathode 3 NC 5 Master Reset 7 5 VDC 9 Not connected 11 GND 13 Not connected 15 Not connected 17 ...

Page 144: ...Chapter 7 Power and Signal Distribution Compaq Deskpro EX Series of Personal Computers First Edition August 2000 7 10 This page is intentionally blank ...

Page 145: ...x DMI 2 1 Intel Wired for Management WfM ver 2 2 Alert On LAN AOL and Wake On LAN WOL ACPI and OnNow APM 1 2 SMBIOS 2 3 1 PC98 99 and NetPC Boot Integrity Services BIS Video BIOS on systems with 815E based graphics or integrated nVIDIA AGP graphics Intel PXE boot ROM for the integrated LAN controller BIOS Boot Specification 1 01 Enhanced Disk Drive Specification 3 0 El Torito Bootable CD ROM Forma...

Page 146: ...ver from a failed remote flashing of the system BIOS ROM If the BIOS ROM fails the flash check the boot block code provides the minimum amount of support necessary to allow booting the system from the diskette drive and re flashing the system ROM with a ROMPAQ diskette Note that if an administrator password has been set in the system the boot block will prompt for this password by illuminating the...

Page 147: ...ng and pre viewing Background and foreground colors can be chosen from the selected image s palette The splash screen image requirements are as follows Format Windows bitmap with 4 bit RLE encoding Size 424 width x 320 height pixels Colors 16 4 bits per pixel File Size 64 KB The Image Flash utility can be invoked at a command line for quickly flashing a known image as follows Flashi exe Image_File...

Page 148: ...boot The order can be changed in the ROM based Setup utility accessed by pressing F10 when so prompted during POST 8 3 2 NETWORK BOOT F12 SUPPORT The BIOS supports booting the system to a network server The function is accessed by pressing the F12 key when prompted at the lower right hand corner of the display during POST Booting to a network server allows for such functions as Flashing a ROM on a...

Page 149: ... 133MHz memory operation and program the memory clock and GMCH see note below NOTE The presence of PC133 compliant DIMMS will be indicated by BIOS reading 75h from byte 9 and 64h or 85h from byte 126 For PC133 operation to occur the FSB of the processor must be running at 133 MHz and all installed DIMMs must be PC133 compliant and total no more than four sides Refer to Chapter 3 for more details o...

Page 150: ...t notice Set Time and Date Allows you to set system time and date Save to Diskette Saves system configuration including CMOS to a blank formatted 1 44 MB diskette Restore from Diskette Restores system configuration including CMOS from a diskette Set Defaults and Exit Restores factory default settings which includes clearing any established passwords Ignore Changes and Exit Exits Computer Setup wit...

Page 151: ...e only visible and changeable when the drive translation mode is set to User Multisector Transfers IDE ATA devices only Specifies how many sectors are transferred per multi sector PIO operation Options subject to device capabilities are Disabled 8 and 16 Quiet Drive available on select drives only Performance Allows the drive to operate at maximum performance Quiet will not be displayed if not sup...

Page 152: ...se the arrow keys to select a device and press the Enter key Security Setup Password Allows user to set and enable setup administrator password Note If the setup password is set it is required to change Computer Setup options flash the ROM and make changes to certain plug and play settings under Windows Also this password must be set in order to use some Compaq remote security tools See the Troubl...

Page 153: ...MBR change will be detected by the BIOS during the next reboot and an MBR Security warning message will be displayed Save Master Boot Record Saves a backup copy of the Master Boot Record of the current bootable disk Note Only appears if MBR Security is enabled Restore Master Boot Record Restores the backup Master Boot Record to the current bootable disk Note Only appears if all of the following co...

Page 154: ...aver Options Allows user to set Power button configuration on off or sleep wake under APM enabled operating systems Power LED blink in suspend mode enable disable This option is not available under ACPI enabled operating systems Note Energy Saver Options will not appear if the energy saver mode is disabled Advanced Advanced users only Power On Options Allows user to set POST mode QuickBoot FullBoo...

Page 155: ...ce Options Allows user to set Printer mode bi directional EPP ECP output only Num Lock state at power on off on PME power management event wakeup events enable disable Processor cache enable disable Processor Number enable disable for Pentium III processors ACPI S3 support enable disable S3 is an ACPI advanced configuration and power interface sleep state that some add in hardware options may not ...

Page 156: ...em memory map Real E81Ah Write chassis serial number Real E81Bh Get hard drive threshold Real E81Eh Get hard drive ID Real E827h DIMM EEPROM Access Real 16 32 bit Prot NOTE 1 Industry standard function All 32 bit protected mode functions are accessed by using the industry standard BIOS32 Service Directory Using the service directory involves three steps 1 Locating the service directory 2 Using the...

Page 157: ...PUT EAX Service Identifier CLM EBX 31 8 Reserved EBX 7 0 Must be set to 00h CS Code selector set to encompass the physical page holding entry point as well as the immediately following physical page It must have the same base CS is execute read DS Data selector set to encompass the physical page holding entry point as well as the immediately following physical page It must have the same base DS is...

Page 158: ...IOS function INT 15 AX E813h is a tri modal call that retrieves the VESA extended display identification data EDID Two subfunctions are provided AX E813h BH 00h retrieves the EDID information while AX E813h BH 01h determines the level of DDC support Input AX E813h BH 00 Get EDID BH 01 Get DDC support level If BH 00 then DS E SI Pointer to a buffer 128 bytes where ROM will return block If 32 bit pr...

Page 159: ... functions supported Table 8 5 PnP BIOS Functions Table 8 5 PnP BIOS Functions Function Register 00h Get number of system device nodes 01h Get system device node 02h Set system device node 03h Get event 04h Send message 50h Get SMBIOS Structure Information 51h Get Specific SMBIOS Structure The BIOS call INT 15 AX E841h BH 01h can be used by an application to retrieve the default settings of PnP de...

Page 160: ...mation 1 System Information 3 System Enclosure or Chassis 4 Processor Information 7 Cache Information 8 Port Connector Information 9 System Slots 13 BIOS Language Information 15 System Event Log Information 16 Physical Memory Array 17 Memory Devices 19 Memory Array Mapped Addresses 20 Memory Device Mapped Addresses 31 Boot Integrity Service Entry Point 32 System Boot Information 128 OEM Defined St...

Page 161: ...evice activity If any of the device activity status bits are set at the time of the 1 minute SMI BIOS resets the time out minute countdown The system timer can be configured through the Setup utility for counting down 0 5 10 15 20 30 40 50 60 120 180 or 240 minutes The following devices are checked for activity Keyboard Mouse Serial port s Parallel port IDE primary controller NOTE The secondary co...

Page 162: ... not needed The drives can be in this state with the system still awake 8 7 1 3 Suspend Suspend is not supported in the Independent PM mode 8 7 1 4 System OFF When the system is turned Off but still plugged into a live AC outlet the NIC ICH2 and I O components continue to receive auxiliary power in order to power up as the result of a Magic Packet being received over a network Some NICs are able t...

Page 163: ... Suspend it notifies all APM aware drivers requesting approval for the state change If all drivers approve the BIOS is not involved in this process each is instructed to go to that state then the BIOS is told to go to that state All versions of Windows later versions of OS 2 and Linux support APM The BIOS ROM for these systems support APM 1 2 The APM functions are initialized when the O S loads An...

Page 164: ...able settings etc in effect at the time of the disconnect remain in effect CPU Idle The O S uses this call to tell BIOS that the system is idle CPU Busy Informs the BIOS that the O S has determined that the system is now busy The BIOS should restore the CPU clock rate to full speed Set Power State Sets the system or device specified in the power device ID into the requested power state Enable Disa...

Page 165: ...e access resets the hard drive timer If any of the activity status bits are set when the ROM gets the 1 minute SMI it resets its time out minute countdown according to the value 0 default 5 10 15 20 30 40 50 60 120 180 or 240 minutes selected in the Setup utility F10 IDE Hard Drive Timer During POST an inactivity timer in the IDE hard drive controller is set to control hard drive spin down This ac...

Page 166: ...he system still awake Since the hard drive timer is in the hard drive controller and triggered by drive access the system can be in Standby with the hard drive s still spinning awake System Suspend System Suspend is invoked by pressing and releasing the power switch in under four seconds pressing and holding the switch longer that four seconds will turn the system off The system does not time out ...

Page 167: ...hard drive access will cause it to wake up and resume spinning Since the BIOS returns to the currently running software it is possible for the drive to spin up while the system is in Standby with the screen blanked 8 8 USB LEGACY SUPPORT The BIOS ROM checks the USB port during POST for the presence of a USB keyboard This allows a system with only a USB keyboard to be used during ROM based setup an...

Page 168: ...Chapter 8 BIOS ROM Compaq Deskpro EX Series of Personal Computers First Edition August 2000 8 24 This page is intentionally blank ...

Page 169: ... Keyboard LED Codes Table A 2 Beep Keyboard LED Codes Beeps LED 1 Probable Cause 1 short 2 long NUM lock blinking Base memory failure 1 long 2 short CAP lock blinking Video graphics controller failure 2 long 1 short Scroll lock blinking System failure prior to video initialization 1 long 3 short None Boot block executing None All three blink in sequence Keyboard locked in network mode None NUM loc...

Page 170: ...ailure or stuck key 304 Keyboard System Unit Error Keyboard controller failed self test 404 Parallel Port Address Conflict Current parallel port address is conflicting with another device 510 Slpash Image Corrupt Corrupted splash screen image Restore default image w ROMPAQ 601 Diskette Controller Error Diskette drive removed since previous boot 912 Computer Cover Removed Since Last System Start Up...

Page 171: ...em error 105 06 Port 61 bit 5 not at one 112 08 Unable to enter Auto mode in speed test 105 07 Port 61 bit 3 not at one 112 09 Unable to enter High mode in speed test 105 08 Port 61 bit 1 not at one 112 10 Speed test High mode out of range 105 09 Port 61 bit 0 not at one 112 11 Speed test Auto mode out of range 105 10 Port 61 I O test failed 112 12 Speed test variable speed mode inop 105 11 Port 6...

Page 172: ...ttern test 210 03 Error while restoring memory during increment pattern test 211 01 Memory random pattern test 211 02 Error while saving memory during random memory pattern test 211 03 Error while restoring memory during random memory pattern test 213 xx Incompatible DIMM in slot x 214 xx Noise test failed 215 xx Random address test A 6 KEYBOARD ERROR MESSAGES 30x xx Table A 5 Keyboard Error Messa...

Page 173: ...t failed 402 07 Loopback tst data cntrl reg failed 403 xx Printer pattern test failed 402 08 Interrupt test failed 404 xx Parallel port address conflict 402 09 Interrupt test and data reg failed 498 00 Printer failed or not connected 402 10 Interrupt test and control reg failed A 8 VIDEO GRAPHICS ERROR MESSAGES 5xx xx Table A 7 Video Graphics Error Messages Table A 8 Video Graphics Error Messages ...

Page 174: ...603 xx Diskette drive R W compare test 612 xx Sec diskette drive port addr conflict 604 xx Diskette drive random seek test 694 00 Pin 34 not cut on 360 KB drive 605 xx Diskette drive ID media 697 00 Diskette type error 606 xx Diskette drive speed test 698 00 Drive speed not within limits 607 xx Diskette drive wrap test 699 00 Drive media ID error run Setup 608 xx Diskette drive write protect test ...

Page 175: ...M checksum failure 1205 07 Dial number string too long 1201 17 Tone detect failure 1205 08 Modem time out waiting for remote response 1202 XX Modem internal test 1205 09 Modem exceeded maximum redial limit 1202 01 Time out waiting for SYNC 1 1205 10 Line quality prevented remote response 1202 02 Time out waiting for response 1 1205 11 Modem time out waiting for remote connection 1202 03 Data block...

Page 176: ... 17xx 42 Failed to recalibrate drive 17xx 66 Failed to initialize drive parameter 17xx 43 Failed to format a bad track 17xx 67 Failed to write long 17xx 44 Failed controller diagnostics 17xx 68 Failed to read long 17xx 45 Failed to get drive parameters from ROM 17xx 69 Failed to read drive size 17xx 46 Invalid drive parameters from ROM 17xx 70 Failed translate mode 17xx 47 Failed to park heads 17x...

Page 177: ... failed 1901 xx Tape servo write failed 1905 xx Tape read test failed 1902 xx Tape format failed 1906 xx Tape R W compare test failed 1903 xx Tape drive sensor test failed 1907 xx Tape write protect failed A 15 VIDEO GRAPHICS ERROR MESSAGES 24xx xx Table A 14 Hard Drive Messages Table A 15 Video Graphics Error Messages Message Probable Cause Message Probable Cause 2402 01 Video memory test failed ...

Page 178: ...ek test failed See Table A 18 for additional messages A 18 NETWORK INTERFACE ERROR MESSAGES 60xx xx Table A 17 Network Interface Error Messages Table A 18 Network Interface Error Messages Message Probable Cause Message Probable Cause 6000 xx Pointing device interface error 6054 xx Token ring configuration test failed 6014 xx Ethernet configuration test failed 6056 xx Token ring reset test failed 6...

Page 179: ...e write protected 6nyy 54 BSY stayed busy 6nyy 18 No data detected 6nyy 60 Controller CONFIG 1 register fault 6nyy 21 Drive command aborted 6nyy 61 Controller CONFIG 2 register fault 6nyy 24 Media hard error 6nyy 65 Media not unloaded 6nyy 25 Reserved 6nyy 90 Fan failure 6nyy 30 Controller timed out 6nyy 91 Over temperature condition 6nyy 31 Unrecoverable error 6nyy 92 Side panel not installed 6ny...

Page 180: ...Appendix A Error Messages and Codes Compaq Personal Computers Changed June 2000 A 12 This page is intentionally blank ...

Page 181: ...ex Symbol Dec Hex Symbol Dec Hex Symbol 0 00 Blank 32 20 Space 64 40 96 60 1 01 33 21 65 41 A 97 61 a 2 02 34 22 66 42 B 98 62 b 3 03 35 23 67 43 C 99 63 c 4 04 36 24 68 44 D 100 64 d 5 05 37 25 69 45 E 101 65 e 6 06 38 26 70 46 F 102 66 f 7 07 39 27 71 47 G 103 67 g 8 08 40 28 72 48 H 104 68 h 9 09 41 29 73 49 I 105 69 I 10 0A 42 2A 74 4A J 106 6A j 11 0B 43 2B 75 4B K 107 6B k 12 0C 44 2C 76 4C ...

Page 182: ...5 D7 247 F7 152 98 ÿ 184 B8 216 D8 248 F8 153 99 Ö 185 B9 217 D9 249 F9 154 9A Ü 186 BA 218 DA 250 FA 155 9B 187 BB 219 DB 251 FB 156 9C 188 BC 220 DC 252 FC ⁿ 157 9D 189 BD 221 DD 253 FD 158 9E 190 BE 222 DE 254 FE 159 9F ƒ 191 BF 223 DF 255 FF Blank NOTES 1 Symbol not displayed Keystroke Guide Dec Keystroke s 0 Ctrl 2 1 26 Ctrl A thru Z respectively 27 Ctrl 28 Ctrl 29 Ctrl 30 Ctrl 6 31 Ctrl 32 S...

Page 183: ...is appendix covers the following keyboard types Standard enhanced keyboard Space Saver Windows version keyboard featuring additional keys for specific support of the Windows operating system Easy Access keyboard with additional buttons for internet accessibility functions Only one type of keyboard is supplied with each system Other types may be available as an option NOTE This appendix discusses o...

Page 184: ... after a period of 150 ms to 2 seconds The keyboard undergoes a Basic Assurance Test BAT that checks for shorted keys and basic operation of the keyboard processor The BAT takes from 300 to 500 ms to complete If the keyboard fails the BAT an error code is sent to the CPU and the keyboard is disabled until an input command is received After successful completion of the POR and BAT a completion code...

Page 185: ... verify the state of the signal If a low is detected the keyboard will finish the current transmission if the rising edge of the clock pulse for the parity bit has not occurred The system uses the same timing relationships during reads typically with slightly reduced time periods The enhanced keyboard has three operating modes Mode 1 PC XT compatible Mode 2 PC AT compatible default Mode 3 Select m...

Page 186: ...s additional NRZI encoding and formatting prior to leaving the keyboard to comply with the USB I F specification discussed in chapter 5 of this guide Packets received at the system s USB I F and decoded as originating from the keyboard result in an SMI being generated An SMI handler routine is invoked that decodes the data and transfers the information to the 8042 keyboard controller where normal ...

Page 187: ...02 Key Keyboard Key Positions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 39 32 33 34 35 36 37 38 40 41 42 43 44 45 46 47 48 30 49 50 51 59 60 61 62 63 64 65 66 67 68 69 70 71 75 76 77 78 79 80 81 82 83 84 85 86 92 93 94 95 96 52 53 54 55 56 57 72 73 74 88 89 90 100 58 91 87 97 98 99 101 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28...

Page 188: ...36 37 38 40 41 42 43 44 45 46 47 48 30 49 50 51 59 60 61 62 63 64 65 66 67 68 69 70 71 75 76 77 78 79 80 81 82 83 84 85 86 92 93 94 95 96 52 53 54 55 56 57 72 73 74 88 89 90 100 58 91 87 97 98 99 101 110 111 112 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 39 32 33 34 35 36 37 38 40 41 42 43 44 45 46 47 48 49 50 51 59 60 61 62 63 64 65 66 67 68 69 70 75 76 77 78...

Page 189: ...out shown in Figure C 7 and is available with either a legacy PS 2 type connection or a Universal Serial Bus USB type connection NOTE Main key positions same as Windows Enhanced Figures C 5 or C 6 Figure C 7 7 Button Easy Access Keyboard Layout The 8 button Easy Access Keyboard uses the layout shown in Figure C 8 and uses the PS 2 type connection NOTE Main key positions same as Windows Enhanced Fi...

Page 190: ...Caps Lock key Num Lock The Num Lock key pos 32 when pressed and released invokes a BIOS routine that turns on the num lock LED and shifts into upper case key positions 55 57 72 74 88 90 100 and 101 When pressed and released again these keys revert to the lower case state and the LED is turned off The following keys provide special functions that require specific support by the application Print Sc...

Page 191: ...ults in software interrupt 15h AX 8500h being executed It is up to the application to use or not use this BIOS function The Ctrl and Alt keys can be used together in conjunction with keys in positions 1 13 17 34 39 54 60 71 and 76 84 The Ctrl and Alt key positions used and the sequence in which they are pressed make no difference as long as they are held down at the time the third key is pressed T...

Page 192: ...ommunity Emoney 3 Extra web site Compaq web site 4 Go to favorite web site AltaVista web site 5 Internet search Search 6 Instant answer Travel expenses 7 E commerce Shopping 8 Button Easy Access Keyboard Button Description Default Function 1 Go to favorite web site Customer web site of choice 2 Go to AltaVista AltaVista web site 3 Search AltaVista search engine 4 Check Email Launches user Email 5 ...

Page 193: ...mode the keyboard is operating in Mode 1 In Mode 1 operation the keyboard generates scan codes compatible with 8088 8086 based systems To enter Mode 1 the scan code translation function of the keyboard controller must be disabled Since translation is not performed the scan codes generated in Mode 1 are identical to the codes required by BIOS Mode 1 is initiated by sending command F0h with the 01h ...

Page 194: ...6 21 4 05 85 25 F0 25 25 F0 25 22 5 06 86 2E F0 2E 2E F0 2E 23 6 07 87 36 F0 36 36 F0 36 24 7 08 88 3D F0 3D 3D F0 3D 25 8 09 89 3E F0 3E 3E F0 3E 26 9 0A 8A 46 F0 46 46 F0 46 27 0 0B 8B 45 F0 45 45 F0 45 28 0C 8C 4E F0 4E 4E F0 4E 29 0D 8D 55 F0 55 55 F0 55 30 2B AB 5D F0 5D 5C F0 5C 31 Backspace 0E 8E 66 F0 66 66 F0 66 32 Insert E0 52 E0 D2 E0 AA E0 52 E0 D2 E0 2A 4 E0 2A E0 52 E0 D2 E0 AA 6 E0 ...

Page 195: ...0 51 E0 D1 E0 AA E0 51 E0 D1 E0 2A 4 E0 a E0 51 E0 D1 E0 AA 6 E0 7A E0 F0 7A E0 F0 12 E0 7A E0 F0 7A E0 12 5 E0 12 E0 7A E0 F0 7A E0 F0 12 6 6D F0 6D 55 7 47 C7 6 6C F0 6C 6 6C na 6 56 8 48 C8 6 75 F0 75 6 75 na 6 57 9 49 C9 6 7D F0 7D 6 7D na 6 58 4E CE 6 79 F0 79 6 7C F0 7C 59 Caps Lock 3A BA 58 F0 58 14 F0 14 60 A 1E 9E 1C F0 1C 1C F0 1C 61 S 1F 9F 1B F0 1B 1B F0 1B 62 D 20 A0 23 F0 23 23 F0 23...

Page 196: ... 6B E0 F0 12 E0 6B E0 F0 6B E0 12 5 E0 12 E0 6B E0 F0 6B E0 F0 12 6 61 F0 61 98 E0 50 E0 D0 E0 AA E0 50 E0 D0 E0 2A 4 E0 2A E0 50 E0 D0 E0 AA 6 E0 72 E0 F0 72 E0 F0 12 E0 72 E0 F0 72 E0 12 5 E0 12 E0 72 E0 F0 72 E0 F0 12 6 60 F0 60 99 E0 4D E0 CD E0 AA E0 4D E0 CD E0 2A 4 E0 2A E0 4D E0 CD E0 AA 6 E0 74 E0 F0 74 E0 F0 12 E0 74 E0 F0 74 E0 12 5 E0 12 E0 74 E0 F0 74 E0 F0 12 6 6A F0 6A 100 0 52 D2 6...

Page 197: ... 9 E0 1A E0 9A E0 54 E0 F0 54 99 F0 99 Btn 4 9 E0 1E E0 9E E0 1C E0 F0 1C 95 F0 95 Btn 5 9 E0 13 E0 93 E0 2D E0 F0 2D 0C F0 0C Btn 6 9 E0 14 E0 94 E0 2C E0 F0 2C 9D F0 9D Btn 7 9 E0 15 E0 95 E0 35 E0 F0 35 96 F0 96 Btn 8 9 E0 1B E0 9B E0 5B E0 F0 5B 97 F0 97 NOTES All codes assume Shift Ctrl and Alt keys inactive unless otherwise noted NA Not applicable 1 Shift left key active 2 Ctrl key active 3 ...

Page 198: ...board Systems that do not provide a PS 2 interface will ship with a USB keyboard For a detailed description of the PS 2 and USB interfaces refer to chapter 5 Input Output of this guide The keyboard cable connectors and their pinouts are described in the following figures Pin Function 1 Data 2 Not connected 3 Ground 4 5 VDC 5 Clock 6 Not connected Figure C 9 PS 2 Keyboard Cable Connector Male Pin F...

Page 199: ...his card layout shown in the following figure installs in a system s AGP slot The Compaq NVIDIA Vanta LT AGP Graphics card P N 192174 002 provides high 2D performance as well as 3D capabilities Figure D 1 Compaq NVIDIA Vanta LT AGP Graphics Card P N 192174 002 Layout This appendix covers the following subjects Functional description D 2 page D 2 Display modes D 3 page D 3 Software support informat...

Page 200: ...M frame buffer using 128 bit 100 MHz access AGP 2X transfers with sideband addressing 2D drawing engine providing 3 ROP BtBLT Triangle BLT Stretch BLT Line and poly draw Color expansion Coor conversion and scaling 3D rendering engine with Triangle setup Anistropic filtering Flat and Gouraud shading Trilinear filtering TwinTexel engine 250 MHz RAMDAC 32 bit Z stencil buffer eliminates hidden screen...

Page 201: ...le D 1 NVIDIA Vanta LT Display Modes Resolution Bits per pixel Color Depth Max Refresh Frequency Hz 640 x 480 8 256 85 640 x 480 16 65K 85 640 x 480 24 16 7M 85 800 x 600 8 256 85 800 x 600 16 65K 85 800 x 600 24 16 7M 85 1024 x 768 8 256 85 1024 x 768 16 65K 85 1024 x 768 24 16 7M 85 1152 x 864 8 256 85 1152 x 864 16 65K 85 1152 x 864 24 16 7M 85 1280 x 1024 8 256 85 1280 x 1024 16 65K 85 1280 x ...

Page 202: ...onitor s power condition Table I 2 lists the monitor power conditions Table D 2 Monitor Power Management Conditions Table D 2 Monitor Power Management Conditions HSYNC VSYNC Power Mode Description Active Active On Monitor is completely powered up If activated the inactivity counter counts down during system inactivity and if allowed to tiemout generates an SMI to initiate the Suspend mode Active I...

Page 203: ...s the attachment of an optional card such as a video tuner D 6 1 MONITOR CONNECTOR Figure D 3 VGA Monitor Connector Female DB 15 as viewed from rear Table D 3 DB 15 Monitor Connector Pinout Table D 3 DB 15 Monitor Connector Pinout Pin Signal Description Pin Signal Description 1 R Red Analog 9 PWR 5 VDC fused 1 2 G Blue Analog 10 GND Ground 3 B Green Analog 11 NC Not Connected 4 NC Not Connected 12...

Page 204: ...Appendix D Compaq NVIDIA Vanta LT AGP Graphics Card Compaq Personal Computers Original August 2000 D 6 This page is intentionally blank ...

Page 205: ...urations and optional for other models This card is available in 16 and 32 MB versions This appendix covers the following subjects Functional description E 2 page E 2 Display configurations E 3 page E 4 Programming E 4 page E 5 Power management E 5 page E 6 Connectors E 6 page E 7 NOTES 179250 002 Card with 16 MB SDRAM 179250 005 Card with 32 MB SDRAM Figure E 1 Compaq NVIDIA M64 AGP Graphics Card...

Page 206: ...features listed below 16 or 32 MB SDRAM frame buffer using 128 bit 143 MHz access AGP 4X transfers with sideband addressing 2D drawing engine providing 3 ROP BtBLT Triangle BLT Stretch BLT Line and poly draw Color expansion Coor conversion and scaling 3D rendering engine with Triangle setup Anistropic filtering Flat and Gouraud shading Trilinear filtering TwinTexel engine 300 MHz RAMDAC 32 bit Z s...

Page 207: ...x 480 8 256 16 or 32 MB 85 640 x 480 16 65K 16 or 32 MB 85 640 x 480 24 16 7M 16 or 32 MB 85 800 x 600 8 256 16 or 32 MB 85 800 x 600 16 65K 16 or 32 MB 85 800 x 600 24 16 7M 16 or 32 MB 85 1024 x 768 8 256 16 or 32 MB 85 1024 x 768 16 65K 16 or 32 MB 85 1024 x 768 24 16 7M 16 or 32 MB 85 1152 x 864 8 256 16 or 32 MB 85 1152 x 864 16 65K 16 or 32 MB 85 1152 x 864 24 16 7M 16 or 32 MB 85 1280 x 102...

Page 208: ...m to the VESA display power management signaling DPMS protocol This protocol defines different power consumption conditions and uses the HSYNC and VSYNC signals to select a monitor s power condition Table E 5 lists the monitor power conditions Table E 2 Monitor Power Management Conditions Table E 5 Monitor Power Management Conditions HSYNC VSYNC Power Mode Description Active Active On Monitor is c...

Page 209: ...splay monitor connector and the graphics memory expansion connectors Figure E 3 VGA Monitor Connector Female DB 15 as viewed from rear Table E 3 DB 15 Monitor Connector Pinout Table E 6 DB 15 Monitor Connector Pinout Pin Signal Description Pin Signal Description 1 R Red Analog 1 9 5 VDC 5 volts fused 2 G Blue Analog 1 10 GND Ground 3 B Green Analog 1 11 Mon ID Monitor Identification 4 Mon ID Monit...

Page 210: ...n Header Table E 4 Multimedia Interface Connector Pinout Table E 7 Multimedia Interface Connector Pinout Pin Signal Description Pin Signal Description Z1 GND Ground Y1 P0 Pixel Data 0 Z2 GND Ground Y2 P1 Pixel Data 1 Z3 GND Ground Y3 P2 Pixel Data 2 Z4 EVIDEO Overlay Enable Y4 P3 Pixel Data 3 Z5 ESYNC External Sync Enable Y5 P4 Pixel Data 4 Z6 EDCLK External Clock Enable Y6 P5 Pixel Data 5 Z7 SDA ...

Page 211: ...terface 5 7 display VGA monitor 6 6 D 5 5 IDE interface 5 3 IDE diskette drive power 7 5 keyboard pointing device interface 5 19 Multimedia Interface E 6 parallel interface 5 13 PCI bus 4 9 serial interface RS 232 5 8 Universal Serial Bus interface 5 23 cooling 4 36 4 37 core voltage 3 2 3 3 7 7 DIMM 3 5 DIMM detection 8 5 DIMM support 8 15 diskette drive interface 5 4 display modes D 3 display mo...

Page 212: ...rrupts 4 7 Pentium II 2 14 Pentium II processor 2 12 Pentium III processor 3 3 PHY 5 30 Plug n Play 2 2 2 15 8 15 Plug n Play BIOS function 8 15 power button 7 3 Power Button Override 4 24 power consumption graphics card D 4 power distribution 7 5 Power indicator 4 42 power management ACPI 4 35 PCI 4 7 power management BIOS function 8 17 power supply 7 1 power supply assembly 7 2 power on password...

Page 213: ...atus 8 15 thermal sensing 4 36 4 37 typematic C 8 UART 5 8 Universal Serial Bus USB interface 5 20 upgrading 815 based graphics 6 6 upgrading BIOS 8 2 upgrading processor 3 4 USB interface 5 20 USB keyboard C 4 USB legacy support 8 23 USB ports 2 15 voltage core 3 2 3 3 7 7 wake up power 7 4 wake up events 7 4 Wake On LAN 7 4 Windows keys C 9 WOL 7 4 ZIF socket 2 13 ...

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