HP 98628A Installation Manual Download Page 7 | Manualshive

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Summary of Contents for 98628A

Page 1: ...I I HP Computer Systems HP 98628N98691A Datacomm Interface Installation II II I I I Fho HEWLETT a PACKARD I ...

Page 2: ...eight prepaid Repairs necessitated by misuse of the equipment or by hardware software or interfacing not provided by Hewlett Packard are not covered by this warranty HP warrants that its software and firmware designated by HP for use with a CPU will execute its programming instructions when properly installed on that CPU HP does not warrant that the operation of the CPU software or firmware will b...

Page 3: ...This document refers to proprietary computer software which is protected by copyright All rights are reserved Copying or other reproduction of this program except for archival purposes is prohibited without the prior written consent of Hewlett Packard Company Hewlett Packard Roseville Networks Division 8000 Foothills Boulevard Roseville California 95678 ...

Page 4: ...age Note that pages which are rearranged due to changes on a previous page are not considered revised The manual printing date and part number indicate its current edition The printing date changes when a new edition is printed Minor corrections and updates which are incorporated at reprint do not cause the date to change The manual part number changes when extensive technical changes are incorpor...

Page 5: ...a Link Protocol Default Configuration 11 Interface Installation 12 Chapter 3 Interface Cables RS 232C Connections 13 Optional Drivers and Receivers 13 Option 001 DTE Male Cable 14 Option 002 DCE Female Cable 15 Connecting Two Desktop Computers 16 Using DCE Cables to Connect to DTE Devices 17 RS 449 Connections 17 Option 003 RS 423 Unbalanced OTE Cable 17 Test Connectors 19 RS 232C DTE Cable Test C...

Page 6: ...6 Interrupt System 27 Interface Reset 27 Shared Memory Controller 28 Addressing 28 Read Write Control 28 Clock Circuits 28 Memory Access Select Timing 29 Memory Cycle Timing 29 Hardware Registers 31 Shared RAM 32 Default Switches 33 Baud Rate Multiplexer 33 Line Drivers and Receivers 33 Replacement Parts 34 ...

Page 7: ...ronous Async protocol commonly used for timesharing and remote host compu ter applications as well as connections to remote terminals HP DSN Data Link Protocol most commonly used with Data Link network applications based around an HP 1000 network host computer The HP 98691A Programmable Datacomm Interface is designed for installing custom protocols or protocols that are designed and supported by s...

Page 8: ...uld be taken to protect interface printed circuit assemblies from static discharge during handling Each interface is shipped in a protective anti static bag which provides adequate anti static protection for the interface as long as it remains inside the bag It is good practice to use additional anti static protection such as commercially available personnel grounding straps when servicing or inst...

Page 9: ...3 in by 6 6 in Weight 310 grams 11 ounces Environmental Range Temperature O C to 45 C 32 to 113 F Humidity 0 to 80 non condensing Electrical Specifications 98628A power consumption typical 5 V 710 rnA 12 V 37 rnA 12 V 60 rnA The following adapters also obtain power through the HP 98628 interface Their consumption should be added to the interface power consumption when they are used Typical values ...

Page 10: ...enerally exceed the maximum rates available to RS 232C installations The following charts show the maximum speed versus cable length for RS 422 balanced and RS 423 unbalanced RS 449 installations Cable Length feet 10K 4K 1K 400 100 40 10 10K Not Recommended Recommended Combinations 100K 1M 10M RS 422 Modulation Rate Versus Cable Length Data Rate bits second ...

Page 11: ...98691 interfaces are available with 3 cable options which can also be ordered separately Cable length is approximately 4 9 metres 16 feet Cables are discussed in detail in Chapter 3 Option 001 RS 232C DTE Cable with 25 pin Male Connector Used to connect to RS 232C DCE devices such as modems Also available separately as part number 5061 4215 Option 002 RS 232C DCE Cable with 25 pin Female Connector...

Page 12: ...evels required for HP DSN Data Link connections The HP 13265A Modem is a Bell 103 113 compatible asynchronous modem for connecting directly to the US switched public telephone network This modem is originate only and is used in applications requiring up to 300 baud communications rates It supports both auto dial and manual originate capability The HP 13266A Current Loop Adapter provides a 20 rnA c...

Page 13: ...mware that is installed on the interface card Configuration Switches As shown in the following figure the left hand switch cluster is used to set the hardware interrupt level and interface select code The left most switch in that cluster has a function that is dependent on protocol and defined by interface firmware The function of the switches in the right hand cluster is determined by protocol an...

Page 14: ...erals only leaving interrupt levels 3 thru 6 available for interfaces to external peripherals Interrupt level 3 is lowest priority 6 is highest If an interrupt request conflict occurs service is provided by the computer on the basis of highest priority first If two devices at the same level interrupt simultaneously the interrupts are serviced in the order they are en countered by the operating sys...

Page 15: ... compete whenever any information transfer or control or status operation is performed on that select code Each interface is marked with a recommended default setting This setting is adequate for most languages but may have to be altered in some specific instances especially if one computer is being used for multi language applications and supports several peripherals Note When assigning a select ...

Page 16: ...c Protocol Default Configuration At power up the datacomm interface is automatically configured using the default switch settings The initial configuration can be altered under program control by the use of CON TROL and STATUS statements in BASIC or their equivalent in other languages To use the default values omit the corresponding control operations from your program When Async protocol is selec...

Page 17: ...ion If the full complement of handshake signals such as data terminal ready clear to send etc are available in non modem connections then set the switches to hardware handshake ON non modem connection If modems are being used set halflfull duplex to the appropriate configuration This completes default switch configuration for Async connections Data Link Protocol Default Configuration As when Async...

Page 18: ...omputers that use this interface have one or more 110 backplane cover plates that protect the accessory backplane enclosure To install the interface remove the appropriate cover and carefully slide the interface into the selected slot usually the one below the centerline of the cover plate retainer nuts in the computer or expander frame Seat the interface into the backplane connector then tighten ...

Page 19: ...her data communications equipment The DTE deSignation means the cable is designed to be used as a Data Terminal EqUip ment DTE interconnect to Data Communications EqUipment DCE The Option 002 DCE cable has a female connector and is internally cross wired so that the datacomm interface acts like DCE such as a modem Thus by using two cables one of each type two computers can be connected directly to...

Page 20: ...r schematic showing the loop back signal paths used for testing the interface and cable 98628 5061 4215 RS 232C INTERFACE OTE CABLE SIGNALS 12 BA PIN2 J f 4 2 _ _ BB PIN 3 f 13_ _ _ CA PIN 4 44 CB PIN 5 4_6_ _ _ CF PIN 8 _15_ _ _ SCA PIN 19 J 47 SCF PIN 12 f 14_ _ _ CD PIN 20 __ f 9 _ _ CE PIN 22 r f 4 5 _ _ CC PIN 6 41 DB PIN 15 __ 43 f DD PIN 17 SIGNAL f 48 _ _ AB PIN 7 GROUND SAFETY f 2 4 _ _ A...

Page 21: ...g diqgram shows the driver and receiver connections to the female RS 232C connector and includes the test connector loop back wiring 5061 4216 DCE CABLE RS 232C SIGNALS BA PIN2 BB PIN 3 CA PIN4 B CB PIN 5 f CF PIN 8 7 SCA PIN 19 J 1 5 SCF PIN 12 9 CDIPIN F 45 4 l CEIPIN22 CC PIN 6 CE 43 0 DB PIN 15 NOT USED DA PIN 24 RCVTIMING 7 DD PIN 17 NOT USED CH PIN 23 SIGNAL 8 AB PIN 7 f GROUND V SAFETY l 4 ...

Page 22: ...between interfaces through the two cables and includes all connector pin numbers 98628 DTE RS 232C DCE 98628 INTERFACE I CABLE SIGNALS CABLE INTERFACE 2 1 2 BA PIN 2 _ _ _4 2 4 2 4 BB PIN 3 _ _ 12 DATA 1 _ n ___ 13 CA PIN4l r46 44 4 CB PIN 5 4 6 4 CF PIN 8 1I __ 13 rL _ 44 _ 15 4 SCA PIN 19 _ _ 47 SECOND C 47 SCF PIN 12 15 14 CD PIN20 4 9 r _ 45 9 CE PIN22 _ _ IrI4 4 5 4 CC PIN 6 41 43 _D T 4 3 4 ...

Page 23: ...ired handshake inputs for the interface Does the peripheral have receivers that can produce the needed response to the driver signals originating from the interface What signals must be cross wired to maintain the proper states for the various handshake lines such as DSR CTS and RI For more information about what stock adapter cables are available for your needs contact your nearest HP Sales and S...

Page 24: ...ATA MODE COMMON 7 29 REMOTE LOOPBACK 14 R A 46 RECEIVER READY 13 RR BIC 21 RECEIVER READY COMMON 31 41f SIGNAL RATE SELECT 16 a n L_ __ INCOMING CALL J 15 2 RECEIVE COMMON 720 15 OCD2 L NEWSIGNAL 32 _ l _TTIUI SELECTSTANDBY 34 7 TERMINAL TIMING 7 1 7 J TIIC r 32 TERMINAL TIMING COMMON 735 TIA 43 RECEIVE TIMING 8 RTIB C 1 RECEIVE TIMING COMMON 26 47 OCR2 INSERVICE 1 TERMINAL READY i r r 3 TERMINAL ...

Page 25: ... Carrier Detectl Ring Indicator OCRl Data Terminal Ready CD 20 6 CC Data Set Ready Secondary RTS SCA 19 12 SCF Secondary DCD OCR2 not used 14 25 not used Data Rate Select OeDl CH 23 15 DB DCE Transmit Timing Terminal Xmit Timin DA 24 17 DO DCE Receive Timing RS 232C DCE Cable Test Connector A test connector 1251 6624 is also provided with the datacomm interface DeE cable option This connector is s...

Page 26: ... Data Send Data Common SD C 22 24 RD B C Receive Data Common Request to Send unbal RS u 7 5 ST A Send Timing Request To Send Common RS C 25 23 ST B C Send Timing Common Local Loopback OCD3 10 11 DM A Data Mode Send Common SC 37 29 DM B C Data Mode Common 20 RC Receive Common 31 RR B C Receiver Ready Common Remote Loopback OCD4 14 13 RR A Receiver Ready Signal Rate Select OCDI 16 15 OCRI Incoming C...

Page 27: ...ent building grounds before you connect the cable to the modem use an AC OC digital voltmeter to measure the voltage difference between the shield pin of the cable connector and the shield pin of the corresponding modem or other device connector If the voltage is more than 100 to 300 millivolts alternate grounding should be installed to reduce or eliminate the difference After grounding is complet...

Page 28: ...Interface Connector Pin Assignments Interface Interface Function Pin No Pin No Function Optional Driver OCD4 1 26 Optional Driver OCD3 Send Data SD bal B 2 27 Send Data SD bal A Req to Send RS bal B 3 28 Req to Send RS bal A Terminal Ready TR bal B 4 29 Terminal Ready TR bal A Not used 5 30 Not used Not used 6 31 Not used Xmit Timing TT unbal 7 32 Xmit Timing TT unbal return Xmit Timing TT bal B 8...

Page 29: ...E 113 Tx Timing DTE ST Send Timing DB Tx Timing DCE 114 Tx Timing DCE RT Receive Timing DD Receiver Timing 115 Rec Timing DCE RS Request to Send CA Request to Send 105 Request to Send CS Clear to Send CB Clear to Send 108 Ready for Sending RR Receiver Ready CF Data Carrier Detect 109 Received Line Signal Detect SQ Signal Quality CG Signal Quality 110 Data Signal Quality Detector Detector NS New Si...

Page 30: ...24 Interface Cables ...

Page 31: ... is normally serviced on an exchange replacement basis due to its complexity Service at the component level should be attempted only when adequate test equipment is available Theory of Operation The following block diagram shows the functional blocks that comprise the interface MAINFRAME INTERFACE CONTROL SELECT CODE ADDRESS INTERRUPT CONTROL and ADDRESS INTERNAL LINES TO 4t1 11 Z 80A CONTROL OATA...

Page 32: ...e Program ROM Z 80A System Operation The Z 80A CPU SIO and CTC chips as well as the program ROM and default switches are tied together through the internal Z 80A 16 bit address ZA bus and 8 bit data ZD bus These buses belong exclusively to the interface CPU and are not accessible by the mainframe com puter Shared RAM and registers are accessed through the shared data SO and shared address SA buses...

Page 33: ...ared memory The interrupt request is removed when the Interrupt Register Decoder U22 activates one of the Set inputs on the Interrupt Request flip flop Interface Reset During power up the computer mainframe pulls the RESET input on all interface cards low This causes the datacomm interface to reset the Z 80A CPU by activating its reset input for the duration of the pulse and clears the Reset flip ...

Page 34: ...read write control U39 pin 2 during mainframe memory accesses and is held inactive during Z 80A accesses U39 pin 3 The latched mainframe read write signal controls the direction of the 8 bit bus transceiver only the lower 8 bits of the 16 bit bus are used and drives the 28 read write input of the memory control multiplexer U32 The Z 80A read write control line ZRD controls the direction of the sha...

Page 35: ...w indicating that no memory cycle is in progress The state of the Access Select flip flop s 0 input at clock time determines which processor gets control of the shared memory cycle If 0 is low the mainframe processor is connected if 0 is high access defaults to the Z 80A interface processor When the System Clock TPS input to the timing chain goes high the 1A or 1B input to the memory control multi...

Page 36: ...E DTACK MAINFRAME ACCESS WAIT for MEMORY DATA Z 80A ACCESS Memory Cycle Timing Diagram I Assume that all previous memory cycles have run to completion The Shared Memory Control ler samples the incoming memory request lines on alternate falling edges of the clock oscillator when the System Clock at TP5 is LOW When a shared memory access request is received it propogates through intermediate gates a...

Page 37: ...line forcing it high end of write cycle and sends a DTACK data acknow ledge to the mainframe if the mainframe has access to shared memory The controller then hangs in the same state until the shared memory access request is removed by the processor When the processor releases the request line the 0 input U17 pin 2 goes high releasing the data bus transceivers The timing chain then resets to its id...

Page 38: ...ded into two segments lower and upper blocks The first two locations of the lower block are also connected to special decoding hardware that control interrupts between the processors that share the memory One register is used as a command register the other as an Interrupt Cause register When commands are sent to the interface Command Register from the mainframe the command flip flop is set causin...

Page 39: ... interface has two types of line drivers unbalanced and balanced The unbalanced drivers are compatible with EIA RS 232C CCITT V 28 and RS 423 CCITT V 10 electrical interface standards Driver rise and fall times are determined by the resistor connected to pin 1 of each driver package U1 U2 U3 and U7 The 1 MO resistor on control signal drivers limits the rise time to approximately 100 IJ S The data ...

Page 40: ...arts are available from Hewlett Packard at the following address Corporate Parts Center Hewlett Packard Company 333 Logue Avenue Mountain View California 94042 Telephone 415 968 9200 Manufacturer code and part number are listed in the right hand columns of the parts list Manufacturers are as follows Mfr No Manufacturer Name Address Zip Code 00000 Any satisfactory supplier 01121 Allen Bradley Co Mi...

Page 41: ...CHOTTKY 28480 1901 0518 CR4 1901 0518 8 DIODE SM SIG SCHOTTKY 28480 1901 0518 Fl 2110 0297 4 1 FUSE 5A 125V NTD 281X 093 28480 2110 0297 F2 2110 0423 8 1 FUSE 1 5A 125V NTD 281X 093 28480 2110 0423 F3 2110 0592 2 1 FUSE 4A 125V NTD 281X 093 28480 2110 0592 Ql 1854 0019 3 1 TRANSISTOR NPN SI TO 18 PD 360MW 28480 1854 0019 Q2 1853 0015 7 1 TRANSISTOR PNP SI PD 200MW FT 500MHZ 28480 1853 0015 Rl 0683...

Page 42: ... 1568 8 1 IC BFR TTL LS BUS QUAD 01295 SN74LS125AN U36 1820 1202 7 1 IC GATE TTL LS NAND TPL 3 INP 01295 SN74LS10N U37 1820 2657 8 IC GATE TTL ALS OR QUAD 2 INP 01295 SN74ALS32N U38 1820 1905 7 1 IC GATE TTL LS NOR DUAL 5 INP 07263 74LS260PC U39 1820 1444 9 4 IC MUXR DATA SEL TTL LS 2 TO l LINE QUAD 01295 SN74LS298N U40 1820 1444 9 IC MUXR DATA SEL TTL LS 2 TO 1 LINE QUAD 01295 SN74LS298N U41 1820...

Page 43: ...D SAl III 10 U36 8 NC c HALT CPU A4 34 u V 7M t 03 17 R fSi ST A 4 S f 7 A23 15 6v _ 8 D g V 10 NC B WR U2B AA I __ 4 1 0 I ZAA I o R DAf 2 If Ji r r I ST laIC II f 73f B A2 __ 1 P 1 10 I ls 121 I ii DO 30 W7Iim t I I J V 72 8A21 17 PT Q v 6 II 1 4U2 46 il SYNCA CTSA B 5 26l 32A BK ATIA 1 43 BA20 13 p 5roCCQS14 5 12 kSA4 2 U3 ZAO ZMi DCOAP L________ Jlj 1 tjtl _ l 1 Rf 6 RTta e 1 18f t V I I 1_ _1...

Page 44: ...Part No 9H62H 9000 1 FIIOW HEWLETT PACKARD Printed in U S A December 1983 ...

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