HP 8560E, Service Manual

Page: 399 / 665

398 Chapter 7
ADC/Interface Section
A16 Assembly Fast ADC Control Circuits (8560E with Option 007)
Trigger
Refer to function block D of the A16 fast ADC assembly schematic
diagram in the HP 8560 E-Series Component Level Information.
When the A16 fast ADC is triggered, the current static RAM address is
latched into trigger address latches U27 and U28 (block G), and the
post-trigger counter (U19, U20, U21, U22, and U47) begins counting.
Samples continue to be written to consecutive addresses in RAM U32
until the post-trigger counter reaches its terminal count. The CPU on
the A2 controller assembly monitors the HSWP line and starts a
software timer when HSWP goes high after being triggered. The
software timer is set to slightly longer than the post-trigger counter will
be counting, so at the end of the "time-out", the post-trigger counter has
already reached its terminal count. At the end of this "time-out", the
CPU on the A2 controller assembly takes the fast ADC out of "write"
mode and reads latches U27 and U28 to determine the static RAM
address of the sample that was taken when the trigger occurred. The
CPU then writes the trigger address (read at U27/U28) to the fast ADC
static RAM address counter (15-bit circular address counter). If
pre-trigger or post-trigger (delay) is being used, the CPU adds or
subtracts appropriately and writes the "adjusted" trigger address to the
static RAM counter. The CPU then begins reading the fast ADC data,
starting from the trigger (or offset trigger) address.
The trigger circuitry is enabled by the ARM signal (bit 1 of the fast
ADC control word). Once a trigger occurs, the fast ADC cannot be
triggered again until the ARM line goes low (disarmed), then high
again (armed).
The fast ADC is triggered by the HSWP line in
FREE RUN
,
LINE
, and
EXTERNAL
trigger modes. When
VIDEO
trigger is being used, a
synchronous digital video trigger signal, VCLK, is generated by PAL U1
(block A) and U17A (block D).
316-Bit Post-Trigger Counter
Refer to function block E of the A16 fast ADC assembly schematic
diagram in the HP 8560 E-Series Component Level Information.
The 16-bit post-trigger counter controls the number of static RAM
memory locations that will be written after the trigger occurs. This
counter consists of U19, U20, U21, U22, and U47. The counter is loaded
from the CPU on the A2 controller assembly when the A16 fast ADC
assembly is in "read" mode. The CPU loads the counter by first setting
the LLOADPOST (bit 7 of the fast ADC control word) and the
LREADCLK (bit 9 of the fast ADC control word) to their low state. The
CPU then writes the 16-bit word to the fast ADC secondary address.
The rising edge of PCLK then latches the 16-bit data into the
post-trigger counter.