HP ProCurve Switch 5300xl Series Reviewer’s Guide
2.2.2.1 Classification and Lookup
When a packet first comes in, the classifier section determines the packet characteristics, its
addresses, VLAN affiliation, any priority specification, etc. The packet is stored in input memory,
lookups into the table memory are done to determine routing information and a N-Chip specific packet
header is created for this packet with this information. This header is then forwarded to the
programmable section of the N-Chip.
2.2.2.2 N-Chip Programmability
As mentioned in the previous section, one of the functions of the N-Chip is to analyze each packet’s
header as it comes into the switch. The packet’s addresses can be read, with the switch making
forwarding decisions based on this analysis. For example, if a packet’s 802.1Q tag needs to be changed
to re-map the packet priority, the N-Chip needs to look at each packet to see if any particular one
needs to be changed. This packet-by-packet processing has to occur very quickly to maintain overall
wire-speed performance. ASICs (application specific integrated circuits) provide this high
performance, but typically cannot be changed in their functionality once the ASIC design is frozen.
To broaden the flexibility of the N-Chip, a programmable function is included in some areas of its
packet processing. This programmability provides network processor-like capability, giving the HP
designers the opportunity to make some future changes or additions in the packet processing features
of the ASIC by downloading new software into it. Thus new features needing high performance ASIC
processing can be accommodated, extending the useful life of the switch without the need to upgrade
or replace the hardware.
This programmable functionality was originally designed and implemented in the popular HP ProCurve
Switch 4000M switch family and was used to give the HP ProCurve Switch 4000M new ASIC-related
features well after initial release of the product. Customers with existing units could benefit from the
new features via a free software download. The customer’s investment in the Switch 4000M was
preserved by providing new functionality not otherwise possible without the ASIC programmability.
Being based on the Switch 4000M’s implementation, the HP ProCurve 5300xl programmable capability
is a second generation design.
2.2.2.3 Fabric Interface
After the packet header leaves the programmable section, the header is forwarded to the Fabric
Interface. The Fabric Interface makes final adjustments to the header based on priority information,
multicast grouping, etc. and then uses this header to modify the actual packet header as necessary.
The Fabric Interface then negotiates with the destination N-Chip for outbound packet buffer space. If
congestion on the outbound port is present, WRED (weighted random early detection) can also be
applied at this point as a congestion avoidance mechanism.
Finally the N-Chip Fabric Interface forwards the entire packet through the F-Chip to an awaiting output
buffer on the N-Chip that controls the outbound port for the packet. Packet transfer from the N-Chip to
the F-Chip is provided via the 9.6Gbps full duplex backplane connection, also managed by the Fabric
Interface.
2.2.2.4 The N-Chip CPU
The N-Chip contains its own CPU, a 66 MHz ARM-7, for Layer 2 learns, packet sampling for the XRMON
function, handling local MIB counters and running other module related operations.
Overall, the local CPU offloads the master CPU by providing a distributed approach to general
housekeeping tasks associated with every packet. MIB variables, which need to be updated with each
packet, can be done locally. The Layer 2 forwarding table is kept fresh via this CPU. Other per-port
protocols, such as Spanning Tree, LACP and CDP, are also run on this CPU.
The local CPU, being a full-function microprocessor, allows functionality updates through future
software releases.
© Hewlett-Packard Co. 2002, 2003
Rev 1.1 – 2/11/2003
http://www.hp.com/go/hpprocurve
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Summary of Contents for 5300
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