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HP 1660E Series, Service Manual

The HP 1660E Series is a versatile electronic measurement instrument designed for precise data acquisition and analysis. Enhance your understanding of this powerful tool by accessing the comprehensive Service Manual available for free download at manualshive.com. Maximize the potential of your HP 1660E Series with this invaluable resource.

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Summary of Contents for 1660E Series

Page 1: ...ill find any other available product information on the Agilent Test Measurement website www tm agilent com HP References in this Manual This manual may contain references to HP or Hewlett Packard Please note that Hewlett Packard s former test and measurement semiconductor products and chemical analysis businesses are now part of Agilent Technologies We have made no changes to this manual copy In ...

Page 2: ...Service Guide HP 1660EIESIEP Series Logic Analyzers ...

Page 3: ...660 97030 First edition November 1998 For Safety information Warranties and Regulatory information see the pages at the end of the book Copyright Hewlett Packard Company 1987 1998 All Rights Reserved HP 1660E ESIEP Series Logic Analyzers ...

Page 4: ...ata channels and 4 clock data channels in the HP 1662E 32 data channels and 2 clock data channels in the HP 1663E 3 5 inch flexible disk drive 2 3 GB hard disk drive HP IE R8 232 C and Centronics printer interfaces Variable setuplhold time 4k memory on all channels with 8k in half channel mode Marker measurements 12 levels of trigger sequencing for state and 10 levels of sequential triggering for ...

Page 5: ...is on time between markers Lightweight miniprobes Service Strategy The service strategy for this instrument is the replacement of defective assemblies This service guide contains information for finding a defective assembly by testing and servicing the HP 1660EIESIEP series logic analyzers This logic analyzer can be returned to Hewlett Packard for all service work including troubleshooting Contact...

Page 6: ...zer for use Chapter 3 gives instructions on how to test the performance of the logic analyzer Chapter 4 contains calibration instructions for the logic analyzer Chapter 5 contains self tests and flowcharts for troubleshooting the logic analyzer Chapter 6 tells how to replace assemblies of the logic analyzer and how to return them to Hewlett Packard Chapter 7 lists replaceable parts shows an explod...

Page 7: ... the logic analyzer 2 4 3 Testing Performance To perform the self tests 3 2 To make the test connectors logic analyzer 3 7 To test the threshold accuracy logic analyzer 3 9 Set up the equipment 3 9 Set up the logic analyzer 3 10 Connect the logic analyzer 3 10 Test the TTL threshold 3 11 Test the ECL threshold 3 13 Test the User threshold 3 14 Test the User threshold 3 15 Test the 0 VUser threshol...

Page 8: ...etup hold with single clock multiple clock edges 3 56 Test the next channels 3 59 To test the time interval accuracy logic analyzer 3 60 Set up the equipment 3 60 Set up the logic analyzer 3 61 Connect the logic analyzer 3 64 Acquire the data 3 64 To test the CAL OUTPUT ports oscilloscope 3 65 Set up the equipment 3 65 Set up the logic analyzer 3 66 Verify the DC CAL OUTPUT port 3 67 Set up the lo...

Page 9: ...cope 3 91 Set up the equipment 3 91 Set up the logic analyzer 3 92 Connect the logic analyzer 3 94 Acquire the data 3 94 Performance Test Record logic analyzer 3 95 Performance Test Record oscilloscope 3 101 Performance Test Record pattern generator 3 104 4 Calibrating and Adjusting Logic analyzer calibration 4 2 To calibrate the oscilloscope 4 3 Set up the equipment 4 3 Load the Default Calibrati...

Page 10: ...he HP 1660EP series pattern generator board 6 14 To remove and replace the front panel and keyboard 6 15 To remove and replace the LCD display 6 16 To remove and replace the handle plate 6 17 To remove and replace the fan 6 18 To remove and replace the line filter 6 18 To remove and replace the HP 1660EP series pattern generator cables 6 19 To remove and replace the HP IB and RS 232 C cables 6 19 ...

Page 11: ...HP IE 8 27 RS 232 C 8 28 Contents ix ...

Page 12: ...tions pattern generator 1 4 Characteristics Oogic analyzer 1 5 Characteristics oscilloscope 1 5 Characteristics pattern generator 1 6 Recommended test equipment Oogic analyzer 1 9 Recommended test equipment oscilloscope 1 10 Recommended test equipment pattern generator 1 11 General Information ...

Page 13: ...ote 1 1 Note 1 Quantities 8 1660ElES EP 6 1661ElES EP 4 1662ElES EP 2 1663ElESIEP Note 2 Quantities 4 1660ElES EP 3 1661ElES EP 2 1662ElES EP I 1663ElES EP EP Series Additional Accessories Accessories Supplied Data Output Cable Clock Output Cable User s Guide HP Part Number 16522 61601 16522 61602 01660 97028 Qty 4 1 1 ES Series Additional Accessories Accessories Supplied 10 1 probes BNC miniprobe...

Page 14: ... Time 10 0 ns Minimum Glitch Width 3 5 ns Threshold Accuracy 100 mV 3 of threshold setting SetuplHold Tnne Single Clock Single Edge Single Clock Multiple Edges Multiple Clocks Multiple Edges 0 0 3 5 ns through 3 5 0 0 ns adjustable in 500 ps increments 0 0 4 0 ns through 4 0 0 0 ns adjustable in 500 ps increments 0 0 4 5 ns through 4 5 0 0 ns adjustable in 500 ps increments Specified for an input ...

Page 15: ... 50 to 500 MHz 0 125 x full scale 1 MQ 1 50 Q 1 Specifications valid within 10 Cof auto calibration temperature excluding bandwidth see note 1for bandwidth specification 1 Upper bandwidth reduces by 2 5 MHz for every degree Cabove 35 C 2 Specification applies to the maximum sampling rate At lower rates the specification is 0 005 x 6 t 12 x 10 6x delay setting 0 15 x sample interval for bandwidth l...

Page 16: ...HP 1662E EP ES HP 1663E EP ES For all modes except glitch Characteristics oscilloscope 136 102 68 34 68 51 34 17 The HP 1660ES logic analyzers also include the following characteristics Maximum Sample Rate 2 Gigasample per second Number of Channels 2 Rise Time 0 7 ns ADC 8 bit real time Vertical Resolution 8 bits over 4 vertical divisions 0 4 Waveform Record Length 8000 points Vertical DC Gain Acc...

Page 17: ...r of different macros Maximum number of lines in a macro Maximum number of macro invocations Maximum number of Repeat loop invocations Maximum number of Wait event patterns 1 6 16 channels at 200 MHz clock 32 channels at 100 MHz clock 258 048 vectors TTL 3 state TTlJ3 3v 3 state TTUCMOS ECL terminated ECL unterminated and differential ECL without pod 3 bit pattern level sensing clock pod Synchroni...

Page 18: ...les o C to 65 C 32 OF to 149 oF Humidity Instrument probe lead sets and cables up to 80 relative humidity at 40 C 122 OF Altitude To 3067 m l0 000 ft Vibration Operating Random vibration 5 to 500 Hz 10 minutes per axis 0 3 g rms Non operating Random vibration 5 to 500 Hz 10 minutes per axis 2 41 g rms and swept sine resonant search 5 to 500 Hz 0 75 g O peak 5 minute resonant dwell at 4 resonances ...

Page 19: ...ropean Communities EC EMC Directive 89 336 EEC EN5501I CSIPR 11 ISM Groupl Class A equipment IEC 555 2 and IEC 555 3 EN50082 l IEC 801 2 ESD 4kV CD 8kV AD IEC 801 3 Rad 3V m IEC 801 4 EFT lkV lperformance Codes 1 PASS Normal operations no effect 2 PASS Temporary degradation self recoverable 3 PASS Temporary degradation operator intervention required 4 FAIL Not recoverable component damage Emission...

Page 20: ... mV resolution 0 005 accuracy HP 3458A P BNC Banana Cable HP 11001 60001 P BNC Tee BNC mlitHf HP 1250 0781 P Cable BNC Imllm 48 inch HP 8120 1840 P T SMA Coax Cable IUly 3 18 GHz bandwidth HP 8120 4948 P Adapter IUly 4 SMAlm BNC f HP 1250 1200 P T Adapter SMAlf BNC m HP 1250 2015 P Coupler Uly 4 BNC mllm HP 1250 0216 P T 20 1 Probes Uly 2 HP 54006A P BNC Test Connector 17x2 P IUly 1 BNCTestConnect...

Page 21: ...n HP 3458A P Accuracy better than 0 005 Resistance measurement better than 0 25 accuracy Power Meter Sensor 1 500 MHz 3 accuracy HP436 8482A P Power Splitter Outputs differ by 0 15 dB HP 11667B P Blocking Capacitor BNC m lf 0 18 IlF 200 V HP 10240B P BNC Shorting Cap HP 1250 0774 P Adapter BNC I f UG 914 U HP 1250 0080 C Adapter BNC I to Dual Banana Plug HP 1251 2277 P Adapter Type N m to BNC fl H...

Page 22: ...commended test equipment pattern generator Equipment Required Equipment Oscilloscope Probe OutpulOata Pod T Troubleshooting Critical Specifications 500 MHz Bandwidth 500 MHz Bandwidth no substitute Recommended Use Model part HP 54610B T HP 10441A T 10460A series T l ll ...

Page 23: ...t the logic analyzer 2 2 To apply power 2 3 To operate the user interface 2 3 To set the line voltage 2 3 To degauss the display 2 4 To clean the logic analyzer 2 4 To test the logic analyzer 2 4 Preparing for Use ...

Page 24: ...ndensing Storage Store or ship the logic analyzer in environments within the following limits Temperature 40 C to 75 C 40 of to 167 of Humidity Up to 90 at 65 C Altitude Up to 15 300 meters 50 000 feet Protect the logic analyzer from temperature extremes which cause condensation on the instrument To inspect the logic analyzer 1 Inspect the shipping container for damage If the shipping container or...

Page 25: ...o operate the user interface To select a field on the logic analyzer screen use the arrow keys to highlight the field then press the Select key For more information about the logic analyzer interface refer to the HP 1660EIESIEP and 1670E Series Logic Analyz Us s Guide To set the HP IB address or to configure for RS 232 C refer to the HP 1660ElESIEP and 1670E Series Logic Analyzer User s Guide To s...

Page 26: ...ic analyzer With the instrument turned off and unplugged use mild soap and water to clean the front and cabinet ofthe logic analyzer Harsh soap might damage the water base paint To test the logic analyzer Ifyou require a test to verify the specifications start at the beginning of chapter 3 Testing Performance If you require a test to initially accept the operation perform the self tests in chapter...

Page 27: ...49 To test the time interval accuracy logic analyzer 3 60 To test the CAL OUTPUT ports oscilloscope 3 65 To test the input resistance oscilloscope 3 69 Perform an operational accuracy calibration 3 72 To test the voltage measurement accuracy oscilloscope 3 73 To test the offset accuracy oscilloscope 3 77 To test the bandwidth oscilloscope 3 82 To test the time measurement accuracy oscilloscope 3 8...

Page 28: ...th the HP 1660ES series logic analyzers ensure that the operational accuracy calibration has been done before doing the performance verification tests see chapter 4 The performance verification procedures starting on page 3 8 are each shown from power up To exactly duplicate the setups in the tests save the power up configuration to a file on a disk then load that file at the start of each test If...

Page 29: ...been copied insert the PV disk in the flexible disk drive before starting this procedure 1 Disconnect all inputs then turn on the power switch Walt until the power up tests are complete 2 Press the System key Select the field next to System then select Test in the pop up menu I SIn len 102 Channel 1 0 11K STAT IlH TlnH Ch nel of 16SI Swgle Shot OS lllo cope I S1lt50L UTILITY I IPmtJ 3 Select the b...

Page 30: ... Test stotus PASSEO HP lfl T t slijtus PASSED RS 232C Test Sllltus PASSED PS2 Test Stotu PASSED 01 0 1 Test to tus PASSE LOll Test PASSED Front Ponel Test s to tU UNTESTE J 7 Select the Front Panel Test A screen duplicating the front panel appears on the screen a Press each key on the front panel The corresponding key on the screen will change from a light to a dark color Test the knob by turning ...

Page 31: ...ts at once When the tests fInish the status for each test shows Passed or Failed and the status for the All Analyzer Tests changes from Untested to Tested tlllP 2 Tests tOlllS PASSED Chip Tests ilotus PASSEl Chip l Tests status PASSED Chip 5 rliSl status PASSED Boord Tests stllt lS PASSED AI An61y er Tests status TESTEr 10 Record the results of the tests on the performance test record at the end o...

Page 32: ...ll Tests You can run all tests at one time except for the Data Input Inspection by rurming All Tests To see more details about each test when troubleshooting failures you can run each test individually This example shows how to run all tests at once When the tests finish the status for each test shows Passed or Failed Funcllonol Tests Dolo Memory Te t Stotus PASSED TlmebaSe Test 5 fl tllS PASSED 1...

Page 33: ... of Berg strip a Solder ajumper wire to all pins on one side ofthe Berg strip b Solder ajumper wire to all pins on the other side ofthe Berg strip e Solder two resistors to the Berg strip one at each end between the end pins d Solder the center ofthe BNG connector to the center pin of one row on the Berg strip e Solder the ground tab ofthe BNG connector to the center pin of the other row on the Be...

Page 34: ...r wire to all pins on one side ofthe Berg strip b Solder ajurnper wire to all pins on the other side ofthe Berg strip e Solder the center ofthe BNC conneetorto the center pin of one row on the Berg strip d Solder the ground tab ofthe BNC connector to the center pin ofthe other row on the Berg strip Jumpers 2 r 1h2 8e g Sl p BNC Panel Mount Connector 16 OEO l 3 8 ...

Page 35: ...eading you record is within the limits listed on the performance test record Equipment Required Equipment Digital Multimeter Function Generator BNC Banana Cable BNCTee BNC Cable BNC Test Connector 17x2 Critical Specifications 0 1 mV resolution 0 005 accuracy Accuracy 5 110 6 x frequency DC offset voltage 6 3 V Recommended ModeljP_1t HP 3458A HP 3325B Option 002 HP 11001 60001 HP 1250 0781 HP 8120 ...

Page 36: ... Unassigned Analyzer I flome I1ACHWE I I Type Timing Anol zer 2 UnOSSJgnea Pods I J 07 __ LI All p_ Connect the logic analyzer 1 Using the 17 by 2 test connector BNC cable and probe tip assembly connect the data and clock channels ofpod 1 to one side ofthe BNC Tee 2 Using a BNC banana cable connect the voltmeter to the other side of the BNC Tee 3 Connect the BNC Tee to the Main Signal output of th...

Page 37: ...channels and the J clock channel at a logic high rorm t I1ACHIUE I l 3 H TImIng ACQUISltlon MOd umbOIS Conv nllondl Full Chnnnel 250 NH Clocl Inputs l Co 8 LI C II II I Lnb2 3 Using the Modify down arrow on the function generator decrease offset voltage in I mVincrements until all activity indicators for pod I show the channels at a logic low Record the function generator voltage in the perfonnanc...

Page 38: ...function generator increase offset voltage in I mV increments until all activity indicators for pod 1 show the channels at a logic high Record the function generator voltage in the performance test record Format rlilCHIflE 1 Timing IlcqU SlllQn MOd Conv ntionol Full Chon 250 ttH Clocl Inputs l II 3 12 ...

Page 39: ...on the function generator decrease offset voltage in I mV increments until all activity indicators for pod 1 show the channels are at a logic low Record the function generator voltage in the performance test record 4 Using the Modify up arrow on the function generator increase offset voltage in I mV increments until all activity indicators for pod 1 show the channels are at a logic high Record the...

Page 40: ...c high 3 Using the Modify down arrow on the function generator decrease offset voltage in I mV increments until all activity indicators for pod I show the channels at a logic low Record the function generator voltage in the performance test record LallI 81 La LM LaM LabS LObi L l 7 LabS 4 Using the Modify up arrow on the function generator increase offset voltage in I mV increments until all activ...

Page 41: ...r decrease offset voltage in I mV increments until all activity indicators for pod I show the channels at a logic low Record the function generator voltage in the performance test record orm t t1 CHWE I 11 1 TlIfung Acquisition l10de I ymOOIS Convent ln l full Ch nnel 250 11Hz Clock Inputs j j 15 67 O 15 m fi7 r J LI CJII 4 Using the Modify up arrow on the function generator increase offset voltag...

Page 42: ...dify down arrow on the function generator decrease offset voltage in I mV increments until all activity indicators for pod 1 show the channels at a logic low Record the function generator voltage in the performance test record I I II I 4 Using the Modify up arrow on the function generator increase offset voltage in I mV increments until all activity indicators for pod 1 show the channels at a logi...

Page 43: ...d clock channels ofthe next pod to the output ofthe function generator until all pods have been tested To unassign a pod pair and assign the next pod pair to be tested press the Config key Select the pod pairs then select assign or unassign in the pop up menu 2 Start with Test the TTL threshold on page 3 11 substituting the next pod to be tested for pod 1 3 17 ...

Page 44: ... ps rise time 186Hz bandwidth SMA ml BNC fl BNC mllml Recommended Modeltpart HP 8133A Option 003 HP 54750A with HP 54751A plugin HP8120 4948 HP 1250 1200 HP 1250 0216 Set up the equipment 1 Turn on the equipment required and the logic analyzer Let them warm up for 30 minutes before beginning the test if you have not already done so_ 2 Set up the pulse generator Pulse Generator Setup Timebase Mode ...

Page 45: ...ic analyzer 1 Press the Config key Assign all pod fields to Machine 1 To assign the pod fields select the pod fields then select Machine I in the pop up menu 2 In the Analyzer 1 box select the Type field Select Timing in the pop up menu A al r 1 Name 1MIlCHWE 1 I Type AI J_ Il I _ ll L_ A IL AS _ Ii _ 1 7 N li3 _ p_ Type Una slgneoj PodS Connect the logic analyzer 1 Using SMA cables connect the os...

Page 46: ...h 0 2 4 6 ch1 3 5 7 J e1ock L clock Pod 1 Pod 1 Pod 3 Pod 3 ch 8 10 1Z 14 ch 9 11 13 15 ch B 10 12 14 ch9 11 13 15 J e1ock L clock Pod 2 Pod 2 Pod 4 Pod 4 ch 0 2 4 6 ch1 3 5 7 chO 2 4 6 ch1 3 5 7 K clock M clock Pod 2 Pod 2 Pod 4 Pod 4 ch 8 10 12 14 ch 9 11 13 15 ch 8 10 12 14 ch 9 11 13 15 K clock M clock Pod 5 Pod 5 Pod 7 Pod 7 ch 0 2 4 6 ch 1 3 5 7 chO 2 4 6 ch1 3 5 7 N clock 11661C only N cloc...

Page 47: ...Testing Performance To test the glitch capture logic analyzer Test the glitch capture on the connected channels 3 21 ...

Page 48: ...th channel 2 of the oscilloscope verify that the pulse widths of the pulse generator channels 1 and 2 are 3 500 ns 0 ps or 100 ps lfnecessary adjust the pulse widths ofthe pulse generator channels 1 and 2 I H H j j H H I l H H f l H t H I j Pulse Wldlh 01660 01 5 Set up the Waveform menu to view all the channels a Select one ofthe Glitch labels then select Delete All in the pop up menu b Select Al...

Page 49: ...hannell and Channel 2 CaMP with the LED on 8 On the logic analyzer press the Run key The display should be similar to the figure below Record Pass or Fail in the performance test record Hovelorm MACHINE I Acq Control Test the next charmels Return to Connect the logic analyzer on page 3 19 and connect and test the next combination of data and clock channels until all pods are tested To access pods ...

Page 50: ...ons 100 MHz 3 5 ns pulse width 600 ps rise time 6GHz bandwidth 58 ps rise time SMA m BNC fl 18 GHz bandwidth BNC m ml Recommended Model part HP 8133A option 003 HP 54750A with HP 54751A plugin HP 1250 1200 HP8120 4948 HP1250 0216 Set up the equipment 1 Tum on the equipment required and the logic analyzer Let them warm up for 30 minutes before beginning the test ifyou have not already done so 2 Set...

Page 51: ...llowing table Oscilloscope Setup Acquisition Averaging On of averages 16 Display Graticule Graphs 2 Trigger Level 250 mV Shift LI Time Stop src channel 2 Enter Channell Alternate Scale Attenuation 20 00 1 Scale 200 mVidiv Offset 1 300 V Channel2 Alternate Scale Attenuation 20 00 1 Scale 200 mVidiv Offset 1 300 V Define meas Thresholds user defined Units Volts Upper 980 mV Middle 1 30 V Lower 1 62 ...

Page 52: ...ar Trigger then select All in the pop up menu b Select Count Off Press Select again then select Time in the pop up menu Select Done to exit the menu HP 1662E1ESlEP OOAA HP 1663E1ESlEP OOOA c Select the field labeled I under the State Sequence Levels Select the field labeled anystate then select no state Select Done to exit the State Sequence Levels menu d Select the field next to a under the label...

Page 53: ...A cables connect the oscilloscope to the pulse generator channell Output channel 2 Output and Trigger Output Connectthe HP 1660E ESjEP or HP 1661E ESjEP Logic Analyzer to the Pulse Generator Testing Combinations 2 Cunnectta HP B133A Channel 2 Output Pod 1 channel 3 Pod 3 channel 3 Pod 5 channel 3 Pod 7 channel 3 Pod 1 channel 11 Pod 3 channel 11 Pod 5 channel 11 Pod 7 channel 11 Connectto HP B133A...

Page 54: ... J clock IQ e133 Opllon 003 3 Activate the data channels that are connected according to one of the previous tables a Press the Format key b Select the field showing the channel assigrnnents for one ofthe pods being tested then press the Clear entry key Using the arrow keys move the selector to the dats channels to be tested then press the Select key An asterisk means that a channel is turned on W...

Page 55: ...dth is within limits Ij Dill II SIGNAL I j f I f fJ t f H 1 1 1 1 I I j 1 CLOCK SIGNAL A j f H j t j j I I I r 1 I I _I I_ 4_I_H_ I l i l I I I Clock Pulse Wldtll I t 16 SW01 2 Check the clock period Using the oscilloscope verify that the clock period is 10 000 ns 0 ps or 250 ps a In the oscilloscope Timebase menu select Scale 2 000 ns div b In the oscilloscope Timebase menu select Position Using ...

Page 56: ... Stop edge rising b In the oscilloscope timebase menu select Position Using the oscilloscope mob position the rising edge ofthe clock waveform so that it is centered on the display c On the oscilloscope select Shift width channe 11 then select Enter to display the data signal pulse width width 1 d Ifthe pulse width is outside the limits adjust the pulse generator channel 2 width until the pulse wi...

Page 57: ...e SetuplHold field then select the setup hold combination to be tested for all pods The first time through this test use the top combination in the following table Setup Hold Combinations 3 5 0 0 ns 0 0 3 5 ns c Select Done to exit the setup hold combinations POd5 A7 AS 5JOO ns EJ on Done S etvp HoiO 11il ler Clocl pod A A4 POd5 Al A I0 0 1 I 0 I 0 513 0 ns 0 0 3 5 n 1 012 S 05 t rormot tlACHIUE I...

Page 58: ...fme meas Define l Time Stop edge rising b Inthe oscilloscope ttmebase menu select Position Using the oscilloscope mob position the rising edge ofthe clock waveform so that it is centered on the display c On the oscilloscope select Shift l TIme then select Enter to display the setup time l Ttme I 2 d Adjust the pulse generator channell Delay until the pulses are aligned according the the setup time...

Page 59: ...ct the clock edge as indicated in the table The first time through this test use the top clock and edge in the following table Clocks Ji Ki Li Mi Ni pi b Connect the clock to be tested to the pulse generator channell output c Select Done to exit the Master Clock menu formJI IlACHWE 1 Slale A qulS1lJOn riMe I Full h el l t1emOr l 10MIH 110 ter CloCI DUALS Ol 802 03 8 04 L I SetuplHola I 3 33 ...

Page 60: ...qual field and press the Select key At the pop up menu select Not Equal Press Done e Move the cursor to the Reference Listing field and select The field should toggle to Difference Listing Compl re tlACHINE I FIne Error DIfference 11Sl1n9 0 Lobel Bose c J 55 e n AA 8 n S5 16 n AA 3 n 55 0 n AA 6 nS 55 16 n AA 8 n 55 6 n All 6 n S5 16 ns AA 0 ns SS 6 n All B n 55 16 n 6 Press the blue shift key the...

Page 61: ...the oscilloscope select Shift t Time Select Start src channell then select Enter to display the setup time t Time 1 2 d Adjust the pulse generator channel 1 Delay until the pulses are aligned according the the setup time of the setuplhold combination selected 0 0 ps or 100 ps DATA SIGNA f I FF H I f Tlme L Se1up 11 LOCK SiGNAl j I I H j H H j t j f H H H j H 1 I 1 16 65WOS 10 Select the clock to b...

Page 62: ...steps 11 12 and 13 for the next clock edge listed in the table in step 10 until all listed clock edges have been tested 13 Test the next setup hold combination a in the logic analyzer Format menu press Master Clock b Turn off and disconnect the clock just tested c Repeat steps 1 through 14 for the next setuplhold combination listed in step 1 on page 3 30 until all listed setuplhold combinations ha...

Page 63: ...ons 100 MHz 3 5 ns pulse width 600 ps rise time 6GHz bandwidth 58 ps rise time SMA m BNC fl 18 GHz bandwidth BNC mllml Recommended ModellPall HP 8133A option 003 HP 54750A with HP 54751 A plugin HP1250 1200 HP 8120 4948 HP 1250 0216 Set up the equipment 1 Turn on the equipment required and the logic analyzer Let them warm up for 30 minutes before beginning the test ifyou have not already done so 2...

Page 64: ...e Stop src channel 2 Enter Channell Alternate Scale Attenuation 20 00 1 Scala 200 mV div Offset 1 300 V Channel 2 Alternate Scale Attenuation 20 00 1 Scale 200 mV div Offset 1 300 V Define meas Thresholds user defined Units Volts Upper 980 mV Middle 1 30 V Lower 1 62 V Set up the logic analyzer 1 Set up the Configuration menu a Press the Config key b In the Configuration menu assign all pods to Ma...

Page 65: ...gger key Select Modify Trigger then select Clear Trigger then select All b Select the Count Offfield then select Time in the pop up menu Select Done to exit the menu c Select the field labeled 1 under the State Sequence Levels Select the field labeled anystate then select no state Select Done to exit the State Sequence Levels menu d Select the field next to the pattern recognizer a under the label...

Page 66: ...hannel 2 and trigger ofthe oscilloscope to the pulse generator Connect the HP 1660EjES EP or HP 1661EjES EP Logic Analyzer to the Pulse Generator Testing Combinations 2 Connectto HP8t33A Channel 2 OUlput Pod 1 channel 3 Pod 3 channel 3 Pod 5 channel 3 Pod 7 channel 3 Pod 1 channel 11 Pod 3 channel 11 Pod 5 channel 11 Pod 7 channel 11 Connect to HP 8t33A Channel 2 Output Pod 2 channel 3 Pod 4 chann...

Page 67: ...unnectta HP 8133A Channell Output J clock K clock L clock M clock 3 Activate the data channels that are connected according to one of the previous tables a Press the Format key b Select the field showing the charmel assignments for one ofthe pods being tested Press the Clear entry key Using the arrow keys move the selector to the data charmels to be tested then press the Select key An asterisk mea...

Page 68: ... pulse width is within limits OAT II SIGNAL I I I I H I r t t H t H f j I l f t H l I r CLOCK SIGNAL l l I I I I 1 1 1 I j r t t t j I t t t Clock Pulse Wldlh 1 16555W1 2 Check the clock period Using the oscilloscope verify that the clock period is 10 000 ns 0 ps or 250 ps a In the oscilloscope Timebase menu select Scale 2 000 nsldiv b Inthe oscilloscope Timebase menu select Position Using the osc...

Page 69: ...v b In the oscilloscope Timebase menu select Position Using the oscilloscope mob position the data waveform so that the waveform is centered on the screen c On the oscilloscope select Shift width channell then select Enter to display the data signal pulse width width I d Ifthe pulse width is outside the limits adjust the pulse generator channel 2 width until the pulse width is within limits r OAf ...

Page 70: ...setup hold combinations pods AI AZ 4 5 0 0 liS pods A7 Ae 1 5 0 0 ns pods 113 A4 I 1 5 0 0 n 2 012 5 nS Analy er J form t J1ACHWE 1 1 5 4 0 n _ 1 513 0 flS 8 Done I Jl 5 flS 2 Disable the pulse generator channell COMP with the LED off 3 Using the Delay mode of the pulse generator channell position the pulses according to the setup time of the setuplhold combination selected 0 0 ps or 100 ps a On t...

Page 71: ...the clock field to be tested and then select the clock edges as indicated in the table The first time through this test use the top clocks and edges HP 1660ElESlEP and HP l661ElESlEP Note that the clocks used depends on which logic analyzer you have Clocks HP 1660EjESjEP and HP 1661EjESjEP JI MI NI KI LI PI HP 1662EjES EP and HP 1663E ES EP JI KI LI MI b Corrnect the rising edge clocks to the puls...

Page 72: ...ursor to Specify Stop Measurement and press the Select key Press Select again to turn on Compare At the pop up menu select Compare Move the cursor to the Equal field and press the Select key At the pop up menu select Not Equal Press Done e Move the cursor to the Reference Listing field and select The field should toggle to Difference Listing Analyzer J CaffirM tlllCHHlE I IFind Error I Dllierenc 1...

Page 73: ... select Enter to display the setup time LI Time 1 2 d Adjust the pulse generator channel 1 Delay until the pulses are aligned according the the setup time ofthe setupihold combination selected 0 0 ps or 100 ps Oil T Sl5NIIL il I ItH H 4 t r I Selup Time LOCK SIGNAL 11 _ I 1 1 I I I I H JIH_ I H H 1 H I I L______ 16555W06 9 Select the clocks to be tested a Select the clock field to be tested then s...

Page 74: ...le in step 4 until all listed clock edges have been tested 12 Test the next setuplhold combination a In the logic analyzer Format menu select Master Clock b Tum off and disconnect the clocks just tested c Repeat steps 1 through 12 for the next setuplhold combination listed in step 1 on page 342 until all listed setup hold combinations have been tested When aligning the data and clock waveforms usi...

Page 75: ...SMA Coax Cable IUly 3 Coupler BNC Test Connector 6x2 Uly 41 Critical Specifications 100 MHz 3 5 ns pulse width 600 ps rise time 6GHz bandwidth 58 ps rise time SMAlml BNC fl 18 GHz bandwidth BNClmllml Recommended Model part HP 8133A option 003 HP 54750A with HP 54751A plugin HP 1250 1200 HP8120 4948 HP 1250 0216 Set up the equipment 1 Turn on the equipment required and the logic analyzer Let them w...

Page 76: ...er Channell Alternate Scale Attenuation 20 00 1 Scale 200 mV div Offset 1 300 V Channel 2 Alternate Scale Attenuation 20 00 1 Scale 200 mVidiv Offset 1 300 V Define meas Thresholds user defined Units Volts Upper 980 mV Middle 1 30 V Lower 1 62V Set up the logic analyzer 1 Set up the Configuration menu a Press the Config key b In the Configuration menu assign all pods to Machine 1 To assign all pod...

Page 77: ...662E1ESlEP OOAA HP 1663E1ESIEP OOOA 3 Set up the Trigger menu a Press the Trigger key Select Modify Trigger select Clear Trigger then select All in the pop up menu b Select Count Off Press Select again then select Time in the pop up menu Select Done to exit the menu c Select the field labeled 1 under the State Sequence Levels Select the field labeled anystate then select uno state 1 Select Done to...

Page 78: ...connect channell channel 2 and trigger from the oscilloscope to the pulse generator Connect the HP 1660EjES EP or HP 1661EjES EP logic Analyzer to the Pulse Generator Testing Combinations 2 Connect to HP 8133A ChannelZ Output Pod 1 channel 3 Pod 3 channel 3 Pod 5 channel 3 Pod 7 channel 3 Pod 1 channel 11 Pod 3 channel 11 Pod 5 channel 11 Pod 7 channel 11 Connect to HP 8133A Channel ZOutput Pod 2 ...

Page 79: ...Pod 4 channel 3 Connect to HP 8133A Channel 1 Output J clock 3 Activate the data channels that are connected according to one of the previous tables a Press the Format key b Select the field showing the channel assignments for one ofthe pods being tested Press the Clear entry key Using the arrow keys move the selector to the data channels to be tested then press the Select key An asterisk means th...

Page 80: ...ft width channel 2 then select Enter to display the master to master clock time width 2 Ifthe positive going pulse width is more than 10 000 ns go to step d Ifthe positive going pulse width is less than or equal to 10 000 ns but greater than 9 750 ns go to step 2 e On the oscilloscope select Shift width channel 2 then select Enter width 2 If the negative pulse width is less than or equal to 10 000...

Page 81: ...lloscope Tirnebase menu select Position Using the oscilloscope knob position the data wavefonn so that the wavefonn is centered on the screen c On the oscilloscope select Shift width channell then select Enter to display the data signal pulse width width l d Ifthe puise width is outside the limits adjust the pulse generator channel 2 width until the puise width is within limits I DAl A SIGNAL I 1 ...

Page 82: ...d Select Done to exit the setup hold combinations pods ALA 1 0 0 0 os r1i ster ClOCk Setup HO 1d pod 113 A4 4 0 0 os 0 2 0 os 1 5 2 51 5 pods A7 6 4 0 0 0 os 1 0 3 0 05 8 Done 0 5 3 5 05 2 Using the Delay mode of the pulse generator channell position the pulses according to the setup time of the setup hold combination selected 0 0 ps or lOOps a On the Oscilloscope select Define meas Define 1 Time ...

Page 83: ...I I H H II I H t 1 t H I 1 1 t 16SSSltJ1Z 3 Select the clock to be tested a Select the clock field to be tested then select the clock as indicated in the table The first time through this test use the top multiple edge clock in the following table Clocks J Kt Lt Mt Nt Pt b Connect the clock to be tested to the pulse generator channell output c Select Done to exit the Master Clock menu AJlOly er Fi...

Page 84: ... again to turn on Compare At the pop up menu select Compare Move the cursor to the Equal field and press the Select key At the pop up menu select Not Equal Press Done e Move the cursor to the Reference Listing field and select The field should toggle to Difference Listing CotPpore ltllCHIHE I I C Base IRelative I 55 I 15 Ali 6 n 55 16 r All B n 55 e ns All 6 ns 55 16 liS All B ns S5 8 n All 8 n 55...

Page 85: ...nation listed in step 1 on page 3 54 until all listed setup hold combinations have been tested When aligning the data and clock waveforms using the oscilloscope align the waveforms according to the setup time of the setup hold combination being tested 0 0 ps or 100 ps Test the next channels Connect the next combination of data channels and clock channels then test them Start on page 3 52 Connect t...

Page 86: ... Function Generator Accuracy 51110 x frequency SMA Cable Adapter BNClm SMAlfl BNC Test Connector 6x2 Set up the equipment Recommended ModellPart HP 8133A option 003 HP 3325B Option 002 HP 8120 4948 HP 1250 2015 1 Turn on the equipment required and the logic analyzer Let them warm up for 30 minutes ifyou have not already done so 2 Set up the pulse generator according to the following table Pulse Ge...

Page 87: ...40 000 00 MHz Amptd 1 00 V Modulation Off Set up the logic analyzer 1 Set up the Configuration menu a Press the Config key b In the Configuration menu assign Pod 1 to Machine 1 To assign Pod 1 select the Pod 1 field then select Machine 1 c In the Analyzer 1 box select the Type field then select TImtng Conflgurollon Anoly er 1 Nome MACHWE I Typ Anol per 2 Type 3 61 ...

Page 88: ...ctivating the channel then press the Done key Form l1fiCHWE I TIming AcquIsition tlode Tr nsl llonol FilII Chunn 115 11Hz L lbl 81 L lb2 Lllb u b4 U bS U b6 L lb7 Li bEl C ocllnpul I POdA2l POdAI kEel 3 Set up the Trigger menu a Select Acquisition Control Select the Acquisition Mode field and the acquisition mode should toggle to Manual b Select Trigger Position in the Pop up menu select Start c S...

Page 89: ...ose X nt rlng 0 t nt rlng SlOP m llsur menl p fg n I Do 1 e Select Done to exit the Specify Patterns menu f Move the cursor to the X pat field Type 1 then press Done g Move the cursor to the O patfield Type 1901 then press Done h Select the Markers Patterns field then select Statistics Select Reset Statistics to initialize the statistics fields An l rerJ Waveform U CHW I J Acq Control _ ACC U He I...

Page 90: ...ress the blue key then press the Run key to select Run Repetitive Allow the logic analyzer to acquire data for at least 100 valid runs as indicated in the pattern statistics field Observe the X to 0 time field and ensure the X marker to 0 marker time is between 47 496 and 47 5041lS during the test 3 When the logic analyzer has acquired more than 100 valid runs press Stop The Min X O field Max X O ...

Page 91: ...ide accurate calibration for the instrument operational accuracy calibration and probe calibration Equipment Required Equipment Digital Multimeter Cable Adapter Critical Specifications 0 1 mV resolution better than 0 005 accuracy BNC m m 48 inch BNC II to Dual Banana Plug Recommended ModelJPart HP 3458A HP 8120 1840 HP 1251 2277 Set up the equipment Turn on the equipment required and the logic ana...

Page 92: ...Igger Del 0 1 Time Null Log Ic Tn ggH p passed F fOIled defnulled C corrupted Prefl ed by if ne solUlere reYlslOn lthoUI re col c Select the Mode field then select Service Cal d Select the Procedure field then select DC Cal BNC e Select the DC volts field and set it to 0 V Scope Cllllbrllllon r MOlle Procedure DC vol IS Service Col DC Col fmc 0 v FUNCTION GOln Offset Hy l es Tr I gger Delo Time Nu...

Page 93: ...igital voltmeter should read close to 0 0000 V Record the reading to four decimal places VI _ 3 In the Calibration menu set the DC Volts to 5 V 4 The digital voltmeter should read close to 5 0000 V Record the reading to four decimal places Vz _ 5 In the Calibration menu set the DC Volts to 0 V 6 Subtract VI from Vz The clifference should be between 4 990 and 5 010 V Record the reading in the perfo...

Page 94: ... up the Channel menu a Press the Chan key b Select the Coupling field then select 1M DC c Move the cursor to the Probe field then use the RPG knob to dial in 1 1 Scope Chonne I Auloscale I E I V Oiv 1 Offset rp e 11 Coupl inq I Proset 15 mV ZSO mV 1M I DC User L LI Display l omPl IDato acquired ott SOOns 0 Options Porlod No l acqUISitIon I ns Verify the AC CAL OUTPUT port 1 Using the BNC cable con...

Page 95: ...Digital Multimeter Cables 2 Adapter Adapters 21 Critical Specifications Measure resistance 4 wirel better than 0 25 accuracy BNC mllmI48 inch BNC Tee mllfllfl BNC f to Dual Banana Plug Recommended ModellPart HP 3458A HP 8120 1840 HP 1250 0781 HP 1251 2277 Set up the equipment 1 Turn on the equipment required and the logic analyzer Let them warm up for 30 minutes ifyou have not already done so 2 Se...

Page 96: ... f Move the cursor to the Offset field Set the Offset to 0 Vby typing 0 then pressing the Select key g Select the Coupling field then select 50Q I DC Stope Seor e Chenne Autoscole I c EJ VIOl I O fret I GIlCouplIng II Preset 20mV 0 1 11 SOQ DC User 5 010 I I Ol plo I ampl I rHO ocqulre M I 500 os OpllOhS Porlod No acquIs tlon 1 os 2 Set up the Trigger menu a Press the Trigger key b Select the Mode...

Page 97: ...gic analyzer Using the BNC to banana adapters connect one end of each BNC cable to the 4 wire resistance connections on the multimeter and connect the free ends of the cables to the BNC Tee Connect the male end of the BNC tee to the channell input of the oscilloscope module 3 71 ...

Page 98: ...g field to 50 O DC and VlDiv to 200 mVlDiv Repeat steps I through 3 5 In the Channel menu change the Coupling field to 50 0 IDC and VlDiv to I VlDiv Repeat steps I through 3 6 In the Channel menu change the Coupling field to 50 0 DC and V Div to 4 V Div Repeat steps I through 3 7 Connect the male end ofthe ENC tee to the channel 2 input of the oscilloscope module S Repeat from Set up the logic ana...

Page 99: ...ent DC Power Supply Digital Multimeter Cable Adapter Icable to power supply Adapter Blocking Capacitor BNC Shorting Cap Critical Specifications 14 Vdc to 14 Vdc 0 1 mV resolution Better than 0 1 accuracy BNC Im m 48 inch BNC II to Dual Banana Plug BNC tee Im llIl BNC Im l 0 18 F 200 V Recommended ModellPart HP 3245A option 002 HP 3458A HP8120 1840 HP 1251 2277 HP 1250 0781 HP 10240B HP 1250 0774 S...

Page 100: ...el I AUl l c l11 I Input GJ ICOUPlln If P e e 20m I V 1 1 IMl OC Us r s h GJ D1SP10U lls mp Delli acquired 01 0 0 ns s Options Period tMr t acquISItion c 2 Set up the Display menu a Press the Display key b Select the Mode field then select Average c Move the cursor to the Average field Type 8 on the front panel keyboard then press Done d Select the Grid field and set it to On e In the Waveform sel...

Page 101: ...d and pressing Select Select Off ll 5cop n ner AU O Cl l I VtlMI r V VOll I IVbV01 1 01 Ct 0 If Ct I If 0 If ScrHn S f IV fT M lrten lIS lmpl TOllto ocqulred 01 J 5C n J Off F erlOG Next eCQulsl Jon 1 ns Connect the logic analyzer 1 Using a BNC to banana adapter connect one end of the cable to the power supply Connect the BNC tee the blocking capacitor and the shorting endcap to the other end of t...

Page 102: ...s to select either mVor V 2 Acquire the zero input voltage a Disconnect the power supply from the channel input b Press the blue shift key then press the Run key Wait for approximately five seconds averaging complete then press Stop e Press the Markers key Move the cursor to the Va Volts field Using the RPG knob move the Va marker over the oscilloscope trace on the display 3 Acquire the measured v...

Page 103: ...king Capacitor BNC Shorting Cap Critical Specifications 35 000 to 35 000 Vdc 1mV resolution Better than 0 1 accuracy BNC mllm 48 inch BNC f to Dual Banana Plug BNC tee mllt lf BNC mllt 0 18 IF 200 V Recommended Model part HP 3245A option 002 HP 3458A HP 8120 1840 HP 1251 2277 HP1250 0781 HP 10240B HP 1250 0774 Set up the equipment Turn on the equipment required and the logic analyzer Let them warm...

Page 104: ...amage to the equipment will resuit g Move the cursor to the slDiv field then use the RPG knob to dial in 500 ns Scope Ch nnel AUlo cole _ fYJ V v 1 01 1 l Gl fCOUPlin 1f Preset CI 1 0 0 1 1 1 lMs OC U er jD1V 1 t Display 1ffa PleITDoto acquired at D SOD lS s Options Penod 11 1 OCqUlsIllOIP 1 ns 2 Set up the Display menu a Press the Display key b Select the Mode field then select Average c Move the...

Page 105: ...arkers are On tum the Vmarkers Offby moving the cursor to the Vrnarkers field and pressing Select 5cop l1 ner t Alllo c le GIlD 0mJ v M rl r C nler Screen S l IT IT I1MI ers l EJ IT EEl 500 tlS 0 On Os o os Connect the logic analyzer 1 Using a BNC to banana adapter connect one end of the cable to the power supply Connect the BNC tee the blocking capacitor and the shorting endcap to the other end o...

Page 106: ...un key After approximately 15 seconds averaging complete press the Stop 1 y Read the voltage from the Markers voltage field 0 00 V 80 mV and enter the value in the perfonnance test record 5 Use the RPG knob to dial in 100 mV Div Press the blue shift key then press the Run key After approximately 15 seconds averaging complete press the Stop key Read the voltage from the Markers voltage field 0 00 V...

Page 107: ...r to the V Div field then use the RPG mob to dial in the V Div value shown on the first line ofthe table b Move the cursor to the Offset field Use the front panel keyboard to type in the offset value shown in the first line ofthe table Use the left and right cursor control keys to select either mV or V Press the Select key 3 Acquire the measured voltage a Press the blue shift key then press the Ru...

Page 108: ...ent Signal Generator Power Sensor Power Splitter Cable Adapter Cr ical Specifications 1 500 MHz at approximately 170 mV rms 1 500 MHz 3 accuracy Outputs differ by 0 15 dB Type N mllm 24 inch Type N m to BNC IfI Recommended ModellPart HP 8656B HP436 8482A HP 11667B HP 11500B HP 1250 0780 Set up the equipment Turn on the equipment required and the logic analyzer Let them warm up for 30 minutes if yo...

Page 109: ...he offset to 0 by typing 0 then pressing the Select key f Select the Coupling field then select 50n I DC g Move the cursor to the slDiv field then use the RPG knob to dial in 200 us Seop Chaflnel Autoec le _ I lnput J V Div Q I OUPI in J I Preset CI off V 0V 1 50t f DC Use s v l IDisplay IrsamPI IData acqulre l at 0 00 OptionS PeriOd tJe n acqulsltlon 2 Set up the Display menu a Press the Display ...

Page 110: ...ce I rL l 11 Slope l IAlllo Trig EdQe J Cl 0 V J PosItive I L J On S OIV I IOISPIOIJ I Son ple 1 Dolo ocquln d 01 0 s 200 oS J Opllons IPerlod I Ne t i1cqulslllon 1 ns C I 4 Turn off the voltage and time markers a Press the Marker key b Move the cursor to the V Markers field and press Select The Select key should toggle the marker to Off c Move the cursor to the T Markers field and press Select At...

Page 111: ...alyzer I Using the N cable connect the signal generator to the power splitter input Connect the power sensor to one output ofthe power splitter 2 Using the N to BNC adapter and the BNC cable connect the other power splitter output to the channell input ofthe oscilloscope 3 85 ...

Page 112: ...he power reading Reading dB 3 Obtain the 500 MHz response a Use the RPG knob to dial in a s1Div value of 2 nsJDiv b Press the blue shift key then press the Run key After approximately 15 seconds averaging complete press the Stop key c Note the voltage reading in the Vp p field V500Mllz mY 4 Determine the oscilloscope response a Calculate the response using the formula response dB 20 logroV OOMhZ 2...

Page 113: ...ctions Equipment Required Equipment Signal Generator Cable Adapter Critical Specifications 200 MHz timebase accuracy 0 25 ppm BNC Im m 48 inch Type NIml to BNC If Recommended ModeljPart HP 8656B Opt 001 HP 8120 1840 HP 1250 0780 Set up the equipment 1 Tum on the equipment required and the logic analyzer Let them warm up for 30 minutes if you have not already done so 2 Set the signal generator to 1...

Page 114: ... the Coupling field then select 50Q DC g Move the cursor to the slDiv field then use the RPG knob to dial in 2 00 ns Scope Channel I Autoscole I Input II V DIV J GJ ICOUPlillgl CI lOt mV 0 I 1 1 50 I DC user f IV OI pllJ J l omp I0 0 ocqu r d 01 0 O ns Options PerIod Ne t acqulslllon lie 2 Set up the Display menu a Press the DisPlay key b Select the Mode Arm field then select Normal c Select the G...

Page 115: ... s ith I Deloy 1f lISpllly 150m I I loto aCQuired ot C 2 00 os 511 Options IPerlM J N01 cqul Jtlon I flS 4 Set up the Markers menu a Press the Marker key b Move the cursor to the T Markers field and press Select At the pop up menu select Auto c Select the Xmarker and set it on Cl at Level 50 Slope Positive Occur 1 use the RPG knob for Occur d Selectthe 0 marker and set it on Cl at Level 50 Slope P...

Page 116: ... ps ofthe Mean X o Record the results in the performance test record 2 Determine longer time period accuracy a Press Select twice to call up the T Markers Auto menu b Select the X marker Set On field At the pop up menu select Manual c Move the cursor to the 0 marker Occur field Press the 1 key then press Select d Press Done e Press the Display key Select the Mode field then select Average Move the...

Page 117: ...MHz 0 125 x full scale 0 5 division Equipment Required Equipment Signal Generator Cable Adapter Critical Specifications 50 MHz and 225 MHz 30 80 mV RMS output BNC 48 inch Type N m to BNC f Recommended ModeljPart HP8656B Opt 001 HP 8120 1840 HP 1250 0780 Set up the equipment Tum on the equipment required and the logic analyzer Let them warm up for 30 minutes if you have not already done so 3 91 ...

Page 118: ...0 DC g Move the cursor to the slDiv field then use the RPG knob to dial in 5 00 ns Scope Chonnel I AUIO COle I Input It VI I I ICouPllng 1 l lOOm SMIDCJ it l l I l5plo I SomPle I DHo ocqulreaot 0 5 00 Il I Options Period I Ne acquisitIon 1 ns 2 Set up the Display menu a Press the Display key b Select the Mode Arm field then select Average c Move the cursor to the Average field Enter 8 in the front...

Page 119: ... 0 in the front panel keyboard then pressing Select l10defArm Edqe s1 h 5 l O ll S OPD Trtgger 4 Turn off the voltage and time markers a Press the Marker key b Move the cursor to the VMarkers field and press Select The Select key should toggle the marker to Off c Move the cursor to the T Markers field and press Select At the pop up menu select Off 5cop rI rl u I Auto cole v norl er g 0 1 Scr een l...

Page 120: ...triggers record a pass in the performance test record e Press Stop to halt the acquisition Read the Vp p field and record the voltage in the performance test record 2 Test the lower bandwidth trigger sensitivity a Use the RPG knob to dial in slDiv of 20 fiS b Set the signal generator to provide a 50 MHz signal with 35 mVrms amplitude c Press the blue shift key then press the Run key d Ifthe oscill...

Page 121: ... ECL 139 mV ECLVL 1 439 V ECLVH 1 161 V User 280 mV User VL 6 280 V User VH 5 720 V User 280 mV User VL 5 720 V User VH 6 280 V OV 100mV oVUser VL 100 mV OVUserVH 100 mV Pod 2 TIL 145mV TILVL 1 355 V TILVH 1 645 V ECL 139 mV ECLVL 1 439 V ECLVH 1 161 V User 280 mV UserVL 6 280 V User VH 5 720 V User 280 mV UserVL 5 720 V User VH 6 280 V OV 100 mV OVUserVL 100 mV OV UserVH 100 mV Pod 3 TIL 145 mV T...

Page 122: ... Vl 5 720 V User VH 6 280 V OV 100 mV OVUserVl 100 mV oVUserVH 100 mV Pod 6 TTL 145 mV TTlVl 1 355 V TTlVH 1 645 V ECL 139 mV EClVl 1 439 V EClVH 1 161 V User 280 mV User Vl 6 280 V User VH 5 720 V User 280 mV UserVl 5 720 V UserVH 6 280 V oV 100 mV OVUserVl 100 mV OVUserVH 100 mV Pod 7 TTL 145 mV TTlVl 1 355 V TTlVH 1 645 V ECL 139 mV ECl Vl 1 439 V EClVH 1 161 V User 280 mV UserVl 6 280 V User V...

Page 123: ... Test Record continued Testing Performance Performance Test Record logic analyzer rest Settings Resu s Glitch Capture Minimum Detectable Pass Fail Glitch 3 5 ns Pod 1 Pod 2 Pod 3 Pod 4 Pod 5 Pod 6 Pod 7 Pod B 3 97 ...

Page 124: ...Fail Pass Fail Single Edge Acquisition All Pods Channel 3 Setup Hold Time 3 5 0 0 ns Jt JJ Kt KJ Lt LJ Mt MJ Nt NJ pt pJ Setup Hold Time 0 0 3 5 ns Jt JJ Kt KJ Lt LJ Mt MJ Nt NJ pt pJ All Pods Channel Setup Hold Time 3 5 0 0 ns Jt JJ 11 Kt KJ Lt LJ Mt MJ Nt NJ pt pJ Setup Hold Time 0 0 3 5 ns Jt JJ Kt KJ Lt LJ Mt MJ Ni NJ pt pJ 3 98 ...

Page 125: ...rator channel 2 Multiple Edge COMP LED on CDMP LED off Acquisition Pass Fail Pass Fail All Pods Channel 3 Setup Hold Time 4 5 0 0 ns JI MI NI JJ MJ NJ KI LI PI KJ LJ PJ Setup Hold Time 0 0 4 5 ns JI MI NI JJ MJ NJ KI LI PI KJ LJ pJ All Pods Channel Setup Hold Time 4 5 0 0 ns JI MI NI JJ MJ NJ 11 KI LI PI KJ LJ pJ SetuplHold Time 0 0 4 5 ns JI MI NI JJ MJ NJ KI LI PI KJ LJ PJ 3 99 ...

Page 126: ...nell CDMP LED off Multiple Edge Pass Fail Acquisition All Pods Channel 3 Setup Hold Time 4 0 0 0 ns J Kt U Mt Nt P Setup Hold Time 0 0 4 0 ns Jt Kt U Mt Nt Pt All Pods Channel Setup Hold Time 4 0 0 0 ns J 11 Kt Lt Mt Nt pt Setup Hold Time 0 0 4 0 ns J Kt Lt Mt Nt P Time Interval Pass Fail Accuracy min X O 47 50 fls maxX O 47 50 fls avg X O 47 50 fls 3 100 ...

Page 127: ...d 4 990 Vdc 5 010 Vdc AC CAL Output 0 8 Vp_p 1 000 KHz Input Resistance 50 ili 0 5 Q 49 5 to 50 5 Q lMili 10 KQ 0 990 to 1 010 MQI Channell 50 Q ZO mVlOiv 1MQ ZO mVlO v 50 Q ZOO mV Oiv 1MQ ZOO mV Oiv 50Q 1V10iv 1MQ 1 VlOiv 50 Q 4V10 v 1MQ 4V10iv ChannelZ 50Q ZOmVlOiv 1MQ ZO mVlOiv 50Q ZOOmVlOiv 1MQ ZOO mV O v 50Q 1V10iv 1MQ 1 V O v 50Q 4V10iv 1MQ 4V10iv 3 101 ...

Page 128: ... 0 mV 1 43 V to 1 37 V 3 57 V to 3 43 V 14 3Vto 13 7V Offset Accuracy Zero input offset Channell 4VlOlv 0 00 V 320 0 mV 1VlOlv 0 00 V 80 0 mV 100 mVlOiv 0 00 V 8 0 mV 10 mVlOiv 0 00 V 800 0 flV Channel 2 4VlOlv 0 00 V 320 0 mV 1VlOlv 0 00 V 80 0 mV 100 mVlOiv 0 00 V 8 0 mV 10 mVlOiv 0 00V 800 0 flV DC input offset Channell 35 00V 35 4 V to 34 6 V 10 00V 10 1 Vto 9 90 V 2 00 V 2 02 V to 1 98 V 2 00...

Page 129: ...ime 5 500 ns 150 ps MEAN X O Measurement MINX O Accuracy MEAN X O MIN X O MAXX O MAX X O MEAN X O 99 000 ns 155 ps MEAN X O MINX O MEAN X O MIN X O MAXX O MAX X O MEAN x o Trigger Sensitivity Channell Trigger Stable de to 50 MHz Pass Fail Trigger Stable 50 MHz to 500 MHz Pass Fail Channel 2 Trigger Stable de to 50 MHz Pass Fail Trigger Stable 50 MHz to 500 MHz Pass Fail 3 103 ...

Page 130: ...Performance Test Record pattern generator Performance Test Record pattern generator Test Settings Results Self Tests Pass Fail 3 104 ...

Page 131: ...4 Logic analyzer calibration 4 2 To calibrate the oscilloscope 4 3 Set up the equipment 4 3 Load the Default Calibration Factors 4 4 Self Cal menu calibrations 4 5 Calibrating and Adjusting ...

Page 132: ...nalyzer circuitry against specifications full calibration refer to chapter 3 Testing Performance The oscilloscope circuitry in the HP 1660ES series logic analyzers requires an operational accuracy calibration by the user or service department under any of the following conditions at six months intervals or every 1 000 hours if the ambient temperature changes more than 10 Cfrom the temperature at f...

Page 133: ...ter Adapter Critical Specification BNC equal length BNC BNC tee m iflll BNC 1111 ug 914 u Recommended ModellPart HP 8120 1838 HP 8120 1840 HP 1250 0781 HP 1250 0080 Set up the equipment Turn on the logic analyzer Let it warm up for 30 minutes if you have not already done so 4 3 ...

Page 134: ...p menu 3 Select the Mode field then select Service Cal from the pop up menu 4 Select the Procedure field then select Default Values from the pop up menu 5 Select the Start field and follow the instructions on the display Scope Calibration AutoscOle Mode ServIce Col Stort FUUCTIOll GOIn Offset H stereSl Tngger De10y Tir e lIull Log 1C Tn gger I roc dure Default lalu s Continue I CI C2 p p ss d f I ...

Page 135: ...ay of the Self Cal a Obtain a BNC 50 Q 48 inch cable Once you select Start the instrument will prompt you to connect the cable to the appropriate location on the rear panel ofthe instrument b Select the Procedure field then select Delay from the pop up menu c Select the Channel field then select Cl d Select the Start field and follow the instructions on the display e Repeat steps c and d for chann...

Page 136: ...4 6 ...

Page 137: ...D display signals 5 26 To test the keyboard signals 5 27 To test the flexible disk drive voltages 5 28 To test the hard disk drive voltages 5 30 To perform the BNC test 5 31 To test the logic analyzer probe cables 5 32 To verify pattern output HI 1660EP series only 5 36 The ether address 5 38 To test the auxiliary power 5 39 Troubleshooting ...

Page 138: ...fective assemblies This instrument can be returned to Hewlett Packard for all service work including troubleshooting Contact your nearest Hewlett Packard Sales Office for more details CAUT ION Electrostatic discharge can damage electronic components Use grounded wriststraps and _______ mats when you perform any service to this instrwnent or to the cards in it To use the flowcharts Flowcharts are t...

Page 139: ...TtST PROL OURE 00 SELF TeSTS PASS ODES OSCILLOSCOPE FUN JION YES HART 8 YES ODES FRONT PAN L KEYBOARD WORK YES O 0 Cf ART 5 DOCS PAT1LRN GENeRATOR FUNCTION o 0 HART U DOES HARD DISK ORIV WORK I YES DOES O J O 0 FLEXIBLE DISK DRIVE 6 WOf1 O HART 6 I Y S j L _ ODES RS 232 L f UNL1ION_ YES DOES HB i8 FUNC1ION_ HART 9 UIART 10 Troubleshooting Flowchart I DOES 0 MOUSUKLYBOARO rUNUION CHART 11 I YES OOL...

Page 140: ...TOP COVER AND CHECK FAN CONNECTION IS FAN CABLE CONNECTED YES TURN ON POWER AND CHECK POWER SUPPLY VOLTAGES NO NO REPLACE FUSE RESEAl FAN CABLE ON CONNECTOR POII R SUPPLY VOLTAGES OK YES REMOVE FAN CABLE AND CHECK VOLTAGES N O 3 CHART 3 IS FAN VOLTAGE OK REPLACE ACQUISITION BOARD Troubleshooting Flowchart 2 5 4 YES REPLACE FAN 01 61lDZ6 ...

Page 141: ...INO II REPLACE SWEEP ABLE YES YES I POWER SUPPI_ Y VOL TAGES OK NO POWER SUPPl Y VOL 1AGES OK REMOVE CPU BOARD CABLE FROM A OU151 110N BOARD NO REMOVE l ACQUISITION BOARD I cABL FROM POWER 5UPPL y REPLACE BOARD ABLE POWER 5UPPL Y VOL TAGES OK YES ACQUISITION ABLE CONTINUITY OK YES REPLACE ACOUISITION BOARD NO NO 01660101 RlYLA ACOUISITION ABLE I I 1 __ RLPLACE poweR 5Uf PL Y ASSEMBLY Troubleshooti...

Page 142: ...s y Cl fART 1 CHECK THAT THE VIDEO DATA CABLE IS SEATED ON CPU AND ON LCD DISPLAY IS CABLE SEATED 7 NO DO TO TEST THE LCD DISPLAY SIGNALS TEST YES Troubleshooting Flowchart4 5 6 YES SEAT CABLE ON BOTH CPU BOARD AND ON LCD DISPLAY UIART 4 ...

Page 143: ...RT 5 PERFORM FRONT PANEL KEYBOARD SELF TEST PASS YES SELF TEST NO CHECK SIGNAL INPUT TO KEYBOARD INPUT SIGNALS OK YES NO KEYBOARD CABLE CONTINUITY OK NO YES REPLACE CPU BOARD ASSEMBLY REPLACE KEYBOARD ASSEMBLY Troubleshooting Flowchart 5 016600Z9 5 7 ...

Page 144: ...to To lesl Itle flexible disk dflve vol loges 10 verify flex ble disk olive vall ages Refer to To lesl the hard disk drive I ollages 10 verily hord disk drive vall ages U ART 6 SIGNALS AND VOLT AGES OK YES NO DISK DRIVE IIBLE CONTINUITY OK NO YES REPLACE CPU mARD ASSEMBLY REPLACE DISK DRIVE CABLE 01660B60 Troubleshooting Flowchart 6 5 8 REPLACE DISK DRiVe ...

Page 145: ...O ACQUIRE DATA _N_O_ o l REPLACE ACQUISITION BOARD ASSEMBLY NO NO TROUBLE fOUNO NOTE VERIFY THAT THERE ARE NO BENT OR BROKEN PINS ON THE SYSTEM BOARD CABLE CONNECTOR HP PART NUMBER 1252 4181 OOCS FAILURE fOLLOW THE SUSPECT PROBE TIP ASSEMBL Troubleshooting Flowchart7 YES YES REPLACE PROBE TIP ASSEMBLY REPLACE CABLE S END 5 9 ...

Page 146: ...PERAliNG SYSTEH DISK IS CORRECT OPERATING SYSTEM USED OBTAIN CURRENT NO 166OCS_ O ATIONAL f SYSTEM SOFTWARE ATTEI1PT TO OBTAIN AN OSCILLOSCOPE ACOUISITION YES IS DATA CORRECT NO CHECK PROBES ARE PROBES GOOO FIXED YES NO RESEAl OSOLLOS OPE BOARD CABLE WS AXED YES REPLACE PROBES REPLACE OSCILLOSCOPE BOARD REPLACE OSCILLOSCOPE BOARD END Troubleshooting FlowchartS 5 10 ...

Page 147: ...URA TlON IS LOOPBACK CONNECTOR INST ALLED YES H CK RS 23ze ABLE IS SEA TED IN CORRECT SOlKE ON CPU BOARD STALl CONNECTOR N0 j I N RS 232C PORl LAND RE RUN lESI DOES EXTERNAL lOQPBA K TES1 fAIL YES NO 1 IS ABLE SEATED YES CHECK RS 232C ABLE CONTINUITY NO RESEAl ABLE AND RE RUN lESI DOES EXTERNAL LOOP BACK TEST fAIl7 YES J J IS CABLE GOOD Troubleshooting Flowchart 9 1 CL 0 5 11 ...

Page 148: ...ERNAL lOOPBACK TEST DOES TEST PASS NO ARE RS 232C HP IB CABLES SWITCHED ON CPU BOARD YES SWITCH CABLES AND RERUN RS 232C TEST Troubleshooting Flowchart to 5 12 NO NO YES NO REPLACE CPU BOARD RECONFIGURE HP IB CHECK HP IB CABLE IS SEATED ON SOCKET ON CPU BOARD IS ABLE SEATED YES CHECK CABLE CONTINUITY IS ABLE GOOD YES NO NO RESEAl CABLE REPLACE CABLE REPLACE CPU BOARD ENO ...

Page 149: ...BOARD OR MOUSE TO EXTERNAL KEYBOARD CONNECTOR DOES KEYBOARD OR MOUSE CURSOR APPEAR NO YES REPLACE CPU BOARD DOES KEYBOARD OR MOUSE OPERATE PROPEl lLy7 NO YES aalS PS2 rr ST PASS NO Troubleshooting To use the flowcharts UIART 11 YES I Troubleshooting Flowchartll 5 13 ...

Page 150: ...wcharts UIART 1 REPLACE CPU BOARD IS LAN INSTALLED 7 YES DOES LAN TEST PASS 7 NO I L DISREGARD ST ATUS N_O1 01660863 YES I _ REFER TO USER S GUIDE TO ENSURE LAN PARAMETERS ARE PROPERLY SET l _I END Troubleshooting Flowchart 12 5 14 ...

Page 151: ...oting To use the flowcharts C IART 13 DOES YES PROBLEM NO TEST PASS7 STILL PRESENl 1 NO iYES REAR I PANEL ABLES NO CONNECT rONNEC TED TO ACQUISITION ABLES BOARD YES I lACC L 0 ND J A QUISITION BOARD 01660865 Troubleshooting Flowchart13 5 15 ...

Page 152: ...PUI TES1 I PASS REPLIICE POD WITH KNOWN GOOD POD AND REPEAT PROCEDURE ODES PATTERN OUTPUT 1 51 _ PASS REPLACE ABLE WITH KNOWN GOOD ABLE 1 10 REPEAl PROCEDURE CHECK OPERATING SYSTEM DISK REPLAC DEFECTIVE SOARD lM PAlTERN GENERATOR IS FUN IIONING PROFERLY REPLACE SUSPECT POD CHART 1t CORRlL 1 OPeRATING SYSTEM USED YLS mn llN CURReNT h VERSION OF 16 OC_ SERIES OPERA liNG oe W J DOlS PATTERN OUTPUT Tl...

Page 153: ...ect all inputs then insert a formatted disk into the flexible disk drive 2 Let the instrument warm up for a few minutes then cycle power by turning off then turning on the power switch If the instrument is not warmed up the power up test screen will complete before you can view the screen 3 As the tests complete check ifthey pass or fail The Flexible Disk Test reports No Disk if a disk is not in t...

Page 154: ...k in the flexible disk drive before starting this procedure 1 If you just did the power up self tests go to step 2 If you did not just do the power up self tests disconnect all inputs then turn on the power switch Wait until the power up tests are complete 2 Press the System key then select the field next to System Then select Test in the pop up menu liPID S lung rinl I Hord li 1 EHernal 110 PrInl...

Page 155: ...he j losh ROn components Ron Test pro9rorrmobl ROil 119Stl ROM rUnS loi lur 5 6 Select Run then select Single To run a test continuously select Repetitive Select Stop to halt a repetitive test Rorl TeH progforMloble Ron i 1ash ROM Repe tl U ve ThIS test performs 0 Chan Sum test progrllmmoble ROil and ttl floSh COllcel For a Single run the test runs one time and the screen shows the results ThiS le...

Page 156: ...aining System Tests in the same manner 9 Select the Front Panel Test A screen duplicating the front panel appears on the screen a Press each key on the front panel The corresponding key on the screen will change from a light to a dark color b Test the knob by turning it in both directions c Note any failures then press the Done key a second time to exit the Front Panel Test The test screen shows t...

Page 157: ...sts SIHUS UrlTESTED CtOlP 5 Tests statu UrHESTED Boord Tests s ta Ius WITESTED All AMly er Tests ll ltus WITESTED 12 In the Chip 2 Tests menu select Run then select Single The test runs one time then the screen shows the results When the test is finished select Done Then perform the other Chip Tests To run a test continuously select Repetitive Select Stop to halt a Run Repetitive fill lures o o o ...

Page 158: ...lonlng cnrrectlg Ild should not be used 1n 0 meosurement If you have an HP 1660E series logic analyzer no oscilloscope or pattern generator go to step 19 If you have an HP 1660EP series logic analyzer go to step 18 If you have an HP 1660ES series logic analyzer continue with step 15 15 Select Analy PV then select Scope PV in the pop up menu Select Functional Tests 16 Select one of the Scope PV tes...

Page 159: ... all tests at one time except the Output Patterns routine by selecting All Tests To see more details about each test you can run each test individuaily This example shows how to run the Clock Source Test The Vector Memory Test Address Counter Test and instruction Tests are run in a similar manner When the tests finish the status for each test shows Passed or Failed Select Done 1600C PERFOp rliUlCE...

Page 160: ...n the instrument 3 Check for the 5 V as indicated by the figure below Loaded by the added resistor 1 Turn off the instrument then remove the power cable Remove the cover of the instrument and the disk drive assembly 2 Remove the power supply far enough to disconnect the power supply cable from the acquisition board Bring the end of the cable up and out ofthe instrument Use the disconnected cable t...

Page 161: ... 13 12V 4 5 00V 14 Ground 5 Ground Digital 15 12V 6 Ground Digital 16 Ground 7 Ground Digital 17 12 V Display 8 Ground Displayl 18 5 20 V 9 3 50 V 19 15 V Fanl 10 Ground 20 Ground IFan tA 0 5 DOV P n 1 f ronl of 0 j OOV Instrumenl 0 SODV 0 SODV 0 Ground Dlspluy 0 Ground Dlsploy 0 Ground DISpluy 0 Ground DISploy 0 3 SOy 0 Ground 0 5 lOY 0 Ground 0 12V 0 Ground 0 12V 0 Ground 0 12V lDlSPlay 0 520Y 0...

Page 162: ...oes not obstruct the CPU board yet provides access to probe J4 on the CPU board b Connect both the line filter and the power output cable to the power supply c Ensure the power supply does not contact any other subassembly in the instrument 3 Using an oscilloscope probe the following pins ofJ4 for digital signals 12 13 14 16 17 18 20 21 22 24 25 26 28 29 30 23 33 34 5 26 lJTTTl TTTlT c ...

Page 163: ...RT and the CRT driver board This procedure is to be performed by service trained personnel aware ofthe hazards involved _______ such as fire and electrical shock 1 Turn off the instrument and remove the power cable 2 Without disconnecting the keyboard cable follow the keyboard removal procedure to loosen the keyboard Leave the keyboard in place in front of the instrument 3 Reconnect the power cabl...

Page 164: ...and electrical shock Equipment Required Equipment Digitizing Oscilloscope Critical Specification 100 MHz Bandwidth Recommended Model part HP 54600B 1 Tum off the instrument then remove the power cable Remove the instrument cover and the disk drive assembly 2 Reconnect the disk drive cable to the rear ofthe flexible disk drive Turn the disk drive assembly over so that the solder connections ofthe c...

Page 165: ...67UeOl INDEX DRIVE SELECT DISK CHANGE READY MOTOR ON DIRECTION SELECT STEP WRITE DATA WRITE GATE TRACK 00 WRITE PROTECT READ DATA SIDE ONE SELECT 7 Select Stop and turn off the logic analyzer Remove the power cable The test will not immediately stop when Stop is selected it will continue until the current iteration of the disk test is completed and then stop 8 Disconnect the disk drive cable and r...

Page 166: ...nstrument cover and the disk drive assembly 2 Remove the two locking pins from the top of the power supply Slide the CPU board out of the instrument enough to access Jl2 on the outer edge of the CPU board 3 Connect the power cable then turn on the instrument 4 In the Sys PV menu select the Disk test Select Run Repetitive 5 Check for the following voltages and signals at JI2 on the CPU board using ...

Page 167: ...t HP 54600B 1250 0774 HP8120 1B40 1251 2277 1 Press the Config key 2 Assign pods I and 2 to Machine 1 To assign the pod field select the pods 1 and 2 field then select Machine 1 in the pop up menu 3 In the Analyzer I box select the Type field Select Timing in the pop up menu 4 Set up the trigger menu a Press the Trig key Select Clear Trigger All b Select Arming Control In the Arming Control pop up...

Page 168: ...se Generator Adapter Qty 4 Coupler Qty 4 6x2 Test Connectors Qty 4 1 Tum on the equipment required and the logic analyzer 2 Set up the pulse generator according to the following table Pulse Generator Setup Timebase Mode Int Period 20 000 ns ChannelZ Mode Pulse Divide PULSE 1 Width 3 500 ns High 0 90 V Low 1 70V COMPo Disabled LED Off Period Divide Divide 1 Ampl 0 50 V Offs 0 00 V Channell Mode Pul...

Page 169: ...i TTL TTL Moster CloCI NostH Clocl Lllbt EI Lob Leb LII04 LubS LabD LIlb7 Lab8 c Select Master Clock then select a double edge for the clock ofthe pod 1lllder test Tum off the other clocks AnOly er Format tlAClHNE 1 Slole AcqUISitIon MOde Full ChonnelJ lK Memory lC OnH2 noster ClOCk QUALS Ol 02CEJ 03 8D l S upfHOld d In the Master Clock menu select SetuplHold then select 4 0 0 0 ns for the pod bei...

Page 170: ...up the Trigger menu a Press the Trigger key b Select Modify Trigger then select Clear Trigger then select All Anoly er J Tngger MAtHIUE I Print Armlog Control qUl51tlOn Control Docle e Sequence Lovel Mod i f Y Sequence Levo I Reploce Sequence Level Stole Sequence Lov Hhlln storing Qnyslolo TRIGGER on 0 1 lHlW o 6 Set up the Listing menu a Press the List key b Select the field to the right of Base ...

Page 171: ... upper byte ofthe pod under test to the pulse generator channel 2 Output 8 On the logic analyzer press Run The display should look similar to the figure below L n l LobI D e 8lnar 1101010101010101 1010 10 1010 1 10 10 1101010101010101 1010 lO 1010 10 10 10 010101010101010 I 1010 10 10 10 10 10 10 010101010101 1101 1010101010101010 6 0101010101010101 1010101010101010 Hi 0101010101010101 11 10101010...

Page 172: ...rns In the pop up menu touch Checkerboard Pattern Pott Gpn 1660 fIOTE au Output Test Patterns Instruction Test Slottls UNTESTE EJ StllP All Tests Ctwckerbo6rd Pot tern liolking Ones Pattern EJ 50tlHZ Output 11ode CIocr Source Tes Stolu PASSED Vee lOf ttemory Te 5 otos UNTESTE Address Counter T 51 lu UNTESTE 3 Using an oscilloscope verify the existence oflogic level transitions by touching the osci...

Page 173: ...robe 4 Repeat step 3 for each ofthe remaining four data pods 5 Connect one ofthe 10460 series clock pods to the end ofthe pattern generator clock cable 6 Using the oscilloscope as in step 3 verify the existence oflogic Ievel transitions by touching the oscilloscope probe to each clock output ofthe clock pod 7 In the pattern generator Output Patterns menu touch Stop then touch Done to exit the menu...

Page 174: ...not appear use the following procedure to re enter the original Ether address after replacing the CPU board The Ether address is on a sticker on the rear panel of the instrument 1 Look on the rear panel for the Ether Address sticker On the sticker is the 12 digit Ether address If desired write down the number 2 After the instrument rmishes booting push the System Jkey The instrument should be in t...

Page 175: ...s the circuit will open When the short is removed the circuit will reset in approximately 1minute There should be 5 V after the 1 minute reset time Equipment Required 0 1 mVresolution better than HP E2373A 0 005 accuracy Equipment Digital Multimeter Critical Specifications Recommended Model Parl Using the multirneter verify the 5 V on pins 1 and 39 of the probe cables 1 5V 2 GND MISC EXS3 5 39 ...

Page 176: ...Troubleshooting To test the auxiliary power 5 40 ...

Page 177: ...bly 6 11 HP 1660E series acquisition board 6 12 HP 1660ES series oscilloscope board 6 13 HP 1660EP series pattern generator board 6 14 Front panel and keyboard 6 15 To remove and replace the LCD display 6 16 Handle plate 6 17 Fan 6 18 Line filter 6 18 HP 1660EP series pattern generator cables 6 19 HP IB and RS 232 C cables 6 19 I O board 6 20 To return assemblies 6 20 Replacing Assemblies ...

Page 178: ... Never attempt to remove or install any assembly with the instrument on or with the power cable cormected Replacement Strategy These replacement procedures are organized as if disassembling the complete instrument from the first assembly to be removed to the last Some procedures say to remove other assemblies of the instrument but do not give complete instructions Refer to the procedure for that s...

Page 179: ...inet WS Power supply cable A9 Power supply MPll Handle plate W9 Cable 50 conductor Al0 Hard disk drive MP19 Insulator Wl0 Hard disk drive cable All Flexible disk drive MP20 Mounting plate Wll I Or cable Al2 SIMM MP23 Label W12 Display Cable Al3 LCD display MP24 Label Wl3 Inverter cable Al4 Fan MP25 Elastomeric keypad H3 Locking pin MP26 RPG knob H4 BNC connector MP27 Keyboard panel H29 Hex nut lHl...

Page 180: ...ies __ MP17 1 lY _____ MP9 7r 7 A6 21 Hi MP4 MP5 h MP3 H29 H3D MP22 HZ MP33 H36 4 W MP6 I _A15 J r W9 Al A MP19 1 W10 He 2 A10 W1 All W3 MP11 A13 MP23 A9 A12 6 MPa 3 Oll we A1 MP26 MP21 Exploded View 01the HP 1660E 6 4 ...

Page 181: ...ce the cover 1 Tum off the power and unplug the logic analyzer 2 Remove the probe plate and dIsconnect the logic analyzer cables from the rear panel 3 Using the previous procedures remove the handle and the four rear feet 4 Remove the seven screws from the front moldIng then slide the molding forward to remove it 5 Remove the cover To remove the cover set the instrument upright and facing toward y...

Page 182: ... four screws that attach the flexible disk drive to the bracket There are two on each side c Lift the flexible disk drive out of the bracket d To remove the interface board remove one screw that attaches the interface board to the bracket and lift the board out ofthe bracket 6 Remove the hard disk drive from the bracket a Disconnect the hard disk drive cable from the hard disk drive When connectin...

Page 183: ...he chassis 3 Slide the power supply out far enough to reach the power supply cables then disconnect them from the power supply 4 Slide the power supply the rest ofthe way out the side of the instrument 5 Reverse this procedure to install the power supply Check that the following assemblies are properly installed before installing the power supply LCD display Front Panel Switch Actuator CPU Board T...

Page 184: ...e ofthe instrument 5 Reverse this procedure to install the CPU board When connecting the LCD data cable to the CPU board ensure the blue side of the cable faces away from the SIMM memmory Check that the following assemblies are properly instaJIed before installing the CPU board LCD display Front Panel Switch Actuator After replacing the CPU board you will have to restore the ether address in the C...

Page 185: ...erfrom the instrument before performing the following procedures After disconnecting the power wait at least three minutes for the capacitors to discharge before servicing the instrwnent 2 Hold the release tabs away from the SIMM single inline memory module then pull the module out 3 Reverse this procedure to install a replacement SIMM Slide the SIMM module into the connector at an angle then push...

Page 186: ...r c Slide the cable out ofthe switch assembly Ou ler N i pp I e line filler SWllch MounLing Chass s Swi ldl P Iunger Cable Clamp 4 Remove the switch actuator assembly from the front of the cabinet To remove depress the retaining ears on both sides of the assembly next to the front panel and push the assembly out the front 5 Install the new switch actuator assembly Make sure that the line filter sw...

Page 187: ...from both BNC Cal ports b For the HP 1660EP series logic analyzers dlsconnect the pattern generator cable from the pattern generator board 6 Remove the six rear panel screws 7 Lift the rear panel away from the chassis 8 Reverse this procedure to install the rear panel Check that the following assemblies are properly installed before installing the rear panel Monitor Acquisition Board Oscilloscope ...

Page 188: ...y cable 4 Slide the mounting plate out the rear of the instrument Verify that all cable release tabs are down to slide the mounting plate out then slide the mounting plate toward the rear out of the chassis 5 Separate the acquisition board from the mounting plate by removing the screw at the center of the board 6 Reverse this procedure to install the acquisition board Check that the following asse...

Page 189: ...t of the chassis 6 Remove the oscilloscope board a Disconnect the acquisition board oscilloscope board interface cable from the oscilloscope board To do this press down on the cable release tabs on the cable socket located on the board b Remove the screw at the center ofthe oscilloscope board that secures the board to the mounting plate c Slide the board approximatly 0 5 em and lift the board off ...

Page 190: ...e out then slide the mounting plate toward the rear out of the chassis 5 Remove the oscilloscope board a Disconnect the acquisition board oscilloscope board interface cable from the oscilloscope board To do this press down on the cable release tabs on the cable socket located on the board b Remove the screw at the center of the oscilloscope board that secures the board to the mounting plate c Slid...

Page 191: ...cer When installing the spacer insert the pins of the spacer in the appropriate holes in the chassis You can hold the spacer in place while installing the front panel by holding it with your finger through the disk drive mounting slot in the chassis 5 Remove the RPG knob by pulling the knob off the RPG shaft 6 Disassemble the front panel assembly by lifting the keyboard circuit board away from the...

Page 192: ...n back ofthe LCD display b Disconnect two cables on the LCD display from the LCD Inverter c Remove four screws one at each comer ofthe LCD display that secure the display to the bezel d Remove the LCD display from the bezel When connecting the LCD data sable to the LCD display ensure the blue side ofthe cable faces toward the LCD display 3 Remove the Inverter Board a Disconnect the CPU Inverter Ca...

Page 193: ... remove the following assemblies Handle RearFeet Cover 2 Remove the four screens that attach the handle plate to the chassis 3 Remove the handle plate To remove the handle plate align the plate toward the front of the instrument then move it up and out of the instrument 4 Reverse this procedure to install the handle plate 6 17 ...

Page 194: ...he correct orientation of the fan If you mount the fan backwards the instrument will overheat Also check the correct polarity of the fan cable To remove and replace the line filter 1 Using previous procedures remove the following assemblies Handle Rear Feet Cover Disk Drive Assembly Power Supply Rear Panel 2 Unsolder the ground wire from the lug on the rear panel 3 Disconnect the line filter cable...

Page 195: ...e from the pattern generator board and feed the cable through the rear panel 4 Reverse this procedure to install the replacement cable To remove and replace the HP IB and RS 232 C cables 1 Using previous procedures remove the following assemblies Handle Rear Feet Cover Disk Drive Assembly Power Supply Rear Panel 2 Remove the two hex standoffs connecting the HP IE cable then slide the HP IE cable f...

Page 196: ...erse this procedure to install the I O board onto the rear panel To return assemblies Before shipping the logic analyzer or assemblies to Hewlett Packard contact your nearest Hewlett Packard Sales Office for additional details 1 Write the following information on a tag and attach it to the part to be returned Name and address of owner Model number Serial number Description of service required or f...

Page 197: ... 7 Replaceable Parts Ordering 7 2 Replaceable Parts List 7 3 Exploded View 7 4 Power Cables and Plug Configurations 7 8 Replaceable Parts ...

Page 198: ... local Hewlett Packard Sales Office when the orders require billing and invoicing Transportation costs are prepaid there is a small handling charge for each order and no invoices In order for Hewlett Packard to provide these advantages a check or money order must accompany each order Mail order forms and specific ordering information are available through your local Hewlett Packard Sales Office Ad...

Page 199: ...d view does not show all of the parts in the replaceable parts list Information included for each part on the list consists ofthe following Reference designator Hewlett Packard part number Total quantity included with the instrument Qty Description ofthe part Reference designators used in the parts list are as follows A E F H MP W Assembly Miscellaneous Electrical Part Fuse Hardware Mechanical Par...

Page 200: ...Replaceable Parts Exploded View Exploded View jJ__ MP17 4 11 11 He 2 AU Mf 2J MP27 MPZ _ _ M 9 i AO l 1 5 W W3 Exploded view ofthe HP 1660 logic analyzer 7 4 ...

Page 201: ...1662t ES EPj A8 01650 61608 1 Probe tip assembly IHP 1663t ES EPj A9 0950 2261 Power supply Al0 0950 2801 Hard Disk Drive All 0950 2782 Aexible Disk drive A12 1818 5623 2048K x32 SIMM A13 2090 0576 LCD Display assembly A14 3160 1013 Fan tubeaxial A15 16550 61605 4 Probe cable HP 1660t ES EP A15 16550 61605 3 Probe cable HP 1661t ES EPj A15 16550 61605 2 Probe cable HP 1662t ES EPj A15 16550 61605 ...

Page 202: ...eries only MP4 01660 00203 Rear panel 1660EP series only MP4 01660 00204 Rear panel 1660ES series only MP5 54501 62702 Line filter assembly MPB 01660 60003 Cabinet assembly MP9 01660 0410B Cover assembly MPIO 54Bl0 44901 Handle vinyl grip MPl1 01660 01202 1 Handle plate MP13 35672 21703 2 Strap retainer MP14 54Bl0 45001 1 Handle end cap MP15 5041 9167 2 Foot MP16 1460 1345 2 Tilt stand MP17 01660 ...

Page 203: ...01 RS 232 C cable W4 01660 61616 Aexible disk drive cable W5 01660 61604 Cable 60 Conductor W6 01660 61607 Jumper cable assembly orange W7 01660 61608 Jumper cable assembly wht W8 54503 61606 Power supply cable W9 01660 61604 Cable 60 Conductor HP 1660ES and 1660EP series only W10 01660 61615 Hard disk drive cable Wll 01660 61611 I O board cable W12 01660 61618 Display cable W13 01660 61619 Invert...

Page 204: ...urations This instrument is equipped with a three wire power cable The type of power cable plug shipped with the instrument depends on the country of destination The W15 reference designators table previous page show option numbers of available power cables and plug configurations 7 8 ...

Page 205: ...oard 8 7 The Oscilloscope Board 8 10 The Pattern Generator Board 8 13 Self Tests Description 8 15 Power up Self Tests 8 15 System Tests System PV 8 16 Analyzer Tests Analy PV 8 20 Oscilloscope tests Scope PV 8 22 Pattern Generator tests patt Gen 8 23 HP IB 8 27 RS 232 C 8 28 Theory of Operation ...

Page 206: ...f operation for the logic analyzer and describes the self tests The information in this chapter is to help you understand how the logic analyzer operates and what the self tests are testing This information is not intended for component level repair 8 2 ...

Page 207: ...tion boards A block diagram is shown with each theory The HP 1660ElES EP Series Logic Analyzer I I OO O LCD ULsploy 110 OO ll d I I I IKE YPQd one RPG I 1 OIy I Hp 1El onnec lo I I RS 2J2 l lomllKlor I I CPU Boord I Power Supply Sysle l RAM Pollern Gefl uulor Boord Osc llloscope Soma CPU The HP 1660EjESjEP Logic Analyzer 8 3 ...

Page 208: ...g system is on the disks The DRAM stores the instrument configuration acquired data to be processed and any inverse assembler loaded in the instrument by the user LCD Display Controller and Display RAM Two RAMDAC 1Cs store the video information then supply the data to a proprietary color palette A video frame generator 1C provides the sync signal to the display to create new frames Disk Drive Cont...

Page 209: ...ers receivers interface the instrument with data communications equipment Slew rate control is provided on the ICs eliminating the need for external capacitors LCD Display Assembly The LCD dicplay is a Mitsubishi 8A inch industrial quality TFT active display 6 bits of display data from the CPU board result in a 640x480 VGA resolution at the display Flexible Disk Drive The disk drive assembly is a ...

Page 210: ...a Centronics port and two mini DIN PS 2 ports for the HP I660EIESIEP series products On products ordered with the LAN interface the 1 0 board also includes isolation circuitry and LAN connectors for the LAN Hard Disk Drive Interface Buffers interface the hard disk drive with the logic analyzer backplane Hard DIsk Drive The Hard Disk Drive is an IDE compatible disk drive A 40 pin IDE connector allo...

Page 211: ...gic Acquisition Board Pods 1 2 Theory of Operation The Logic Acquisition Board f I 1 Pods 7 8 1660 1661 unlyl 1 1 r F I I 7 16 __ A l t n I bl 1 0 I i i illwr l1 I I Do I lrvo u Th Logic Acquisition Board 8 7 ...

Page 212: ...s on the circuit board are resistive terminations that reduce transmission line effects on the cable The terminations also improve signal integrity to the comparators by matching the impedance of the probe cable channels with the impedance of the signal paths of the circuit board All 17 channels of each pod are terminated in the same way The signals are reduced by a factor of 10 Comparators Two pr...

Page 213: ...ich allows you to set the thresholds of the individual pods The 16 data channels and the clock channel of each pod are all set to the same threshold voltage Test and Clock Synchronization Circuit ECLinPS TM ICs are used in the Test and Clock Synchronization Circuit for reliability and low channel to channel skew Test patterns are generated and sent to the comparators during software operation veri...

Page 214: ...P CLOCK j SELECT 100 MHZ I as SYNC 9 TIMEBASE HYBRID W HT ANALOG H2 ARM TRIGGER QVAL TRIGGER TRIG LOuie lRI illER Al AL IM6 A w 0 0 4 4 4 0 OPE DIGIT AL A ON 9 INTERFI CE Y v f ANAlOCl IN Ill ll ALL _ ___ DAU ____ n f I 1 __ r _____________ I ACOUI llIQN BOARD IIC Al OUTPUT CHANT IN r l _ HAN L IN or CAL OUIPUI TO OSCILLOSC AlQUISlll IRCUITR The Oscilloscope Board 8 10 ...

Page 215: ... system timing and sample clocking A voltage controlled oscillator yCO frequency divider and digital phase detector provide the sample clock for higher sample rates After conditioning and sampling the signals are digitized then stored in a hybrid lC containing a FISO fast in slow out memory ADC The eight bit ADC digitizes the channel signal Digitization is done by comparators in a flash converter ...

Page 216: ...base The time base then sends a pulse to the fine interpolator The pulse is equal in width to the time between the trigger and the next sample clock The fine interpolator stretches this time by a factor of approximately 500 Meanwhile the time base hybrid runs a counter with a clock derived from the sample rate oscillator When the interpolator indicates the stretch is complete the counter is stoppe...

Page 217: ...ases the next vector address location would be the start of the vector listing Consequently the vectors would continue to loop from the end of the listing back to the beginning until the user instructs the module to stop RAM Consisting of six 256Kxl6 VRAM ICs and RAM addressing circuitry the RAM stores the desired patterns that appear at the output The RAM addressing circuitry is merely a counter ...

Page 218: ...ock select multiplexer The output of the multiplexer which represents the user selected clocking rate is distributed to the above listed subcircuits on both the master board and all expander boards that are configured with the master board The output of the clock select multiplexer is also distributed to an external clock out circuit The clock signal is routed to a bank of external clock delays an...

Page 219: ...s and monitors test data for the logic analyzer to read The performance verification procedures in chapter 3 of this service guide make up the parametric performance verification for the logic analyzer Refer to chapter 3 Testing Performance for further information about parametric performance verification Power up Self Tests The power up self tests are divided into two parts The first part is the ...

Page 220: ... that the interrupt circuitry is ftmctioning properly Passing the Interrupt Test also implies that the interrupt generating devices are ftmctioning properly and not generating false interrupts This means that the microprocessor can execute the operating system code and properly service interrupts generated by pressing a front panel key or receiving an HP IB or RS 232 C command System Tests System ...

Page 221: ... functioning and that the keyboard controller can communicate with the microprocessor in the logic analyzer Incoming PS2 information from the external keyboard will not be corrupted by the pathway between the keyboard controller and microprocessor Disk Test The disk test verifies the operation of both the flexible disk drive and hard disk drive For the flexible disk drive the disk test exercises t...

Page 222: ...sponding front panel key and the two RPG fields can be toggled by turning the knob The Front Panel Test is not called when Perform Test All is selected Display Test When initiated the display test will cause three test screens to be displayed sequentially The first test screens is a test pattern used to align the CRT The second two screens verify correct operation of the color palette by displayin...

Page 223: ...ing properly If this bit is sel then the LAN module is not able to properly transmit and receive packets and must be replaced Bit 5 The ENOEC Encoder Decoder bit indicates whether the encoder decoder internal to the LAN IC is functioning The encoder decoder is the interface between the MAC and the Ethernet transceiver If this bit is sel then the ENOEC is not operating properly and the LAN module m...

Page 224: ...ions pipeline between the various subsystems of the IC are operating Checkerboard patterns of Is and Os are routed to the address and data buses and to the read write registers of each chip After verifying the communications pipelines the acquisition clock synchronization signals that are routed from IC to IC are checked Finally the IC master clock optimization path is checked and verified Passing...

Page 225: ...hat all possible sequence level jumps can occur Also passing this test implies that user dermed ANDing and ORing of storage qualified data patterns will occur and that the occurrence counter that appears at each sequence level is functioning Clock Generator Test The master clock generator on the acquisition ICs is tested by fIrst checking the operation of the clock optimization circuit The state a...

Page 226: ...tect when one clock period has elapsed The clock period time interval is then compared with a known value AID Test This test verifies the correct operation of the AID converter on the board A check ofthe trigger in Trigger Immediate mode is first made The AID converters are then exercised by setting the reference voltage and channel offset such that a simulated acquisition obtains data in the extr...

Page 227: ... pattern of each nibble has the following definition o passed 1 failed to run 2 failed to stop 3 failed to both run and stop Vector Memory Test The Vector Memory Test does a first order check of the functionality of RAM The first pass of the test will load the entire RAM with OxOOOO The software will step the clock enough times to output one page worth of data At each clock a test read port for ea...

Page 228: ...e loop registers are operating correctly Diagnostic Integer Valne This test checks the counters of the entire board The returned integer has the following format 81T 115 114 13 12 11 10 9 8 7 6 Row Col Fail row Bit 15 is used to flag where the value of the fail row bits 6 14 came from If the failing row value was less than 511 bit 15 is set to zero If the failing row was greater than 511 bit 15 is...

Page 229: ...s begun for the vectors to hit the break instruction on the third page The main status is checked to see that the hardware is stopped by the break instruction The second pass of the test places a wait on any condition in the event register Again the hardware is started wait is begun On this pass the hardware should be stopped by the wait condition and not by the break condition The final pass clea...

Page 230: ...nteger Value The integer returned will have the following bit format BIT 115 14 13 12 11 10 9 8 7 6 5 4 13 2 1 0 unused Test Mode The Test Mode bit positions have the following meaning o passed 1 failed to stop on wait in non if branch 2 took if branch on no branch event 4 failed to stop on break in if branch 8 took non if branch on any branch event Output Patterns for testing with an external log...

Page 231: ... bit ASCII code normally represents each piece of data Data is transferred by means of an interlocking Handshake technique which permits data transfer asynchronously at the rate of the slowest active device used in that transfer The data byte control lines coordinate the handshaking and form the second functional group The remaining five general interface management lines third functional group ar...

Page 232: ...tective Ground AA Not applicable 2 Transmitted Data lTD BA Data from Mainframe High Space 0 12 V Low Mark 1 12V 3 Received Data IRD BB Data to Mainframe High Space 0 3 Vto 25 V Low Mark 1 3 Vto 25 V 4 Requeslto Send IRTS CA Signal from Mainframe High DN 12V Low OFF 12V 5 Clear to Send ICTS CB Signal to Mainframe High ON 3 Vto 12 V Low OFF 3 Vto 25 V 6 Data Set Ready IDSR CC Signal to Mainframe Hig...

Page 233: ...te preparation or maintenance No other warranty is expressed or implied Hewlett Packard specifically disclaims the implied warranties of merchantability or fitness for a particular purpose Exclusive Remedies The remedies provided herein are the buyer s sale and exclusive remedies Hewlett Packard shall not be liable for any direct indirect special incidental or consequential damages whether based o...

Page 234: ...s not sufficient protection Only fuses with the required rated current voltage and specified type normal blow time delay etc should be used Do not use repaired fuses or short circuited fuseholders To do so could cause a shock or fIre hazard Service instructions are for trained service personneL To avoid dangerous electric shock do not perform any service unless qualified to do so Do not attempt in...

Page 235: ...FliiiW HEWLETP PACKARD Hewlett Packard Company Printed in the USA Manual Part Number 01660 97030 1111 1111 1 1 1 1 1 11 1111111 1111 111111111 111111111111111111 ...

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