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Holtek TinyPower HT69F30A Manual Download Page 74

Rev. 1.20

74

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Rev. 1.20 

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HT69F30A/HT69F40A/HT69F50A

TinyPower

TM

 I/O Flash 8-Bit MCU with LCD & EEPROM

HT69F30A/HT69F40A/HT69F50A

TinyPower

TM

 I/O Flash 8-Bit MCU with LCD & EEPROM

Watchdog Time-out Reset during SLEEP or IDLE Mode

The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds 
of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack 
Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for 

t

SST

 details.

  

           

             

WDT Time-out Reset during SLEEP or IDLE Timing Chart

Note: The t

SST

 is 15~16 clock cycles if the system clock source is provided by ERC or 

HIRC. The t

SST

 is 1024 clock for HXT or LXT. The t

SST

 is 1~2 clock for LIRC.

Reset Initial Conditions

The different types of reset described affect the reset flags in different ways. These flags, known 
as PDF and TO are located in the status register and are controlled by various microcontroller 
operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are 
shown in the table:

TO

PDF

RESET Conditions

0

0

Powe�-on �eset

u

u

RES o� LVR �eset du�ing N�RMAL o� SL�W Mode ope�ation

1

u

WDT time-out �eset du�ing N�RMAL o� SL�W Mode ope�ation

1

1

WDT time-out �eset du�ing IDLE o� SLEEP Mode ope�ation

"u" stands for unchanged

The following table indicates the way in which the various components of the microcontroller are 
affected after a power-on reset occurs.

Item 

Condition After RESET

P�og�am Counte�

Reset to ze�o

Inte��upts

All inte��upts will �e disa�led

WDT� Time Base

Clea� afte� �eset� WDT �egins �ounting

Time� Modules

Time� Modules will �e tu�ned off

Input/�utput Po�ts

I/� po�ts will �e setup as inputs

Sta�k Pointe�

Sta�k Pointe� will point to the top of the sta�k

The different kinds of resets all affect the internal registers of the microcontroller in different ways. 
To ensure reliable continuation of normal program execution after a reset occurs, it is important to 
know what condition the microcontroller is in after a particular reset occurs. The following table 
describes how each type of reset affects the microcontroller internal registers.

Summary of Contents for TinyPower HT69F30A

Page 1: ...TinyPowerTM I O Flash 8 Bit MCU with LCD EEPROM HT69F30A HT69F40A HT69F50A Revision V1 20 Date October 08 2015 ...

Page 2: ...eristics 31 System Architecture 31 Clocking and Pipelining 31 Program Counter 32 Stack 33 Arithmetic and Logic Unit ALU 33 Flash Program Memory 34 Structure 34 Special Vectors 35 Look up Table 35 Table Program Example 35 In Circuit Programming ICP 36 On Chip Debug Support OCDS 37 Data Memory 38 Structure 38 General Purpose Data Memory 39 Special Purpose Data Memory 39 Special Function Register Des...

Page 3: ...ction 56 Internal 32kHz Oscillator LIRC 56 External Clock EC 56 Supplementary Oscillators 56 Operating Modes and System Clocks 57 System Clock 57 System Operation Modes 58 Control Register 59 Fast Wake up 61 Operating Mode Switching 61 Operating Mode Switching and Wake up 62 NORMAL Mode to SLOW Mode Switching 63 SLOW Mode to NORMAL Mode Switching 64 Entering the SLEEP0 Mode 65 Entering the SLEEP1 ...

Page 4: ...ct Type TM CTM 102 Compact TM Operation 102 Compact Type TM Register Description 103 Compact Type TM Operating Modes 107 Compare Match Output Mode 107 Timer Counter Mode 110 PWM Output Mode 110 Standard Type TM STM 113 Standard TM Operation 113 Standard Type TM Register Description 114 Standard Type TM Operating Modes 123 Compare Output Mode 123 Timer Counter Mode 126 PWM Output Mode 126 Single Pu...

Page 5: ... Function 175 Clock Source 175 LCD Driver Output 175 LCD Voltage Source Biasing 176 LCD Waveform Timing Diagram 177 Programming Considerations 182 Configuration Options 183 Application Circuits 184 Instruction Set 185 Introduction 185 Instruction Timing 185 Moving and Transferring Data 185 Arithmetic Operations 185 Logical and Rotate Operations 186 Branches and Control Transfer 186 Bit Operations ...

Page 6: ...egrated internal 4MHz 8MHz and 12MHz oscillator requires no external components All instructions executed in one or two instruction cycles Table read instructions 63 powerful instructions Up to 8 level subroutine nesting Bit manipulation instruction Peripheral Features Flash Program Memory 2K 16 8K 16 Data Memory 128 8 384 8 EEPROM Memory 64 8 128 8 Watchdog Timer function Up to 52 bidirectional I...

Page 7: ...ty to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption The inclusion of flexible I O programming features Time Base functions along with many other features ensure that the devices will find excellent use in applications such as consumer products handheld inst...

Page 8: ...gram Flash EEPROM Programming Circuitry ICP OCDS Watchdog Timer 8 bit RISC MCU Core Reset Circuit Interrupt Controller ERC EC HXT Oscillator LIRC LXT Oscillator HIRC Oscillator Stack EEPROM Data Memory Flash Program Memory RAM Data Memory TM0 TMn Low Voltage Reset Low Voltage Detect Time Base I O LCD Driver TM1 ...

Page 9: ...23 PE3 SEG11 PE4 SEG12 PE5 SEG13 PE6 SEG14 PE7 SEG15 PF0 SEG16 PF1 SEG17 PF2 SEG18 PF3 SEG19 PF4 SEG20 PF5 SEG21 PF6 SEG22 HT69F30A 48 LQFP A HT69F40A 48 LQFP A 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 PA6 TP0_0 PA5 TP2_1 PA4 INT0 PA3 TP2_0 PA2 TCK0 TCK2 PA0 INT1 TCK1 PA1 TP0_1 PB1 OSC2 PB0 OSC1 VDD VSS P...

Page 10: ...EG23 PG0 SEG24 PG1 SEG25 PG2 SEG26 PG3 SEG27 PG4 SEG28 PG5 SEG29 PG6 SEG30 PA6 TP0_0 PA5 TP2_1 PA4 INT0 PA3 TP2_0 PA2 TCK0 TCK2 PA0 INT1 TCK1 PA1 TP0_1 PB1 OSC2 PB7 TP1B_2 PB6 TP1B_1 PB5 TP1B_0 PB4 TP1A PB0 OSC1 VDD VSS PB2 XT1 HT69F40A 64 LQFP A HT69F50A 48 LQFP A 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25...

Page 11: ..._2 PB6 TP1B_1 PB5 TP1B_0 PB4 TP1A PB0 OSC1 VDD VSS PB2 XT1 HT69F50A 64 LQFP A 47 46 45 44 43 42 41 HT69F50A 80 LQFP A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2526 2728 29 30 31 32 33 3435 36 3738 39 40 80 79 78 77 7675 7473 72 71 70 69 68 6766 65 6463 62 61 60 59 58 57 56 55 54 53 52 51 40 49 48 PA6 TP0_0 PA5 TP2_1 PA4 INT0 PA3 TP2_0 PA2 TCK0 TCK2 PA0 INT1 TCK1 PA1 TP0_1 PB1...

Page 12: ... SEG9 PE2 SEG10 PE3 SEG11 PE4 SEG12 PE5 SEG13 PE6 SEG14 PE7 SEG15 PF0 SEG16 PF1 SEG17 PF2 SEG18 PB3 XT2 VLCD VMAX V1 PC0 V2 PC1 C1 PC2 C2 COM0 COM1 COM2 COM3 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 PH7 SEG39 PF3 SEG19 PF4 SEG20 PF5 SEG21 PF6 SEG22 PF7 SEG23 PG0 SEG24 PG1 SEG25 PG2 SEG26 PG3 SEG27 PG4 SEG28 PG5 SEG29 PG6 SEG30 PG7 SEG31 PH0 SEG32 PH1 SEG33 PH2 SEG34 PH3 SEG35 PH4 SEG3...

Page 13: ...ster enabled pull up and wake up TP1_0 PAFS ST CMOS TM1 I O pin PA4 INT0 PA4 PAPU PAWU ST CMOS General purpose I O Register enabled pull up and wake up INT0 INTEG INTC0 ST External Interrupt 0 PA5 TP1_1 PA5 PAWU PAPU PAFS ST CMOS General purpose I O Register enabled pull up and wake up TP1_1 PAFS ST CMOS TM1 I O pin PA6 TP0_0 PA6 PAWU PAPU PAFS ST CMOS General purpose I O Register enabled pull up ...

Page 14: ...EG2 PDFS AO LCD segment output TCK1 SFS ST TM1 input PD3 SEG3 PD3 PDPU PDFS ST CMOS General purpose I O Register enabled pull up SEG3 PDFS AO LCD segment output PD4 SEG4 PD4 PDPU PDFS ST CMOS General purpose I O Register enabled pull up SEG4 PDFS AO LCD segment output PD5 SEG5 PD5 PDPU PDFS ST CMOS General purpose I O Register enabled pull up SEG5 PDFS AO LCD segment output PD6 SEG6 PD6 PDPU PDFS ...

Page 15: ...G19 PF3 PFPU PFFS ST CMOS General purpose I O Register enabled pull up SEG19 PFFS AO LCD segment output PF4 SEG20 PF4 PFPU PFFS ST CMOS General purpose I O Register enabled pull up SEG20 PFFS AO LCD segment output PF5 SEG21 PF5 PFPU PFFS ST CMOS General purpose I O Register enabled pull up SEG21 PFFS AO LCD segment output PF6 SEG22 PF6 PFPU PFFS ST CMOS General purpose I O Register enabled pull up...

Page 16: ...CMOS TM2 I O pin PA4 INT0 PA4 PAPU PAWU ST CMOS General purpose I O Register enabled pull up and wake up INT0 INTEG INTC0 ST External Interrupt 0 PA5 TP2_1 PA5 PAWU PAPU PAFS ST CMOS General purpose I O Register enabled pull up and wake up TP2_1 PAFS ST CMOS TM2 I O pin PA6 TP0_0 PA6 PAWU PAPU PAFS ST CMOS General purpose I O Register enabled pull up and wake up TP0_0 PAFS ST CMOS TM0 I O pin PA7 ...

Page 17: ...I O Register enabled pull up C2 PCFS AO LCD voltage pump PD0 SEG0 INT1 PD0 PDPU PDFS ST CMOS General purpose I O Register enabled pull up SEG0 PDFS AO LCD segment output INT1 INTEG INTC0 SFS ST External Interrupt 1 PD1 SEG1 TCK0 PD1 PDPU PDFS ST CMOS General purpose I O Register enabled pull up SEG1 PDFS AO LCD segment output TCK0 SFS ST TM0 input PD2 SEG2 TCK2 PD2 PDPU PDFS ST CMOS General purpos...

Page 18: ...er enabled pull up SEG11 PEFS AO LCD segment output PE4 SEG12 PE4 PEPU PEFS ST CMOS General purpose I O Register enabled pull up SEG12 PEFS AO LCD segment output PE5 SEG13 PE5 PEPU PEFS ST CMOS General purpose I O Register enabled pull up SEG13 PEFS AO LCD segment output PE6 SEG14 PE6 PEPU PEFS ST CMOS General purpose I O Register enabled pull up SEG14 PEFS AO LCD segment output PE7 SEG15 PE7 PEPU...

Page 19: ...7 PGFS AO LCD segment output PG4 SEG28 PG4 PGPU PGFS ST CMOS General purpose I O Register enabled pull up SEG28 PGFS AO LCD segment output PG5 SEG29 PG5 PGPU PGFS ST CMOS General purpose I O Register enabled pull up SEG29 PGFS AO LCD segment output PG6 SEG30 PG6 PGPU PGFS ST CMOS General purpose I O Register enabled pull up SEG30 PGFS AO LCD segment output PG7 SEG31 PG7 PGPU PGFS ST CMOS General p...

Page 20: ...CMOS TM2 I O pin PA4 INT0 PA4 PAPU PAWU ST CMOS General purpose I O Register enabled pull up and wake up INT0 INTEG INTC0 ST External Interrupt 0 PA5 TP2_1 PA5 PAWU PAPU PAFS ST CMOS General purpose I O Register enabled pull up and wake up TP2_1 PAFS ST CMOS TM2 I O pin PA6 TP0_0 PA6 PAWU PAPU PAFS ST CMOS General purpose I O Register enabled pull up and wake up TP0_0 PAFS ST CMOS TM0 I O pin PA7 ...

Page 21: ...S AO LCD voltage pump PC3 PC6 PCn PCPU ST CMOS General purpose I O Register enabled pull up PD0 SEG0 INT1 PD0 PDPU PDFS ST CMOS General purpose I O Register enabled pull up SEG0 PDFS AO LCD segment output INT1 INTEG INTC0 SFS ST External Interrupt 1 PD1 SEG1 TCK0 PD1 PDPU PDFS ST CMOS General purpose I O Register enabled pull up SEG1 PDFS AO LCD segment output TCK0 SFS ST TM0 input PD2 SEG2 TCK2 P...

Page 22: ...er enabled pull up SEG11 PEFS AO LCD segment output PE4 SEG12 PE4 PEPU PEFS ST CMOS General purpose I O Register enabled pull up SEG12 PEFS AO LCD segment output PE5 SEG13 PE5 PEPU PEFS ST CMOS General purpose I O Register enabled pull up SEG13 PEFS AO LCD segment output PE6 SEG14 PE6 PEPU PEFS ST CMOS General purpose I O Register enabled pull up SEG14 PEFS AO LCD segment output PE7 SEG15 PE7 PEPU...

Page 23: ...t output PG4 SEG28 PG4 PGPU PGFS ST CMOS General purpose I O Register enabled pull up SEG28 PGFS AO LCD segment output PG5 SEG29 PG5 PGPU PGFS ST CMOS General purpose I O Register enabled pull up SEG29 PGFS AO LCD segment output PG6 SEG30 PG6 PGPU PGFS ST CMOS General purpose I O Register enabled pull up SEG30 PGFS AO LCD segment output PG7 SEG31 PG7 PGPU PGFS ST CMOS General purpose I O Register ...

Page 24: ... PWR Negative Power supply Ground Note I T Input type O T Output type OPT Optional by configuration option CO or register option PWR Power CO Configuration option ST Schmitt Trigger input AO Analog output CMOS CMOS output NMOS NMOS output HXT High frequency crystal oscillator LXT Low frequency crystal oscillator Absolute Maximum Ratings Supply Voltage VSS 0 3V to VSS 6 0V Input Voltage VSS 0 3V to...

Page 25: ...Hz WDT enable 450 700 μA 5V 1000 1500 μA 3V No load fH 8MHz WDT enable 0 8 1 5 mA 5V 1 5 3 0 mA 3V No load fH 12MHz WDT enable 1 5 2 5 mA 5V 3 0 5 0 mA 5V No load fH 16MHz WDT enable 4 0 6 0 mA IDD2 Operating Current ERC fSYS fH fS fSUB fRTC or fLIRC 3V No load fH 455kHz WDT enable 66 110 μA 5V 200 300 μA 3V No load fH 1MHz WDT enable 250 400 μA 5V 500 1000 μA 3V No load fH 4MHz WDT enable 450 700...

Page 26: ...ble 0 6 1 0 mA 5V No load fH 12MHz fL fH 4 WDT enable 0 9 1 4 mA IDD8 Operating Current LXT fSYS fL fRTC fS fSUB fRTC HT69F30A HT69F40A 3V No load WDT enable QOSC 0 10 20 μA 5V 20 35 μA 3V No load WDT enable QOSC 1 10 20 μA 5V 20 35 μA IDD8a Operating Current LXT fSYS fL fRTC fS fSUB fRTC HT69F50A 3V No load WDT enable QOSC 0 10 20 μA 5V 30 50 μA 3V No load WDT enable QOSC 1 10 20 μA 5V 30 50 μA I...

Page 27: ... 1 0 1 1 μA 5V 0 3 2 μA ISTB9 Standby Current Sleep1 HXT fSYS off fS fSUB fRTC 3V No load system HALT WDT enable fSYS 12MHz 1 5 3 0 μA 5V 2 5 5 0 μA ISTB10 Standby Current Sleep1 HXT fSYS off fS fSUB fLIRC 3V No load system HALT WDT enable fSYS 12MHz 1 5 3 0 μA 5V 2 5 5 0 μA ISTB11 Standby Current Sleep0 LXT fSYS off fS fSUB fRTC 3V No load system HALT WDT disable fSYS 32768Hz 0 1 1 μA 5V 0 3 2 μA...

Page 28: ...RC 5V Ta 25 C External RERC 150kΩ 2 4 2 MHz 5V Ta 0 C 70 C External RERC 150kΩ 5 4 5 MHz 5V Ta 40 C 85 C External RERC 150kΩ 7 4 7 MHz 3 0V 5 5V Ta 40 C 85 C External RERC 150kΩ 9 4 9 MHz 2 2V 5 5V Ta 40 C 85 C External RERC 150kΩ 12 4 12 MHz fLXT System Clock LXT 32768 Hz fLIRC System Clock LIRC 5V Ta 25 C 10 32 10 kHz 2 2V 5 5V Ta 40 C 85 C 50 32 60 kHz tTIMER TCKn and timer capture Input Pulse ...

Page 29: ...3 8V option 3 8 VLVD1 Low Voltage Detector Voltage LVDEN 1 VLVD 2 0V 5 2 0 5 V VLVD2 LVDEN 1 VLVD 2 2V 2 2 V VLVD3 LVDEN 1 VLVD 2 4V 2 4 V VLVD4 LVDEN 1 VLVD 2 7V 2 7 V VLVD5 LVDEN 1 VLVD 3 0V 3 0 V VLVD6 LVDEN 1 VLVD 3 3V 3 3 V VLVD7 LVDEN 1 VLVD 3 6V 3 6 V VLVD8 LVDEN 1 VLVD 4 0V 4 0 V VBG Bandgap reference with buffer voltage 3 1 25 3 V IBG Additional Power Consumption if bandgap reference with...

Page 30: ... or 32K RC OSC 3V No load system HALT LCD on WDT off R type VLCD VDD 1 2 bias IBIAS 45μA 51 80 μA 5V 85 160 μA ISTB6 Standby Current Idle fSYS fWDT off fS fSUB 32768 or 32K RC OSC 3V No load system HALT LCD on WDT off R type VLCD VDD 1 2 bias IBIAS 90μA 96 160 μA 5V 160 320 μA ISTB7 Standby Current Idle fSYS fWDT off fS fSUB 32768 or 32K RC OSC 3V No load system HALT LCD on WDT off R type VLCD VDD...

Page 31: ...rs along with additional architectural features ensure that a minimum of external components is required to provide a functional I O control system with maximum reliability and flexibility This makes the device suitable for low cost high volume production for controller applications Clocking and Pipelining The main system clock derived from either a HXT LXT HIRC LIRC EC or ERC oscillator is subdiv...

Page 32: ...nto the Program Counter For conditional skip instructions once the condition has been met the next instruction which has already been fetched during the present instruction execution is discarded and a dummy cycle takes its place while the correct instruction is obtained Device Program Counter Porgram Counter High Byte Porgram Counter Low Byte HT69F30A PC10 PC8 PCL7 PCL0 HT69F40A PC11 PC8 HT69F50A...

Page 33: ...utine instruction can still be executed which will result in a stack overflow Precautions should be taken to avoid such cases which might cause unpredictable program branching If the stack is overflow the first Program Counter save in the stack will be lost P r o g r a m C o u n t e r S t a c k L e v e l 1 S t a c k L e v e l 2 S t a c k L e v e l 3 S t a c k L e v e l N P r o g r a m M e m o r y ...

Page 34: ... flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating Structure The Program Memory has a capacity of up to 8k 16 bits The Program Memory is addressed by the Program Counter and also contains data table information and interrupt entries information Table data which can be setup in any location within the Program Memory is add...

Page 35: ... s L a s t p a g e o r T B H P R e g i s t e r Table Program Example The accompanying example shows how the table pointer and table data is defined and retrieved from the device This example uses raw table data located in the last page which is stored there using the ORG statement The value at this ORG statement is 700H which refers to the start address of the last page within the 2K Program Memor...

Page 36: ... user with a means of convenient and easy upgrades and modifications to their programs on the same device As an additional convenience Holtek has provided a means of programming the microcontroller in circuit using a 4 pin interface This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un programmed microcontroller and then programming...

Page 37: ...ment process The devices HT69Fx0A and HT69V50A are almost functional compatible except the On Chip Debug function and package types Users can use the HT69V50A device to emulate the HT69Fx0A series of devices behaviors by connecting the OCDSDA and OCDSCK pins to the Holtek HT IDE development tools The OCDSDA pin is the OCDS Data Address input output pin while the OCDSCK pin is the OCDS clock input ...

Page 38: ...ly affect the displayed data Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value Structure The Data Memory is subdivided into several banks all of which are implemented in 8 bit wide RAM The Data Memory located in Bank 0 is subdivided into two sections the Special Purpose Data Memory and the General Purpose Data Memory The start address of...

Page 39: ...Memory is fully accessible by the user programing for both reading and writing operations By using the SET m i and CLR m i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory Special Purpose Data Memory This area of Data Memory is where registers necessary for the correct operation of the microc...

Page 40: ...H MFI1 16H 17H MFI2 Bank 0 1 SMOD1 LVRC Unused PBPU PB PBC PCPU PC PCC PDPU PD PDC PEPU PE PEC PFPU PF PFC 20H 21H 22H 29H 28H 2BH 2AH 2DH 2CH 2FH 2EH 23H 24H 25H 26H 27H 30H 31H 32H 39H 38H 3BH 3AH 3DH 3CH 3FH 3EH 33H 34H 35H 36H 37H PAFS PCFS PDFS PEFS PFFS SFS TM0C0 TM0C1 TM0DL TM0DH TM0AL TM0AH 40H EEC 41H EEA 42H EED 43H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH LCDC 5FH Bank 0 Bank 1 TM1C0 TM1C1 TM1DL...

Page 41: ... Unused PBPU PB PBC PCPU PC PCC PDPU PD PDC PEPU PE PEC PFPU PF PFC PGPU PG PGC 20H 21H 22H 29H 28H 2BH 2AH 2DH 2CH 2FH 2EH 23H 24H 25H 26H 27H 30H 31H 32H 39H 38H 3BH 3AH 3DH 3CH 3FH 3EH 33H 34H 35H 36H 37H PAFS PBFS PCFS PDFS PEFS PFFS PGFS SFS TM0C0 TM0C1 TM0DL TM0DH TM0AL TM0AH 40H EEC 41H EEA 42H EED 43H TM2C0 47H TM2C1 48H TM1C2 49H TM2DL 4AH TM2DH 4BH TM2AL 4CH TM2AH 4DH TM1BL 4EH TM1BH 4FH...

Page 42: ...C Unused PBPU PB PBC PCPU PC PCC PDPU PD PDC PEPU PE PEC PFPU PF PFC PGPU PG PGC PHPU PH PHC 20H 21H 22H 29H 28H 2BH 2AH 2DH 2CH 2FH 2EH 23H 24H 25H 26H 27H 30H 31H 32H 39H 38H 3BH 3AH 3DH 3CH 3FH 3EH 33H 34H 35H 36H 37H PAFS PBFS PCFS PDFS PEFS PFFS PGFS PHFS SFS TM0C0 TM0C1 TM0DL TM0DH TM0AL TM0AH 40H EEC 41H EEA 42H EED 43H TM2C0 47H TM2C1 48H TM1C2 49H TM2DL 4AH TM2DH 4BH TM2AL 4CH TM2AH 4DH T...

Page 43: ...t of 00H and writing to the registers indirectly will result in no operation Memory Pointers MP0 MP1 Two Memory Pointers known as MP0 and MP1 are provided These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data When any operation to the relevant Indirect Addressing...

Page 44: ...cial Function Registers can be accessed from within any bank Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer Accessing data from banks other than Bank 0 must be implemented using Indirect addressing As both the Program Memory and Data Memory share the same Bank Pointer Register care must be taken during programming Devic...

Page 45: ... Low Register PCL To provide additional program control functions the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory By manipulating this register direct jumps to other program locations are easily implemented Loading a value directly into this PCL register will cause a jump to the specified Program Memory locatio...

Page 46: ...he status of the latest operations C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation otherwise C is cleared C is also affected by a rotate through carry instruction AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtracti...

Page 47: ...V Overflow flag 0 No overflow 1 An operation results in a carry into the highest order bit but not a carry out of the highest order bit or vice versa Bit 2 Z Zero flag 0 The result of an arithmetic or logical operation is not zero 1 The result of an arithmetic or logical operation is zero Bit 1 AC Auxiliary flag 0 No auxiliary carry 1 An operation results in a carry out of the low nibbles in addit...

Page 48: ...isters are located in Bank 0 they can be directly accessed in the same was as any other Special Function Register The EEC register however being located in Bank1 cannot be addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register IAR1 Because the EEC control register is located at address 40H in Bank 1 the MP1 Memory Pointer...

Page 49: ... Write cycle has finished 1 Activate a write cycle This is the Data EEPROM Write Control bit and when set high by the application program will activate a write cycle This bit will be automatically reset to zero by the hardware after the write cycle has finished Setting this bit high will have no effect if the WREN bit has not first been set high Bit 1 RDEN Data EEPROM read operation enable 0 Disab...

Page 50: ...en written into the EEPROM Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt When the write cycle terminates the WR bit will be automatically cleared to zero by the microcontroller informing the user that the data has been written to the EEPROM The application program can therefore poll the WR bit to det...

Page 51: ... a write cycle is executed and then re enabled after the write cycle starts Programming Examples Reading Data from the EEPROM Polling Mothod MOV A EEPROM_ADRES user defined address MOV EEA A MOV A 040H setup memory pointer MP1 MOV MP1 A MP1 points to EEC register MOV A 01H setup Bank Pointer MOV BP A SET IAR1 1 set RDEN bit enable read operations SET IAR1 0 start Read Cycle set RD bit BACK SZ IAR1...

Page 52: ...vantage of higher power requirements while the opposite is of course true for the lower frequency oscillators With the capability of dynamically switching between fast and slow system clock the device has the flexibility to optimize the performance power ratio a feature especially important in power sensitive portable applications Type Name Freq Pins External Crystal HXT 400kHz 16MHz OSC1 OSC2 Ext...

Page 53: ...essary phase shift and feedback for oscillation without requiring external capacitors However for some crystal types and frequencies to ensure oscillation it may be necessary to add two small value capacitors C1 and C2 Using a ceramic resonator will usually require two small value capacitors C1 and C2 to be connected as shown for oscillation to occur The values of C1 and C2 should be selected in c...

Page 54: ...t can be noted that with an external 150kΩ resistor connected and with a 5V voltage power supply and temperature of 25 C degrees the oscillator will have a frequency of 4MHz within a tolerance of 2 Here only the OSC1 pin is used which is shared with I O pin PB0 leaving pin PB1 free for use as a normal I O pin For oscillator stability and to minimise the effects of noise and crosstalk it is importa...

Page 55: ...al even when the microcontroller is in the SLEEP or IDLE Mode To do this another clock independent of the system clock must be provided However for some crystals to ensure oscillation and accurate frequency generation it is necessary to add two small value external capacitors C1 and C2 The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer s spe...

Page 56: ... is selected via configuration option It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V requiring no external components for its implementation Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage temperature and process variations on the oscillat...

Page 57: ...e The main system clock can come from either a high frequency fH or low frequency fSUB source and is selected using the HLCLK bit and CKS2 CKS0 bits in the SMOD register The high speed system clock can be sourced from an HXT ERC or HIRC oscillator selected via a configuration option The low speed system clock source can be sourced from the clock fSUB If fSUB is selected then it can be sourced by e...

Page 58: ...peed oscillator is used running the microcontroller at a divided clock ratio reduces the operating current SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source The clock source used will be from one of the low speed oscillators either the LXT or the LIRC Running the microcontroller in this mode allows it to run with much lower oper...

Page 59: ... 1 Bit 7 5 CKS2 CKS0 The system clock selection when HLCLK is 0 000 fSUB fLXT or fLIRC 001 fSUB fLXT or fLIRC 010 fH 64 011 fH 32 100 fH 16 101 fH 8 110 fH 4 111 fH 2 These three bits are used to select which clock is used as the system clock source In addition to the system clock source the LIRC a divided version of the high speed system oscillator can also be chosen as the system clock source Bi...

Page 60: ...e device will enter the SLEEP Mode when a HALT instruction is executed bit 0 HLCLK System clock selection 0 fH 2 fH 64 or fSUB 1 fH This bit is used to select if the fH clock or the fH 2 fH 64 or fSUB clock is used as the system clock When the bit is high the fH clock will be selected and if low the fH 2 fH 64 or fSUB clock will be selected When system clock switches from the fH clock to the fSUB ...

Page 61: ...he LIRC osrillator respectively to wake up the system from the SLEEP or IDLE0 Mode The Fast Wake up bit FSTEN will have no effect in these cases System Oscillator FSTEN Bit Wake up Time SLEEP0 Mode Wake up Time SLEEP1 Mode Wake up Time IDLE0 Mode Wake up Time IDLE1 Mode HXT 0 1024 HXT cycles 1024 HXT cycles 1 2 HXT cycles 1 1024 HXT cycles 1 2 fSUB cycles System runs with fSUB first for 1024 HXT c...

Page 62: ...ce can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications In simple terms Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2 CKS0 bits in the SMOD register while Mode Switching from the NORMAL SLOW Modes to the SLEEP IDLE Modes is executed via the HALT instruction When a HALT instruct...

Page 63: ...et the HLCLK bit to 0 and set the CKS2 CKS0 bits to 000 or 001 in the SMOD register This will then use the low speed system oscillator which will consume less power Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption The SLOW Mode is sourced from the LXT or the LIRC oscillators and therefore requires these oscillato...

Page 64: ...ack to the NORMAL Mode where the high speed system oscillator is used the HLCLK bit should be set to 1 or HLCLK bit is 0 but CKS2 CKS0 is set to 010 011 100 101 110 or 111 As a certain amount of time will be required for the high frequency clock to stabilise the status of the HTO bit is checked The amount of time required for high speed system oscillator stabilization depends upon which high speed...

Page 65: ...ill occur The system clock will be stopped and the application program will stop at the HALT instruction but the WDT or LVD will remain with the clock source coming from the fSUB clock The Data Memory contents and registers will maintain their present condition The WDT will be cleared and resume counting as the WDT is enabled and its clock source is selected to come from the fSUB clock The I O por...

Page 66: ...le perhaps only in the order of several micro amps except in the IDLE1 Mode there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised Special attention must be made to the I O pins on the device All high impedance input pins must be connected to either a fixed high or low level as any floating input pins could create in...

Page 67: ...t which woke up the device will not be immediately serviced but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free The other situation is where the related interrupt is enabled and the stack is not full in which case the regular interrupt response takes place If an interrupt request flag is set high before entering the SLEEP or IDLE Mode ...

Page 68: ... using the WS2 WS0 bits in the WDTC register Watchdog Timer Control Register A single register WDTC controls the required time out period as well as the enable disable operation This register controls the overall operation of the Watchdog Timer WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R W R W R W R W R W R W R W R W R W POR 0 1 0 1 0 0 1 1 Bit 7 3 WE4 WE0 WDT function...

Page 69: ...og Timer function is determined using a configuration option With regard to the Watchdog Timer enable disable function there are also five bits WE4 WE0 in the WDTC register to offer the additional enable disable control and reset control of the Watchdog Timer If the WDT function configuration option is determined that the WDT function is always enabled the WE4 WE0 bits still have effects on the WD...

Page 70: ...tion Watchdog Timer Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters The most important reset condition is after power is first applied to the microcontroller In this case internal circuitry will ensure that the microcontroller after a short delay will be in ...

Page 71: ...eset function may be incapable of providing proper reset operation For this reason it is recommended that an external RC network is connected to the RES pin whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise During this time delay normal operation of the will be inhibited After the RES line reaches a certain voltage va...

Page 72: ...g the battery the LVR will automatically reset the device internally and the LVRF bit in the SMOD1 register will also be set to 1 For a valid LVR signal a low supply voltage i e a voltage in the range between 0 9V VLVR must exist for a time greater than that specified by tLVR in the A C characteristics If the low supply voltage state does not exceed this value the LVR will ignore the low supply vo...

Page 73: ...the register contents will be reset to the POR value SMOD1 Register Bit 7 6 5 4 3 2 1 0 Name FSYSON LVRF LRF WRF R W R W R W R W R W POR 0 x 0 0 x unknown Bit 7 FSYSON fSYS Control in IDLE Mode Described elsewhere Bit 6 3 Unimplemented read as 0 Bit 2 LVRF LVR function reset flag 0 Not occurred 1 Occurred This bit is set to 1 when a specific Low Voltage Reset situation condition occurs This bit ca...

Page 74: ... or Watchdog Timer The reset flags are shown in the table TO PDF RESET Conditions 0 0 Power on reset u u RES or LVR reset during NORMAL or SLOW Mode operation 1 u WDT time out reset during NORMAL or SLOW Mode operation 1 1 WDT time out reset during IDLE or SLEEP Mode operation u stands for unchanged The following table indicates the way in which the various components of the microcontroller are af...

Page 75: ...VDC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u INTEG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 u u u u u u u u TBC 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 u u u u u u u u INTC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u INTC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u SMOD1 0 x 0 0 0 1 u u 0 u u u u u u u LVRC 0 ...

Page 76: ...1 u u u u u u u u PHPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PH 1111 1111 1111 1111 1111 1111 u u u u u u u u PHC 1111 1111 1111 1111 1111 1111 u u u u u u u u PAFS 0 0 0 0 0 0 0 0 0 0 0 0 u u u u PBFS 0 0 0 0 0 0 0 0 0 0 0 0 u u u u PCFS 0 0 0 0 0 0 0 0 0 u u u PDFS 1111 1111 1111 1111 1111 1111 u u u u u u u u PEFS 1111 1111 1111 1111 1111 1111 u u u u u u u u PFFS 1111...

Page 77: ... 0 u u u u u u u u TM1AH 0 0 0 0 0 0 u u TM1BL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TM1BH 0 0 0 0 0 0 u u TM2C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TM2C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TM2DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TM2DH 0 0 0 0 0 0 u u TM2AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 78: ... means the inputs must be ready at the T2 rising edge of instruction MOV A m where m denotes the port address For output operation all the data is latched and remains unchanged until the output latch is rewritten I O Port Register List HT69F30A Register Name Bit 7 6 5 4 3 2 1 0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PA PA7 PA6 PA5 ...

Page 79: ...PBC1 PBC0 PCPU PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 PC PC6 PC5 PC4 PC3 PC2 PC1 PC0 PCC PCC6 PCC4 PCC4 PCC3 PCC2 PCC1 PCC0 PDPU PDPU7 PDPU6 PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PDPU0 PD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PDC PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 PEPU PEPU7 PEPU6 PEPU5 PEPU4 PEPU3 PEPU2 PEPU1 PEPU0 PE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PEC PEC7 PEC6 PEC5 PEC4 PEC3 PEC2 PEC1 PEC0 PFPU PFPU...

Page 80: ...C7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 PEPU PEPU7 PEPU6 PEPU5 PEPU4 PEPU3 PEPU2 PEPU1 PEPU0 PE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PEC PEC7 PEC6 PEC5 PEC4 PEC3 PEC2 PEC1 PEC0 PFPU PFPU7 PFPU6 PFPU5 PFPU4 PFPU3 PFPU2 PFPU1 PFPU0 PF PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PFC PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 PGPU PGPU7 PGPU6 PGPU5 PGPU4 PGPU3 PGPU2 PGPU1 PGPU0 PG PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PGC PGC7 P...

Page 81: ...O Port Control Registers Each Port has its own control register known as PAC PHC which controls the input output configuration With this control register each I O pin with or without pull high resistors can be reconfigured dynamically under software control For the I O pin to function as an input the corresponding bit of the control register must be written as a 1 This will then allow the logic st...

Page 82: ... PBFS4 PCFS PCFS2 PCFS1 PCFS0 PDFS PDFS7 PDFS6 PDFS5 PDFS4 PDFS3 PDFS2 PDFS1 PDFS0 PEFS PEFS7 PEFS6 PEFS5 PEFS4 PEFS3 PEFS2 PEFS1 PEFS0 PFFS PFFS7 PFFS6 PFFS5 PFFS4 PFFS3 PFFS2 PFFS1 PFFS0 PGFS PGS7 PFGFS6 PGFS5 PGFS4 PGFS3 PGFS2 PGFS1 PGFS0 SFS SFS7 SFS6 SFS5 SFS4 SFS3 SFS2 SFS1 SFS0 HT69F50A Register Name Bit 7 6 5 4 3 2 1 0 PAFS PAFS6 PAFS5 PAFS3 PAFS1 PBFS PBFS7 PBFS6 PBFS5 PBFS4 PCFS PCFS2 PC...

Page 83: ... Function Selection 0 I O 1 TP1_0 Bit 2 Unimplemented read as 0 Bit 1 PAFS1 Port A 1 Function Selection 0 I O 1 TP0_1 Bit 0 Unimplemented read as 0 PAFS Register HT69F40A HT69F50A Bit 7 6 5 4 3 2 1 0 Name PAFS6 PAFS5 PAFS3 PAFS1 R W R W R W R W R W POR 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 PAFS6 Port A 6 Function Selection 0 I O 1 TP0_0 Bit 5 PAFS5 Port A 5 Function Selection 0 I O 1 TP2_1 B...

Page 84: ...FS6 Port B 6 Function Selection 0 I O 1 TP1B_1 Bit 5 PBFS5 Port B 5 Function Selection 0 I O 1 TP1B_0 Bit 4 PBFS4 Port B 4 Function Selection 0 I O 1 TP1A Bit 3 0 Unimplemented read as 0 PCFS Register HT69F30A HT69F40A HT69F50A Bit 7 6 5 4 3 2 1 0 Name PCFS2 PCFS1 PCFS0 R W R W R W R W POR 0 0 0 Bit 7 3 Unimplemented read as 0 Bit 2 PCFS2 Port C 2 Function Selection 0 I O 1 C2 Bit 1 PCFS1 Port C 1...

Page 85: ... 1 1 1 1 1 1 1 1 Bit 7 PDFS7 Port D 7 Function Selection 0 I O 1 SEG7 Bit 6 PDFS6 Port D 6 Function Selection 0 I O 1 SEG6 Bit 5 PDFS5 Port D 5 Function Selection 0 I O 1 SEG5 Bit 4 PDFS4 Port D 4 Function Selection 0 I O 1 SEG4 Bit 3 PDFS3 Port D 3 Function Selection 0 I O 1 SEG3 Bit 2 PDFS2 Port D 2 Function Selection 0 I O 1 SEG2 Bit 1 PDFS1 Port D 1 Function Selection 0 I O 1 SEG1 Bit 0 PDFS0 ...

Page 86: ...1 Bit 7 PDFS7 Port D 7 Function Selection 0 I O 1 SEG7 or TP1B_2 Bit 6 PDFS6 Port D 6 Function Selection 0 I O 1 SEG6 or TP1B_1 Bit 5 PDFS5 Port D 5 Function Selection 0 I O 1 SEG5 or TP1B_0 Bit 4 PDFS4 Port D 4 Function Selection 0 I O 1 SEG4 or TP1A Bit 3 PDFS3 Port D 3 Function Selection 0 I O 1 SEG3 Bit 2 PDFS2 Port D 2 Function Selection 0 I O 1 SEG2 Bit 1 PDFS1 Port D 1 Function Selection 0 ...

Page 87: ... W POR 1 1 1 1 1 1 1 1 Bit 7 PEFS7 Port E 7 Function Selection 0 I O 1 SEG15 Bit 6 PEFS6 Port E 6 Function Selection 0 I O 1 SEG14 Bit 5 PEFS5 Port E 5 Function Selection 0 I O 1 SEG13 Bit 4 PEFS4 Port E 4 Function Selection 0 I O 1 SEG12 Bit 3 PEFS3 Port E 3 Function Selection 0 I O 1 SEG11 Bit 2 PEFS2 Port E 2 Function Selection 0 I O 1 SEG10 Bit 1 PEFS1 Port E 1 Function Selection 0 I O 1 SEG9 ...

Page 88: ...W POR 1 1 1 1 1 1 1 1 Bit 7 PFFS7 Port F 7 Function Selection 0 I O 1 SEG23 Bit 6 PFFS6 Port F 6 Function Selection 0 I O 1 SEG22 Bit 5 PFFS5 Port F 5 Function Selection 0 I O 1 SEG21 Bit 4 PFFS4 Port F 4 Function Selection 0 I O 1 SEG20 Bit 3 PFFS3 Port F 3 Function Selection 0 I O 1 SEG19 Bit 2 PFFS2 Port F 2 Function Selection 0 I O 1 SEG18 Bit 1 PFFS1 Port F 1 Function Selection 0 I O 1 SEG17 ...

Page 89: ... 1 1 1 1 1 1 1 1 Bit 7 PGFS7 Port G 7 Function Selection 0 I O 1 SEG31 Bit 6 PGFS6 Port G 6 Function Selection 0 I O 1 SEG30 Bit 5 PGFS5 Port G 5 Function Selection 0 I O 1 SEG29 Bit 4 PGFS4 Port G 4 Function Selection 0 I O 1 SEG28 Bit 3 PGFS3 Port G 3 Function Selection 0 I O 1 SEG27 Bit 2 PGFS2 Port G 2 Function Selection 0 I O 1 SEG26 Bit 1 PGFS1 Port G 1 Function Selection 0 I O 1 SEG25 Bit 0...

Page 90: ...unction Selection 0 I O 1 SEG37 Bit 4 PHFS4 Port H 4 Function Selection 0 I O 1 SEG36 Bit 3 PHFS3 Port H 3 Function Selection 0 I O 1 SEG35 Bit 2 PHFS2 Port H 2 Function Selection 0 I O 1 SEG34 Bit 1 PHFS1 Port H 1 Function Selection 0 I O 1 SEG33 Bit 0 PHFS0 Port H 0 Function Selection 0 I O 1 SEG32 SFS Register HT69F30A Bit 7 6 5 4 3 2 1 0 Name SFS6 SFS5 SFS4 R W R W R W R W POR 0 0 0 Bit 7 Unim...

Page 91: ...R W POR 0 0 0 0 0 0 0 0 Bit 7 SFS7 TCK2 Source Selection 0 PA2 1 PD2 Bit 6 SFS6 TCK1 Source Selection 0 PA0 1 PD3 Bit 5 SFS5 TCK0 Source Selection 0 PA2 1 PD1 Bit 4 SFS4 INT1 Source Selection 0 PA0 1 PD0 Bit 3 SFS3 PD7 Special Function Selection 0 SEG7 1 TP1B_2 Bit 2 SFS2 PD6 Special Function Selection 0 SEG6 1 TP1B_1 Bit 1 SFS1 PD5 Special Function Selection 0 SEG5 1 TP1B_0 Bit 0 SFS0 PD4 Special...

Page 92: ...e port control registers are then programmed to setup some pins as outputs these output pins will have an initial high output value unless the associated port data registers are first programmed Selecting which pins are inputs and which are outputs can be achieved byte wide by loading the correct values into the appropriate port control register or by programming individual bits in the port contro...

Page 93: ...ndard and Enhanced TMs will be described in this section the detailed operation regarding each of the TM types will be described in separate sections The main features and differences between the three types of TMs are summarised in the accompanying table TM Function CTM STM ETM Timer Counter I P Capture Compare Match Output PWM Channels 1 1 2 Single Pulse Output 1 2 PWM Alignment Edge Edge Edge C...

Page 94: ... source for the TM and is selected using the TnCK2 TnCK0 bits in the TMnC0 register This external TM input pin allows an external clock source to drive the internal TM This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2 TnCK0 bits The TM input pin can be chosen to have either a rising or falling active edge The TMs each hav...

Page 95: ...A Register Name Bit 7 6 5 4 3 2 1 0 PAFS PAFS6 PAFS5 PAFS3 PAFS1 SFS SFS6 SFS5 SFS4 HT69F40A HT69F50A Register Name Bit 7 6 5 4 3 2 1 0 PAFS PAFS6 PAFS5 PAFS3 PAFS1 PBFS PBFS7 PBFS6 PBFS5 PBFS4 PDFS PDFS7 PDFS6 PDFS5 PDFS4 PDFS3 PDFS2 PDFS1 PDFS0 SFS SFS7 SFS6 SFS5 SFS4 SFS3 SFS2 SFS1 SFS0 PAFS Register HT69F30A Bit 7 6 5 4 3 2 1 0 Name PAFS6 PAFS5 PAFS3 PAFS1 R W R W R W R W R W POR 0 0 0 0 Bit 7...

Page 96: ...t 4 Unimplemented read as 0 Bit 3 PAFS3 Port A 3 Function Selection 0 I O 1 TP2_0 Bit 2 Unimplemented read as 0 Bit 1 PAFS1 Port A 1 Function Selection 0 I O 1 TP0_1 Bit 0 Unimplemented read as 0 PBFS Register HT69F40A HT69F50A Bit 7 6 5 4 3 2 1 0 Name PBFS7 PBFS6 PBFS5 PBFS4 R W R W R W R W R W POR 0 0 0 0 Bit 7 PBFS7 Port B 7 Function Selection 0 I O 1 TP1B_2 Bit 6 PBFS6 Port B 6 Function Select...

Page 97: ...6 Port D 6 Function Selection 0 I O 1 SEG6 or TP1B_1 Bit 5 PDFS5 Port D 5 Function Selection 0 I O 1 SEG5 or TP1B_0 Bit 4 PDFS4 Port D 4 Function Selection 0 I O 1 SEG4 or TP1A Bit 3 0 PDFS3 PDFS0 Port D 3 0 Function Selection Described elsewhere SFS Register HT69F30A Bit 7 6 5 4 3 2 1 0 Name SFS6 SFS5 SFS4 R W R W R W R W POR 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 SFS6 TCK1 Source Selection 0 ...

Page 98: ...POR 0 0 0 0 0 0 0 0 Bit 7 SFS7 TCK2 Source Selection 0 PA2 1 PD2 Bit 6 SFS6 TCK1 Source Selection 0 PA0 1 PD3 Bit 5 SFS5 TCK0 Source Selection 0 PA2 1 PD1 Bit 4 SFS4 INT1 Source Selection Described elsewhere Bit 3 SFS3 PD7 Special Function Selection 0 SEG7 1 TP1B_2 Bit 2 SFS2 PD6 Special Function Selection 0 SEG6 1 TP1B_1 Bit 1 SFS1 PD5 Special Function Selection 0 SEG5 1 TP1B_0 Bit 0 SFS0 PD4 Spe...

Page 99: ... PD1 TCK0 PA6 PA1 0 1 0 1 PAFS6 PAFS3 PA1 PA6 Output TCK0 Input CTM Function Pin Control Block Diagram HT69F30A HT69F40A HT69F50A TMn STM 0 1 0 1 PA3 TPn_0 PA5 TPn_1 PA2 or PD2 TCKn PA3 PA5 0 1 0 1 PAFS3 PAFS5 PA5 PA3 PAFS3 PAFS5 Capture Input TCKn Input Output 0 0 1 0 1 0 STM Function Pin Control Block Diagram HT69F30A n 1 HT69F40A HT69F50A n 2 ...

Page 100: ...ture Input CCRA Output PB4 or PD4 TP1A PBFS4 PDFS4 1 0 PBFS4 PDFS4 PB5 PD5 PB5 PD5 PBFS5 PDFS5 PB6 PD6 PB6 PD6 PBFS6 PDFS6 PB7 PD7 PB7 PD7 PBFS7 PDFS7 PBFS7 PDFS7 PBFS6 PDFS6 PBFS5 PDFS5 PB6 or PD6 TP1B_1 PB7 or PD7 TP1B_2 ETM Function Pin Control Block Diagram HT69F40A HT69F50A Note The I O register data bits shown are used for TM output inversion control In the Capture Input Mode the TM pin cont...

Page 101: ...cess the CCRA and CCRB low byte registers named TMxAL and TMxBL using the following access procedures Accessing the CCRA or CCRB low byte registers without following these access procedures will result in unpredictable values Data Bus it Buffe TMxDH TMxDL TMxBH TMxBL TMxAH TMxAL TM Counte Registe Read only TM CCRA Registe Read W ite TM CCRB Registe Read W ite The following steps show the read and ...

Page 102: ...source There are also two internal comparators with the names Comparator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits The only way of changing the value of the 10 bit cou...

Page 103: ...D7 D6 D5 D4 D3 D2 D1 D0 TMnDH D9 D8 TMnAL D7 D6 D5 D4 D3 D2 D1 D0 TMnAH D9 D8 Compact TM Register List n 0 TMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 0 TMnDL TMn Counter Low Byte Register bit 7 bit 0 TMn 10 bit Counter bit 7 bit 0 TMnDH Register Bit 7 6 5 4 3 2 1 0 Name D9 D8 R W R R POR 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 ...

Page 104: ...e used to select the clock source for the TM Selecting the Reserved clock input will effectively disable the internal counter The external pin clock source can be chosen to be active on the rising or falling edge The clock source fSYS is the system clock while fH and fSUB are other internal clocks the details of which can be found in the oscillator section Bit 3 TnON TMn Counter On Off Control 0 O...

Page 105: ...e multiples Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value TMnC1 Register Bit 7 6 5 4 3 2 1 0 Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 TnM1 TnM0 Select TMn Operating Mode 00 Compare Match Output Mode 01 Undefined 10 PWM Mode 11 Timer Counter Mode These bits setup the requir...

Page 106: ...WM Mode 0 Active low 1 Active high This is the output control bit for the TM output pin Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode It has no effect if the TM is in the Timer Counter Mode In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs In the PWM Mode it determines if the P...

Page 107: ...m Comparator A However here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when TnCCLR is high no TnPF interrupt request flag will be generated If the CCRA bits are all zero the counter will overflow when its reaches its maximum 10 bit 3FF Hex value however here the TnAF interrupt request flag will not be ...

Page 108: ...itial Level Low if Tn C 0 utput Toggle with TnAF flag Note TnI 1 0 10 A tive High utput sele t He e TnI 1 0 11 Toggle utput sele t utput not affe ted y TnAF flag Remains High until eset y Tn N it utput Pin Reset to Initial value utput ont olled y othe pin sha ed fun tion utput Inve ts when TnP L is high Compare Match Output Mode TnCCLR 0 Note 1 With TnCCLR 0 a Comparator P match will clear the cou...

Page 109: ...1 0 10 A tive High utput sele t He e TnI 1 0 11 Toggle utput sele t utput not affe ted y TnAF flag Remains High until eset y Tn N it utput Pin Reset to Initial value utput ont olled y othe pin sha ed fun tion utput Inve ts when TnP L is high TnPF not gene ated No TnAF flag gene ated on CCRA ove flow utput does not hange Compare Match Output Mode TnCCLR 1 Note 1 With TnCCLR 1 a Comparator A match w...

Page 110: ...erate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP re...

Page 111: ...f Tn N it low Counte Reset when Tn N etu ns high TnDPX 0 TnM 1 0 10 PWM Duty Cy le set y CCRA PWM esumes ope ation utput ont olled y othe pin sha ed fun tion utput Inve ts when TnP L 1 PWM Pe iod set y CCRP TM P Pin Tn C 0 PWM Mode TnDPX 0 Note 1 Here TnDPX 0 Counter cleared by CCRP 2 A counter clear sets the PWM Period 3 The internal PWM function continues running even when TnIO 1 0 00 or 01 4 Th...

Page 112: ...f Tn N it low Counte Reset when Tn N etu ns high TnDPX 1 TnM 1 0 10 PWM Duty Cy le set y CCRP PWM esumes ope ation utput ont olled y othe pin sha ed fun tion utput Inve ts when TnP L 1 PWM Pe iod set y CCRA TM P Pin Tn C 0 PWM Mode TnDPX 1 Note 1 Here TnDPX 1 Counter cleared by CCRA 2 A counter clear sets the PWM Period 3 The internal PWM function continues running even when TnIO 1 0 00 or 01 4 Th...

Page 113: ...so two internal comparators with the names Comparator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP comparator is 3 or 8 bits wide whose value is compared the with highest 3 or 8 bits in the counter while the CCRA is the ten or sixteen bits and therefore compares all counter bits The only way of changing the value of the 10 or 16 b...

Page 114: ...T1RP2 T1RP1 T1RP0 TM1C1 T1M1 T1M0 T1IO1 T1IO0 T1OC T1POL T1DPX T1CCLR TM1DL D7 D6 D5 D4 D3 D2 D1 D0 TM1DH D9 D8 TM1AL D7 D6 D5 D4 D3 D2 D1 D0 TM1AH D9 D8 10 bit Standard TM Register List HT69F30A Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TM2C0 T2PAU T2CK2 T2CK1 T2CK0 T2ON T2RP2 T2RP1 T2RP0 TM2C1 T2M1 T2M0 T2IO1 T2IO0 T2OC T2POL T2DPX T2CCLR TM2DL D7 D6 D5 D4 D3 D2 D1 D0 TM2DH D9 D8 TM2A...

Page 115: ...his bit controls the overall on off function of the TM Setting the bit high enables the counter to run clearing the bit disables the TM Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption When the bit changes state from low to high the internal counter value will be reset to zero however when the bit changes from high to low the...

Page 116: ...etermine how the TM output pin changes state when a certain condition is reached The function that these bits select depends upon in which mode the TM is running In the Compare Match Output Mode the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A The TM output pin can be setup to switch high switch low or to toggle its present st...

Page 117: ...igh the TM output pin will be inverted and not inverted when the bit is zero It has no effect if the TM is in the Timer Counter Mode Bit 1 TnDPX TMn PWM period duty Control 0 CCRP period CCRA duty 1 CCRP duty CCRA period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform Bit 0 TnCCLR Select TMn Counter clear condition 0 TMn Comparator ...

Page 118: ...0 Name D9 D8 R W R R POR 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 TMnDH TMn Counter High Byte Register bit 1 bit 0 TMn 10 bit Counter bit 9 bit 8 TMnAL Register 10 bit STM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 TMnAL TMn CCRA Low Byte Register bit 7 bit 0 TMn 10 bit CCRA bit 7 bit 0 TMnAH Register 10 bit STM Bit 7 6 5 4 3...

Page 119: ...source for the TM2 Selecting the Reserved clock input will effectively disable the internal counter The external pin clock source can be chosen to be active on the rising or falling edge The clock source fSYS is the system clock while fH and fSUB are other internal clocks the details of which can be found in the oscillator section Bit 3 T2ON TM2 Counter On Off Control 0 Off 1 On This bit controls ...

Page 120: ...etermine how the TM output pin changes state when a certain condition is reached The function that these bits select depends upon in which mode the TM is running In the Compare Match Output Mode the T2IO1 and T2IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A The TM output pin can be setup to switch high switch low or to toggle its present st...

Page 121: ...igh the TM output pin will be inverted and not inverted when the bit is zero It has no effect if the TM is in the Timer Counter Mode Bit 1 T2DPX TM2 PWM period duty Control 0 CCRP period CCRA duty 1 CCRP duty CCRA period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform Bit 0 T2CCLR Select TM2 Counter clear condition 0 TM2 Comparator ...

Page 122: ...R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 TM2AH TM2 CCRA High Byte Register bit 7 bit 0 TM2 16 bit CCRA bit 15 bit 8 TM2RP Register 16 bit STM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 TM2RP TM2 CCRP Register bit 7 bit 0 TM2 CCRP 8 bit register compared with the TM2 Counter bit 15 bit 8 Comparator P Match Period 0 65536 TM2 c...

Page 123: ... is high then the counter will be cleared when a compare match occurs from Comparator A However here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when TnCCLR is high no TnPF interrupt request flag will be generated In the Compare Match Output Mode the CCRA can not be set to 0 As the name of the mode sugg...

Page 124: ...TnI 1 TnI 0 10 A tive High utput Sele t utput not affe ted y TnAF flag Remains High until eset y Tn N it TnCCLR 0 TnM 1 0 00 TnPAU it Resume Stop Time CCRP 0 CCRP 0 TnP L it utput Pin Reset to initial value utput inve ts when TnP L is high utput ont olled y othe pin sha ed fun tion Counte Value Compare Match Output Mode TnCCLR 0 Note 1 With TnCCLR 0 a Comparator P match will clear the counter 2 Th...

Page 125: ... High utput Sele t TnPAU it Resume Stop Time TnPF not gene ated No TnAF flag gene ated on CCRA ove flow utput does not hange CCRA 0 utput inve ts when TnP L is high TnP L it TnCCLR 1 TnM 1 0 00 utput ont olled y othe pin sha ed fun tion utput not affe ted y TnAF flag emains High until eset y Tn N it Counte Value Compare Match Output Mode TnCCLR 1 Note 1 With TnCCLR 1 a Comparator A match will clea...

Page 126: ...ency but of varying duty cycle on the TM output pin a square wave AC waveform can be generated with varying equivalent DC RMS values As both the period and duty cycle of the PWM waveform can be controlled the choice of generated waveform is extremely flexible In the PWM mode the TnCCLR bit has no effect as the PWM period Both of the CCRA and CCRP registers are used to generate the PWM waveform one...

Page 127: ... 256 384 512 640 768 896 1024 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value 16 bit STM PWM Mode Edge aligned Mode TnDPX 0 CCRP 1 255 000b Period CCRP 256 65536 Duty CCRA If fSYS 16MHz TM clock source select fSYS 4 CCRP 2 and CCRA 128 The STM PWM output frequency fSYS 4 2 256 fSYS 2048 7 8125k...

Page 128: ... Reset when Tn N etu ns high TnDPX 0 TnM 1 0 10 PWM Duty Cy le set y CCRA PWM esumes ope ation utput ont olled y othe pin sha ed fun tion utput Inve ts when TnP L 1 PWM Pe iod set y CCRP TM P Pin Tn C 0 PWM Mode TnDPX 0 Note 1 Here TnDPX 0 Counter cleared by CCRP 2 A counter clear sets the PWM Period 3 The internal PWM function continues running even when TnIO 1 0 00 or 01 4 The TnCCLR bit has no ...

Page 129: ... Reset when Tn N etu ns high TnDPX 1 TnM 1 0 10 PWM Duty Cy le set y CCRP PWM esumes ope ation utput ont olled y othe pin sha ed fun tion utput Inve ts when TnP L 1 PWM Pe iod set y CCRA TM P Pin Tn C 0 PWM Mode TnDPX 1 Note 1 Here TnDPX 1 Counter cleared by CCRA 2 A counter clear sets the PWM Period 3 The internal PWM function continues running even when TnIO 1 0 00 or 01 4 The TnCCLR bit has no ...

Page 130: ...e Pulse output When the TnON bit transitions to a high level the counter will start running and the pulse leading edge will be generated The TnON bit should remain high when the pulse is in its active state The generated pulse trailing edge will be generated when the TnON bit is cleared to zero which can be implemented using the application program or when a compare match occurs from Comparator A ...

Page 131: ...A utput Inve ts when TnP L 1 No CCRP Inte upts gene ated TM P Pin Tn C 0 TCKn pin Softwa e T igge Clea ed y CCRA mat h TCKn pin T igge Auto set y TCKn pin Softwa e T igge Softwa e Clea Softwa e T igge Softwa e T igge Single Pulse Mode Note 1 Counter stopped by CCRA 2 CCRP is not used 3 The pulse triggered by the TCKn pin or by setting the TnON bit high 4 A TCKn pin active edge will automatically s...

Page 132: ...tive of what events occur on the TPn_0 or TPn_1 pin the counter will continue to free run until the TnON bit changes from high to low When a CCRP compare match occurs the counter will reset back to zero in this way the CCRP value can be used to control the maximum counter value When a CCRP compare match occurs from Comparator P a TM interrupt will also be generated Counting the number of overflow ...

Page 133: ...alue XX YY XX YY A tive edge A tive edge A tive edge 00 Rising edge 01 Falling edge 10 Both edges 11 Disa le Captu e Capture Input Mode Note 1 TnM 1 0 01 and active edge set by the TnIO 1 0 bits 2 A TM Capture input pin active edge transfers the counter value to CCRA 3 TnCCLR bit not used 4 No output function TnOC and TnPOL bits are not used 5 CCRP determines the counter value and the counter has ...

Page 134: ...r B and Comparator P These comparators will compare the value in the counter with the CCRA CCRB and CCRP registers The CCRP comparator is 3 bits wide whose value is compared with the highest 3 bits in the counter while CCRA and CCRB are 10 bits wide and therefore compared with all counter bits The only way of changing the value of the 10 bit counter using the application program is to clear the co...

Page 135: ...TM1C0 Register 10 bit ETM Bit 7 6 5 4 3 2 1 0 Name T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 T1PAU TM1 Counter Pause Control 0 Run 1 Pause The counter can be paused by setting this bit high Clearing the bit to zero restores normal counter operation When in a Pause condition the TM will remain powered up and continue to consume powe...

Page 136: ...dition as specified by the T1OC bit when the T1ON bit changes from low to high Bit 2 0 T1RP2 T1RP0 TM1 CCRP 3 bit register compared with the TM1 Counter bit 9 bit 7 Comparator P Match Period 000 1024 TM1 clocks 001 128 TM1 clocks 010 256 TM1 clocks 011 384 TM1 clocks 100 512 TM1 clocks 101 640 TM1 clocks 110 768 TM1 clocks 111 896 TM1 clocks These three bits are used to setup the value on the inte...

Page 137: ...ow the TM output pin changes state when a certain condition is reached The function that these bits select depends upon in which mode the TM is running In the Compare Match Output Mode the T1AIO1 and T1AIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A The TM output pin can be setup to switch high switch low or to toggle its present state when...

Page 138: ...e TP1A output pin When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero It has no effect if the TM is in the Timer Counter Mode Bit 1 T1CDN TM1 Counter count up or down flag 0 Count up 1 Count down Bit 0 T1CCLR Select TM1 Counter clear condition 0 TM1 Comparator P match 1 TM1 Comparator A match This bit is used to select the method which clears the count...

Page 139: ...wo bits are used to determine how the TM output pin changes state when a certain condition is reached The function that these bits select depends upon in which mode the TM is running In the Compare Match Output Mode the T1BIO1 and T1BIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A The TM output pin can be setup to switch high switch low or t...

Page 140: ...low Bit 2 T1BPOL TP1B_0 TP1B_1 TB1B_2 Output polarity Control 0 Non invert 1 Invert This bit controls the polarity of the TP1B_0 TP1B_1 TP1B_2 output pin When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero It has no effect if the TM is in the Timer Counter Mode Bit 1 0 T1PWM1 T1PWM0 Select PWM Mode 00 Edge aligned 01 Centre aligned compare match on cou...

Page 141: ...3 2 1 0 Name D9 D8 R W R W R W POR 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 TM1AH TM1 CCRA High Byte Register bit 1 bit 0 TM1 10 bit CCRA bit 9 bit 8 TM1BL Register 10 bit ETM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 TM1BL TM1 CCRB Low Byte Register bit 7 bit 0 TM1 10 bit CCRB bit 7 bit 0 TM1BH Register 10 bit ETM Bit 7 6 5...

Page 142: ...respectively will both be generated If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A However here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when TnCCLR is high no TnPF interrupt request flag will be generated As the name of ...

Page 143: ...if TnA C 0 utput Toggle with TnAF flag Note TnAI 1 0 10 A tive High utput sele t He e TnAI 1 0 11 Toggle utput sele t utput not affe ted y TnAF flag Remains High until eset y Tn N it utput Pin Reset to Initial value utput ont olled y othe pin sha ed fun tion utput Inve ts when TnAP L is high ETM CCRA Compare Match Output Mode TnCCLR 0 Note 1 With TnCCLR 0 a Comparator P match will clear the counte...

Page 144: ...if TnB C 0 utput Toggle with TnBF flag Note TnBI 1 0 10 A tive High utput sele t He e TnBI 1 0 11 Toggle utput sele t utput not affe ted y TnBF flag Remains High until eset y Tn N it utput Pin Reset to Initial value utput ont olled y othe pin sha ed fun tion utput Inve ts when TnBP L is high ETM CCRB Compare Match Output Mode TnCCLR 0 Note 1 With TnCCLR 0 a Comparator P match will clear the counte...

Page 145: ...h utput sele t He e TnAI 1 0 11 Toggle utput sele t utput not affe ted y TnAF flag Remains High until eset y Tn N it utput Pin Reset to Initial value utput ont olled y othe pin sha ed fun tion utput Inve ts when TnAP L is high TnPF not gene ated No TnAF flag gene ated on CCRA ove flow utput does not hange ETM CCRA Compare Match Output Mode TnCCLR 1 Note 1 With TnCCLR 1 a Comparator A match will cl...

Page 146: ...BI 1 0 10 A tive High utput sele t He e TnBI 1 0 11 Toggle utput sele t utput not affe ted y TnBF flag Remains High until eset y Tn N it utput Pin Reset to Initial value utput ont olled y othe pin sha ed fun tion utput Inve ts when TnBP L is high No TnAF flag gene ated on CCRA ove flow ETM CCRB Compare Match Output Mode TnCCLR 1 Note 1 With TnCCLR 1 a Comparator A match will clear the counter 2 Th...

Page 147: ...h way the PWM period is controlled With the TnCCLR bit set high the PWM period can be finely controlled using the CCRA registers In this case the CCRB registers are used to set the PWM duty value for TPnB_x output pins The CCRP bits are not used and TPnA output pin is not used The PWM output can only be generated on the TPnB_x output pins With the TnCCLR bit cleared to zero the PWM period is set u...

Page 148: ...B_x PWM output frequency fSYS 4 512 fSYS 2048 5 8594kHz duty 256 512 50 If the Duty value defined by CCRA or CCRB register is equal to or greater than the Period value then the PWM output duty is 100 ETM PWM Mode Edge aligned Mode TnCCLR 1 CCRA 1 2 3 511 512 1021 1022 1023 Period 1 2 3 511 512 1021 1022 1023 B Duty CCRB ETM PWM Mode Center aligned Mode TnCCLR 0 CCRA 001b 010b 011b 100b 101b 110b 1...

Page 149: ...utput ont olled y othe pin sha ed fun tion utput Inve ts when TnAP L is high CCRB CCRP Int Flag TnPF TPnB Pin TnB C 1 TPnB Pin TnB C 0 Duty Cy le set y CCRA Duty Cy le set y CCRB PWM Pe iod set y CCRP Duty Cy le set y CCRA Duty Cy le set y CCRA ETM PWM Mode Edge Aligned Note 1 Here TnCCLR 0 therefore CCRP clears the counter and determines the PWM period 2 The internal PWM function continues runnin...

Page 150: ... fun tion utput Inve ts when TnBP L is high CCRB CCRP Int Flag TnPF TPnB Pin TnB C 1 TPnB Pin TnB C 0 Duty Cy le set y CCRB PWM Pe iod set y CCRA ETM PWM Mode Edge Aligned Note 1 Here TnCCLR 1 therefore CCRA clears the counter and determines the PWM period 2 The internal PWM function continues running even when TnBIO 1 0 00 or 01 3 The CCRA controls the TPnB PWM period and CCRB controls the TPnB P...

Page 151: ...n TnAP L is high CCRB CCRP Int Flag TnPF TPnB Pin TnB C 1 TPnB Pin TnB C 0 Duty Cy le set y CCRA Duty Cy le set y CCRB PWM Pe iod set y CCRP ETM PWM Mode Centre Aligned Note 1 Here TnCCLR 0 therefore CCRP clears the counter and determines the PWM period 2 TnPWM 1 0 11 therefore the PWM is centre aligned 3 The internal PWM function continues running even when TnAIO 1 0 or TnBIO 1 0 00 or 01 4 CCRA ...

Page 152: ... C 1 TPnB Pin TnB C 0 Duty Cy le set y CCRB PWM Pe iod set y CCRA utput Inve ts when TnBP L is high CCRP Int Flag TnPF ETM PWM Mode Centre Aligned Note 1 Here TnCCLR 1 therefore CCRA clears the counter and determines the PWM period 2 TnPWM 1 0 11 therefore the PWM is centre aligned 3 The internal PWM function continues running even when TnBIO 1 0 00 or 01 4 CCRA controls the TPnB PWM period and CC...

Page 153: ...TnON bit should remain high when the pulse is in its active state The generated pulse trailing edge of TPnA and TPnB_x will be generated when the TnON bit is cleared to zero which can be implemented using the application program or when a compare match occurs from Comparator A However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse ou...

Page 154: ...en TnBP L 1 TCKn pin Softwa e T igge Clea ed y CCRA mat h TCKn pin T igge Auto set y TCKn pin Softwa e T igge Softwa e Clea Softwa e T igge Softwa e T igge TnBP L TPnA Pin TnA C 0 TPnB Pin TnB C 1 TPnB Pin TnB C 0 Pulse Width set y CCRA utput Inve ts when TnAP L 1 ETM Single Pulse Mode Note 1 Counter stopped by CCRA 2 CCRP is not used 3 The pulse triggered by the TCKn pin or by setting the TnON bi...

Page 155: ... events occur on the TPnA and TPnB_0 TPnB_1 TPnB_2 pins the counter will continue to free run until the TnON bit changes from high to low When a CCRP compare match occurs the counter will reset back to zero in this way the CCRP value can be used to control the maximum counter value When a CCRP compare match occurs from Comparator P a TM interrupt will also be generated Counting the number of overf...

Page 156: ... 0 Value XX YY XX YY A tive edge A tive edge A tive edge 00 Rising edge 01 Falling edge 10 Both edges 11 Disa le Captu e ETM CCRA Capture Input Mode Note 1 TnAM 1 0 01 and active edge set by the TnAIO 1 0 bits 2 The TM Capture input pin active edge transfers the counter value to CCRA 3 TnCCLR bit not used 4 No output function TnAOC and TnAPOL bits not used 5 CCRP determines the counter value and t...

Page 157: ...lling edge 11 Disa le Captu e A tive edge A tive edge XX 10 Both edges A tive edges YY TnBM1 TnBM0 01 Time Counte Value ETM CCRB Capture Input Mode Note 1 TnBM 1 0 01 and active edge set by the TnBIO 1 0 bits 2 The TM Capture input pin active edge transfers the counter value to CCRB 3 TnCCLR bit not used 4 No output function TnBOC and TnBPOL bits not used 5 CCRP determines the counter value and th...

Page 158: ...by the application program is controlled by a series of registers located in the Special Purpose Data Memory as shown in the accompanying table The number of registers depends upon the device chosen but fall into three categories The first is the INTC0 INTC1 registers which setup the primary interrupts the second is the MFI0 MFI2 registers which setup the Multi function interrupts Finally there is...

Page 159: ...EG INT1S1 INT1S0 INT0S1 INT0S0 INTC0 TB0F INT1F INT0F TB0E INT1E INT0E EMI INTC1 MF2F MF1F MF0F TB1F MF2E MF1E MF0E TB1E MFI0 T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PE MFI1 T1BF T1AF T1PF T1BE T1AE T1PE MFI2 DEF LVF DEE LVE INTEG Register Bit 7 6 5 4 3 2 1 0 Name INT1S1 INT1S0 INT0S1 INT0S0 R W R W R W R W R W POR 0 0 0 0 Bit 7 4 Unimplemented read as 0 Bit 3 2 INT1S1 INT1S0 interrupt edge control f...

Page 160: ...ead as 0 Bit 6 TB0F Time Base 0 interrupt request flag 0 No request 1 Interrupt request Bit 5 INT1F INT1 interrupt request flag 0 No request 1 Interrupt request Bit 4 INT0F INT0 interrupt request flag 0 No request 1 Interrupt request Bit 3 TB0E Time Base 0 interrupt control 0 Disable 1 Enable Bit 2 INT1E INT1 interrupt control 0 Disable 1 Enable Bit 1 INT0E INT0 interrupt control 0 Disable 1 Enabl...

Page 161: ...terrupt request Bit 3 MF2E Multi function interrupt 2 control 0 Disable 1 Enable Bit 2 MF1E Multi function interrupt 1 control 0 Disable 1 Enable Bit 1 MF0E Multi function interrupt 0 control 0 Disable 1 Enable Bit 0 TB1E Time Base 1 interrupt control 0 Disable 1 Enable MFI0 Register HT69F30A Bit 7 6 5 4 3 2 1 0 Name T0AF T0PF T0AE T0PE R W R W R W R W R W POR 0 0 0 0 Bit 7 6 Unimplemented read as...

Page 162: ...uest 1 Interrupt request Bit 3 T2AE TM2 Comparator A match interrupt control 0 Disable 1 Enable Bit 2 T2PE TM2 Comparator P match interrupt control 0 Disable 1 Enable Bit 1 T0AE TM0 Comparator A match interrupt control 0 Disable 1 Enable Bit 0 T0PE TM0 Comparator P match interrupt control 0 Disable 1 Enable MFI1 Register HT69F30A Bit 7 6 5 4 3 2 1 0 Name T1AF T1PF T1AE T1PE R W R W R W R W R W POR...

Page 163: ...uest flag 0 No request 1 Interrupt request Bit 3 Unimplemented read as 0 Bit 2 T1BE TM1 Comparator B match interrupt control 0 Disable 1 Enable Bit 1 T1AE TM1 Comparator A match interrupt control 0 Disable 1 Enable Bit 0 T1PE TM1 Comparator P match interrupt control 0 Disable 1 Enable MFI2 Register Bit 7 6 5 4 3 2 1 0 Name DEF LVF DEE LVE R W R W R W R W R W POR 0 0 0 0 Bit 7 6 Unimplemented read ...

Page 164: ... be terminated with a RETI which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred The various interrupt enable bits together with their associated request flags are shown in the accompanying diagrams with their order of priority Some interrupt sources have their own individual ve...

Page 165: ... auto reset in ISR EMI EMI M Funct 2 MF2F MF2E EEPROM DEF DEE EMI Time Base 1 TB1F TB1E EMI EMI Interrupt Structure HT69F30A INT0 Pin INT1 Pin INT0F INT1F INT0E INT1E EMI 04H EMI 08H M Funct 0 MF0F MF0E 0CH 10H 14H Time Base 0 TB0F TB0E 18H LVD LVF LVE 1CH Interrupt Name Request Flags Enable Bits Master Enable Vector EMI auto disabled in ISR Priority High Low TM1 P T1PF T1PE TM1 A T1AF T1AE M Func...

Page 166: ...l remain valid even if the pin is used as an external interrupt input The INTEG register is used to select the type of active edge that will trigger the external interrupt A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt Note that the INTEG register can also be used to disable the external interrupt function Multi function Interrupt Within this...

Page 167: ...nterrupt is to provide an interrupt signal at fixed time periods Its clock source fTB originates from the internal clock source fSUB or fSYS 4 And then passes through a divider the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges The clock source which in turn controls the Time Base interrupt period is...

Page 168: ... stack is not full and a low voltage condition occurs a subroutine call to the Multi function Interrupt vector will take place When the Low Voltage Interrupt is serviced the EMI bit will be automatically cleared to disable other interrupts however only the Multi function interrupt request flag will be also automatically cleared As the LVF flag will not be automatically cleared it has to be cleared...

Page 169: ... the interrupt service routine is executed as only the Multi function interrupt request flags MF0F MF2F will be automatically cleared the individual request flag for the function needs to be cleared by the application program It is recommended that programs do not use the CALL instruction within the interrupt service subroutine Interrupts often occur in an unpredictable manner or need to be servic...

Page 170: ...will be detemined A low voltage condition is indicated when the LVDO bit is set If the LVDO bit is low this indicates that the VDD voltage is above the preset low voltage value The LVDEN bit is used to control the overall on off function of the low voltage detector Setting the bit high will enable the low voltage detector Clearing the bit to zero will switch off the internal low voltage detector c...

Page 171: ...ise and fall rather slowly at the voltage nears that of VLVD there may be multiple bit LVDO transitions LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multi function interrupts providing an alternative means of low voltage detection in addition to polling the LVDO bit The interrupt will only be generated after a delay of tLVD after the LVDO b...

Page 172: ...ea is known as the LCD Memory Any data written here will be automatically read by the internal display driver circuits which will in turn automatically generate the necessary LCD driving signals Therefore any data written into this Memory will be immediately reflected into the actual display connected to the microcontroller As the LCD Memory addresses overlap those of the General Purpose Data Memo...

Page 173: ...T69F30A LCD Memory Map COM0 COM3 COM2 COM1 SEG0 SEG34 SEG33 SEG1 80H A2H A1H 81H SEG35 A3H COM0 COM2 COM1 SEG0 SEG34 SEG33 SEG1 80H A2H A1H 81H SEG36 SEG35 A4H A3H B0 B1 B7 B6 B5 B4 B3 B2 36 SEG x 4 COM B0 B1 B7 B6 B5 B4 B3 B2 37 SEG x 3 COM Unused read as 0 HT69F40A LCD Memory Map COM0 COM3 COM2 COM1 SEG0 SEG46 SEG45 SEG1 80H AEH ADH 81H SEG47 AFH COM0 COM2 COM1 SEG0 SEG46 SEG45 SEG1 80H AEH ADH ...

Page 174: ... to supply the LCD panel with the correct bias voltages A choice to best match the LCD panel used in the application can be selected also to minimise bias current The TYPE bit in the same register is used to select whether Type A or Type B LCD control signals are used LCDC Register Bit 7 6 5 4 3 2 1 0 Name TYPE DTYC BIAS RSEL1 RSEL0 LCDEN R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 TYPE LCD ...

Page 175: ...f Liquid Crystal Displays require that only AC voltages can be applied to their pixels as the application of DC voltages to LCD pixels may cause permanent damage For this reason the relative contrast of an LCD display is controlled by the actual RMS voltage applied to each pixel which is equal to the RMS value of the voltage on the COM pin minus the voltage applied to the SEG pin This differential...

Page 176: ...VLCD pin If the VDD voltage is greater than the voltage applied to the VLCD pin then the VMAX pin should be connected to VDD otherwise the VMAX pin should be connected to pin VLCD Note that no external capacitors or resistors are required to be connected if R type biasing is used Condition VMAX connection VDD VLCD Connect VMAX to VDD Otherwise Connect VMAX to VLCD R Type Bias VMAX Pin Connection F...

Page 177: ... generated by the microcontroller for various values of duty and bias The huge range of various permutations only permits a few types to be displayed here L C D F u n c t i o n i n N o r m a l O p e r a t i o n M o d e D u r i n g R e s e t o r L C D F u n c t i o n i s s w i t c h e d o f f LCD Driver Output Type A 1 3 Duty 1 2 Bias Note For 1 2 Bias the VA VLCD VB VLCD 1 2 for both R and C type ...

Page 178: ...L C D F u n c t i o n i n N o r m a l O p e r a t i o n M o d e D u r i n g R e s e t o r L C D F u n c t i o n i s s w i t c h e d o f f LCD Driver Output Type A 1 4 Duty 1 3 Bias Note For 1 3 R type bias the VA VLCD VB VLCD 2 3 and VC VLCD 1 3 For 1 3 C type bias the VA VLCD 1 5 VB VLCD and VC VLCD 1 2 ...

Page 179: ...M D u r i n g R e s e t o r L C D F u n c t i o n i s s w i t c h e d o f f L C D F u n c t i o n i n N o r m a l O p e r a t i o n M o d e LCD Driver Output Type A 1 3 Duty 1 3 Bias Note For 1 3 R type bias the VA VLCD VB VLCD 2 3 and VC VLCD 1 3 For 1 3 C type bias VA VLCD 1 5 VB VLCD and VC VLCD 1 2 ...

Page 180: ...de segments are ON Normal Operation Mode During Reset or LCD Off COM0 COM1 COM2 All segment outputs COM0 2 side segments are ON VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS All segments are ON LCD Driver Output Type B 1 3 Duty 1 3 Bias Note For 1 3 R type bias the VA VLCD VB VLCD 2 3 and ...

Page 181: ... M0 C M1 C M2 All segments a e FF C M0 side segments a e N C M3 C M1 side segments a e N C M2 side segments a e N othe om inations a e omitted C M0 1 side segments a e N C M3 side segments a e N Normal Operation Mode During Reset or LCD Off C M0 C M1 C M2 C M3 All segment outputs VA VB VC VSS VA VB VC VSS VA VB VC VSS C M0 2 side segments a e N VA VB VC VSS C M0 3 side segments a e N VA VB VC VSS ...

Page 182: ...CD used in the application As the load presented to the microcontroller by LCD pixels can be generally modeled as mainly capacitive in nature it is important that this is not excessive a point that is particularly true in the case of the COM lines which may be connected to many LCD pixels The accompanying diagram depicts the equivalent circuit of the LCD One additional consideration that must be t...

Page 183: ...application program All options must be defined for proper system function the details of which are shown in the table No Options 1 High Speed System Oscillator Selection fH HXT ERC EC or HIRC 2 HXT Mode Selection 1MHz 12MHz or 455kHz 3 Low Speed System Oscillator Selection fL LXT or LIRC 4 HIRC Frequency Selection 4MHz 8MHz or 12MHz 5 LCD Bias Type Selection R type or C type 6 LCD Voltage Selecti...

Page 184: ...DD PA7 RES VSS PB0 OSC1 PB1 OSC2 PB2 XT1 PB3 XT2 OSC Circuit OSC Circuit LCD Panel COM 3 0 SEG 47 0 VLCD VMAX 100KΩ 0 1uF 0 1uF 0 1uF 0 1uF C1 C2 V1 V2 0 1uF PA0 INT1 TCK1 PA1 TP0_1 PA2 TCK0 TCK2 PA3 TP2_0 PA4 INT0 PA5 TP2_1 PA6 TP0_0 PB4 TP1A PB5 TP1B_0 PB6 TP1B_1 PB7 TP1B_2 PC3 PC6 PD0 PD7 PE0 PE7 PF0 PF7 PG0 PG7 PH0 PH7 VDD ...

Page 185: ...so take one more cycle to implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instructions would be CLR PCL or MOV PCL A For the case of skip instructions it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle if no skip is involv...

Page 186: ...ful set of branch instructions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual bits Depending upon the conditions the program will continue with the next instruction or skip over it and jump to the following instruction These instructions are the key to decision making and branching within the program perhaps determined by t...

Page 187: ...in Data Memory 1Note Z C AC OV DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Memory to ACC 1 Z XOR A m Logical XOR Data Memory to ACC 1 Z ANDM A m Logical AND ACC to Data Memory 1Note Z ORM A m Logical OR ACC to Data Memory 1Note Z XORM A m Logical XOR ACC to Data Memory 1Note Z AND A x Log...

Page 188: ...eturn from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read Operation TABRD m Read table specific page to TBLH and Data Memory 2Note None TABRDC m Read table current page to TBLH and Data Memory 2Note None TABRDL m Read table last page to TBLH and Data Memory 2Note None Miscellaneous NOP No operation 1 None CLR m Clear Data Memory 1Note None SET m Set D...

Page 189: ...s of the Accumulator and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C AND A m Logical AND Data Memory to ACC D...

Page 190: ...escription The TO PDF flags and the WDT are all cleared Operation WDT cleared TO 0 PDF 0 Affected flag s TO PDF CLR WDT1 Pre clear Watchdog Timer Description The TO PDF flags and the WDT are all cleared Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect Repetitively executing this instruction without alternately executing CLR...

Page 191: ... be affected by this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Operation m ACC 00H or m ACC 06H or m ACC 60H or m ACC 66H Affected flag s C DEC m Decrement Data Memory Description Data in the specified Data Memory is decremented by 1 Operation m m 1 Affected flag s Z DECA m Decrement Data Memory with result in ACC Des...

Page 192: ...Memory Operation m ACC Affected flag s None NOP No operation Description No operation is performed Execution continues with the next instruction Operation No operation Affected flag s None OR A m Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation The result is stored in the Accumulator Operation ACC ACC OR m Affect...

Page 193: ...RLA m Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6 ACC 0 m 7 Affected flag s None RLC m Rotate Data Memory left through Carry Description The contents of the speci...

Page 194: ...cted flag s C SBC A m Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator The result is stored in the Accumulator Note that if the result of subtraction is negative the C flag will be cleared to 0 otherwise if the result is positive or zero the C flag will be set to 1 Operation ACC A...

Page 195: ...sult is not 0 the program proceeds with the following instruction Operation m m 1 Skip if m 0 Affected flag s None SIZA m Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1 If the result is 0 the following instruction is skipped The result is stored in the Accumulator but the specified Data Memory contents remai...

Page 196: ...ed Data Memory are interchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s None SZ m Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instructio...

Page 197: ...ge to TBLH and Data Memory Description The low byte of the program code last page addressed by the table pointer TBLP is moved to the specified Data Memory and the high byte moved to TBLH Operation m program code low byte TBLH program code high byte Affected flag s None XOR A m Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logica...

Page 198: ...dated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package Carton Information Additional supplementary information with regard to packaging is listed below Click on the relevant section to be transferred to the relevant website page Package Information include Outline Dimensions Product Tape and Reel Specifications The Operation Instruction of...

Page 199: ... in inch Min Nom Max A 0 354 BSC B 0 276 BSC C 0 354 BSC D 0 276 BSC E 0 020 BSC F 0 007 0 009 0 011 G 0 053 0 055 0 057 H 0 063 I 0 002 0 006 J 0 018 0 024 0 030 K 0 004 0 008 α 0 7 Symbol Dimensions in mm Min Nom Max A 9 00 BSC B 7 00 BSC C 9 00 BSC D 7 00 BSC E 0 50 BSC F 0 17 0 22 0 27 G 1 35 1 40 1 45 H 1 60 I 0 05 0 15 J 0 45 0 60 0 75 K 0 09 0 20 α 0 7 ...

Page 200: ...ons in inch Min Nom Max A 0 354 BSC B 0 276 BSC C 0 354 BSC D 0 276 BSC E 0 016 BSC F 0 005 0 007 0 009 G 0 053 0 055 0 057 H 0 063 I 0 002 0 006 J 0 018 0 024 0 030 K 0 004 0 008 α 0 7 Symbol Dimensions in mm Min Nom Max A 9 0 BSC B 7 0 BSC C 9 0 BSC D 7 0 BSC E 0 4 BSC F 0 13 0 18 0 23 G 1 35 1 40 1 45 H 1 60 I 0 05 0 15 J 0 45 0 60 0 75 K 0 09 0 20 α 0 7 ...

Page 201: ...nsions in inch Min Nom Max A 0 472 BSC B 0 394 BSC C 0 472 BSC D 0 394 BSC E 0 016 BSC F 0 007 0 009 0 011 G 0 053 0 055 0 057 H 0 063 I 0 002 0 006 J 0 018 0 024 0 030 K 0 004 0 008 α 0 7 Symbol Dimensions in mm Min Nom Max A 12 BSC B 10 BSC C 12 BSC D 10 BSC E 0 4 BSC F 0 13 0 18 0 23 G 1 35 1 4 1 45 H 1 60 I 0 05 0 15 J 0 45 0 60 0 75 K 0 09 0 20 α 0 7 ...

Page 202: ...ned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or syste...

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