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Rev. 1.10

96

November 26, 2019

Rev. 1.10

97

November 26, 2019

HT68FB240

USB Low Speed Flash MCU

7+1 PWM Mode

Each full PWM cycle, as it is controlled by an 8-bit PWM register, has 256 clock periods. However,
in the 7+1 PWM mode, each PWM cycle is subdivided into two individual sub-cycles known as
modulation cycle 0 ~ modulation cycle 1, denoted as "i" in the table. Each one of these two sub-
cycles contains 128 clock cycles. In this mode, a modulation frequency increase of two is achieved.
The 8-bit PWM register value, which represents the overall duty cycle of the PWM waveform, is
divided into two groups. The first group which consists of bit

1~bit

7 is denoted here as the DC

value. The second group which consists of bit

0 is known as the AC value. In the 7+1 PWM mode,

the duty cycle value of each of the two modulation sub-cycles is shown in the following table.

Parameter

AC (0~1)

DC (Duty Cycle)

Modulation cycle i

(i=0~1)

i < AC

(DC+1)/128

i ≥ AC

DC/128

7+1 PWM Mode

PWM Register for 7+1 Mode

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Summary of Contents for HT68FB240

Page 1: ...USB Low Speed Flash MCU HT68FB240 Revision V1 10 Date November 26 2019 ...

Page 2: ...5 Arithmetic and Logic Unit ALU 15 Flash Program Memory 16 Structure 16 Special Vectors 16 Look up Table 16 Table Program Example 17 In System Programming ISP 18 Flash Memory Read Write Page Size 18 ISP Bootloader 20 Flash Program Memory Registers 20 In Application Program IAP 24 In Circuit Programming ICP 28 On Chip Debug Support OCDS 29 RAM Data Memory 29 Structure 29 Special Function Register D...

Page 3: ...tchdog Timer Operation 47 WDT Enable Disabled using the WDT Control Register 47 Reset and Initialisation 48 Reset Overview 48 Reset Functions 49 Reset Initial Conditions 53 Input Output Ports 56 Pull high Resistors 56 Port Wake up 57 I O Port Control Registers 58 I O Pin Structures 60 Programming Considerations 60 Timer Modules TM 61 Introduction 61 TM Operation 61 TM Clock Source 61 TM Interrupts...

Page 4: ...dge Signal 90 I2 C Time Out Operation 92 Peripheral Clock Output 93 Peripheral Clock Operation 93 Pulse Width Modulator 94 PWM Operation 94 6 2 PWM Mode 95 7 1 PWM Mode 96 PWM Output Control 97 PWM Programming Example 97 Interrupts 98 Interrupt Registers 98 Interrupt Operation 101 External Interrupt 103 USB SIE Interrupt 103 USB Setup Token Interrupt 103 USB Endpoint 0 IN Token Interrupt 103 USB E...

Page 5: ...117 Introduction 117 Instruction Timing 117 Moving and Transferring Data 117 Arithmetic Operations 117 Logical and Rotate Operation 118 Branches and Control Transfer 118 Bit Operations 118 Table Read Operations 118 Other Operations 118 Instruction Set Summary 119 Table Conventions 119 Instruction Definition 121 Package Information 130 SAW Type 46 pin QFN 6 5mm 4 5mm Outline Dimensions 131 48 pin L...

Page 6: ...ing endpoint 0 All endpoints except endpoint 0 support interrupt transfer Endpoint 0 supports control transfer for Setup In and Out token respectively Endpoint 0 has 8 bytes FIFO size supports DMA interface for configure USB descriptor Support 3 3V LDO and integrate an internal 1 5K ohm pull up resistor on UDN line Internal 12MHz RC OSC with 1 5 accuracy for all USB modes Watchdog Timer function U...

Page 7: ...environments The external interrupt can be triggered with falling edges or both falling and rising edges A full choice of two oscillator functions are provided including two fully integrated system oscillators which requires no external components for their implementation The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ...

Page 8: ...O function of the pins However these Port pins are also shared with other function such as the Serial Port pins etc The function of each pin is listed in the following table however the details behind how each pin is configured is contained in other sections of the datasheet Pin Name Function OPT I T O T Description PA0 OCDSDA PA0 PAPU PAWU ST CMOS General purpose I O Register enabled pull high an...

Page 9: ... PC6 PXPU PXWU ST CMOS General purpose I O Register enabled pull high and wake up PWM2 PWMC CMOS PWM2 output PC7 PC7 PXPU PXWU ST CMOS General purpose I O Register enabled pull high and wake up PD0 PD3 PDn PXPU PXWU ST CMOS General purpose I O Register enabled pull high and wake up PD4 TCK0 PD4 PXPU PXWU ST CMOS General purpose I O Register enabled pull high and wake up TCK0 ST TM0 clock input PD5...

Page 10: ... Characteristics Ta 25 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions VDD Operating Voltage HIRC OSC fSYS 12MHz 3 3 5 5 V IDD1 Operating Current HIRC OSC fSYS fH fS fSUB fLIRC 3V No load fH 12MHz WDT enable USB disable LVR enable 2 2 3 3 mA 5V 5 0 7 5 mA IDD2 Operating Current LIRC OSC fSYS fL fLIRC fS fSUB fLIRC 3V No load WDT enable fLIRC 32K Clear CLK_ADJ SYSC 7 0 USB disabl...

Page 11: ... Pull high Resistance between UDN and V33O 3 3V 5 1 5 5 kΩ RPH Pull high Resistance of I O Ports 3V 20 60 100 kΩ 5V 10 30 50 kΩ A C Characteristics Ta 25 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions fSYS System clock HIRC OSC USB mode USB On 4 2V 5 5V Ta 25 C 3 12 3 MHz fLIRC System clock 32K RC 5V Ta 25 C 10 32 10 kHz 2 2V 5 5V Ta 40 C to 85 C 50 32 60 kHz tTCK TCKn Input Pi...

Page 12: ...is used 3V LVR disable LVR enable 30 45 μA 5V 60 90 μA ILVD Additional Power Consumption if LVD is used 3V LVD disable LVD enable LVR disable 40 60 μA 5V 75 115 μA 3V LVD disable LVD enable LVR enable 30 45 μA 5V 60 90 μA tLVR Low Voltage Width to Reset 120 240 480 μs tLVD Low Voltage Width to Interrupt 20 45 90 μs tSRESET Software Reset Width to Reset 45 90 120 μs tLVDS LVDO stable time For LVR e...

Page 13: ...y and flexibility This makes the device suitable for low cost high volume production for controller applications Clocking and Pipelining The main system clock derived from either a HIRC or LIRC oscillator is subdivided into four internally generated non overlapping clocks T1 T4 The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched The re...

Page 14: ...into the Program Counter For conditional skip instructions once the condition has been met the next instruction which has already been fetched during the present instruction execution is discarded and a dummy cycle takes its place while the correct instruction is obtained Program Counter High Byte Low Byte PCL Register PC11 PC8 PCL7 PCL0 Program Counter The lower byte of the Program Counter known ...

Page 15: ... instruction can still be executed which will result in a stack overflow Precautions should be taken to avoid such cases which might cause unpredictable program branching If the stack is overflow the first Program Counter save in the stack will be lost P r o g r a m C o u n t e r S t a c k L e v e l 1 S t a c k L e v e l 2 S t a c k L e v e l 3 S t a c k L e v e l 8 P r o g r a m M e m o r y T o p...

Page 16: ...ram Memory certain locations are reserved for the reset and interrupts The location 000H is reserved for use by the device reset for program initialisation After a device reset is initiated the program will jump to this location and begin execution Look up Table Any location within the Program Memory can be defined as a look up table where programmers can store fixed data To use the look up table ...

Page 17: ...ter and cannot be restored care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions If using the table read instructions the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine As a rule it is recommended that simultaneous use of the table read instruction...

Page 18: ...ices are beyond the scope of this document and will be supplied in supplementary literature The Flash Program Memory Read Write function is implemented using a series of registers Flash Memory Read Write Page Size The Flash memory page size is 32 words The page and buffer size are assigned as 32 words The following diagram illustrates the Read Write page and buffer assignment The write buffer is c...

Page 19: ... into FARH and FARL registers in the same page then the data will be written into the corresponding address 2 If the address already reached the boundary of the flash memory such as 11111b of the 32 words at this moment the address will not be increased and the address will stop at the last address of that page and the writing data is invalid 3 At this point the user has to set a new address again...

Page 20: ...address and data registers and the control register Several registers control the overall operation of the internal Flash Program Memory The address registers are named FARL and FARH the data registers are named FDnL and FDnH and the single control register is named FCR As the FARL and FDnL registers are located in Bank 0 they can be directly accessed in the same was as any other Special Function ...

Page 21: ...ss Flash Program Memory address bit 11 bit 8 FD0L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR x x x x x x x x x unknown Bit 7 0 D7 D0 The first Flash ROM data The first Flash ROM data 7 0 FD0H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R W R W R W R W R W R W R W R W R W POR x x x x x x x x x unknown Bit 7 0 D15 D8 The firs...

Page 22: ...e third Flash ROM data 7 0 FD2H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R W R W R W R W R W R W R W R W R W POR x x x x x x x x x unknown Bit 7 0 D15 D8 The third Flash ROM data The third Flash ROM data bit 15 8 FD3L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR x x x x x x x x x unknown Bit 7 0 D7 D0 The fourth Flash ROM ...

Page 23: ... This bit will be automatically reset to zero by the hardware after the mode change cycle has finished Bit 2 FWT Flash memory Write Control 0 write cycle has finished 1 activate a write cycle This is the Flash memory Write Control Bit and when set high by the application program will activate a write cycle This bit will be automatically reset to zero by the hardware after the write cycle has finis...

Page 24: ...am Regarding the internal firmware the user can select versions provided by HOLTEK or create their own The following section illustrates the procedures regarding how to implement IAP firmware Enable Flash Write Control Procedure The first procedure to implement the IAP firmware is to enable the Flash Write control which includes the following steps Write data 110 to the FMOD 2 0 bits in the FCR re...

Page 25: ...D 2 0 110 Set FWEN bit BWT 1 Hardware set a counter Wrtie the following pattern to Flash Data register FD1L 00h FD1H 04h FD2L 0dh FD2H 09h FD3L C3h FD3H 40h Is pattern is correct CFWEN 0 Set FWEN bit fail no CFWEN 1 Set FWEN bit success yes END Is counter overflow no yes BWT 0 ...

Page 26: ...procedure FWT 1 Yes Page Erase FAH xxh FAL xxh FMOD 2 0 001 FWT 1 FWT 0 Yes No Write FMOD 2 0 000 Clear CFWEN bit END Write Finish Yes No Write data to Write Buffer ROM 8K 1 32 Words data or ROM 8K 1 64 Words data Flash address register FAH xxh FAL xxh Write the following data to register FD0L xxh FD0H xxh Write Buffer Finish No Write next Page Write next data Yes FWT 0 No Write Flash Program ROM ...

Page 27: ...HT68FB240 USB Low Speed Flash MCU Read Flash ROM FDEN 0 Clear CFWEN bit END Read Finish yes no FMOD 2 0 011 FDEN 1 flash address register FAH xxh FAL xxh FRD 0 yes no Read value FD0L xxh FD0H xxh FRD 1 Read Flash Program Procedure ...

Page 28: ...MCU to Writer Programming Pin correspondence table is as follows Holtek Writer Pins MCU Programming Pins Pin Description ICPDA UDN Programming Serial Data Address ICPCK RES Programming Clock VDD VDD Power Supply VSS VSS Ground The Program Memory can be programmed serially in circuit using this 4 wire interface Data is downloaded and uploaded serially on a single pin with an additional line for the...

Page 29: ...ata Address input output OCDSCK OCDSCK On chip Debug Support Clock input VDD VDD Power Supply GND VSS Ground RAM Data Memory The Data Memory is a volatile area of 8 bit wide RAM internal memory and is the location where temporary information is stored Structure Divided into two sections the first of these is an area of RAM known as the Special Function Data Memory Here are located registers which ...

Page 30: ...C0 BP INTC2 13H MFI0 PAWU 15H 16H 14H PAPU PA I2CTOC SIMC1 2DH 2EH 2FH SIMC0 Unused read as 00H Bank 0 1 Bank 1 22H PEC 35H TM0C1 36H TM0DL TM0DH TM0AL TM0AH TM1C0 TM1C1 TM1DL TM1DH TM1AL TM1AH FRCR FCR FARH FD0H FD1H FD2H FD3H USB_STAT UINT USC UCC AWR STL 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H SIES MISC UFEN FIFO0 FIFO1 FIFO2 URDCT PWMC PWM0 PWM1 PWM2 CTRL LVRC SYSC 45H 46H 47H ...

Page 31: ...nters MP0 MP1 Two Memory Pointers known as MP0 and MP1 are provided These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data When any operation to the relevant Indirect Addressing Registers is carried out the actual address that the microcontroller is directed to is...

Page 32: ...r programming and timing overheads Data transfer operations usually involve the temporary storage function of the Accumulator for example when transferring data between one user defined register and another it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted Program Counter Low Register PCL To provide additional program co...

Page 33: ...est operations C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation otherwise C is cleared C is also affected by a rotate through carry instruction AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction otherwise AC is c...

Page 34: ... overflow 1 an operation results in a carry into the highest order bit but not a carry out of the highest order bit or vice versa Bit 2 Z Zero flag 0 The result of an arithmetic or logical operation is not zero 1 The result of an arithmetic or logical operation is zero Bit 1 AC Auxiliary flag 0 no auxiliary carry 1 an operation results in a carry out of the low nibbles in addition or no borrow fro...

Page 35: ...C LIRC 32kHz Oscillator Types System Clock Configurations There are several oscillator sources a high speed oscillator and a low speed oscillator The high speed system clock is sourced from the internal 12MHz RC oscillator and the automatic adjust clock The low speed oscillator is the internal 32kHz RC oscillator Selecting whether the low or high speed oscillator is used as the system oscillator i...

Page 36: ...USP2 USBCKEN EPS1 EPS0 R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 Rctrl 7 5kΩ resistor between UDN and UBUS control bit Described elsewhere Bit 6 SYSCLK Specify MCU oscillator frequency indication bit 0 12MHz 1 6MHz Bit 5 Unimplemented read as 0 Bit 4 SUSP2 Reduce power consumption in suspend mode control bit Described elsewhere Bit 3 USBCKEN USB clock control bit 0 disable 1 enable Bit 2 U...

Page 37: ...ating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible conflicting requirements that are especially true in battery powered portable applications The fast clocks required for high performance will by their nature increase current consumption and of course vice versa lower ...

Page 38: ...it to use System Operation Modes There are six different modes of operation for the microcontroller each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application There are two modes allowing normal operation of the microcontroller the NORMAL Mode and SLOW Mode The remaining four modes the SLEEP0 SLEEP1 IDLE0 an...

Page 39: ... the IDLEN bit in the SMOD register is low In the SLEEP0 mode the CPU will be stopped and the fSUB clock will be stopped too and the Watchdog Timer function is disabled In this mode the LVDEN is must set to 0 If the LVDEN is set to 1 it won t enter the SLEEP0 Mode SLEEP1 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low In the SL...

Page 40: ... indicates when the high speed system oscillator is stable This flag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable Therefore this flag will always be read as 1 by the application program after device power on The flag will be low when in the SLEEP or IDLE0 Mode but after a wake up has occurred the flag wi...

Page 41: ... NORMAL SLOW Modes to the SLEEP IDLE Modes is executed via the HALT instruction When a HALT instruction is executed whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL register When the HLCLK bit switches to a low level which implies that clock source is switched from the high speed clock source fH to...

Page 42: ...t to 0 and set the CKS2 CKS0 bits to 000 or 001 in the SMOD register This will then use the low speed system oscillator which will consume less power Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption The SLOW Mode is sourced from the LIRC oscillators and therefore requires these oscillators to be stable before ful...

Page 43: ...which high speed system oscillator type is used Entering the SLEEP0 Mode There is only one way for the device to enter the SLEEP0 Mode and that is to execute the HALT instruction in the application program with the IDLEN bit in SMOD register equal to 0 and the WDT and LVD both off When this instruction is executed under the conditions described above the following will occur The system clock and W...

Page 44: ...gister equal to 0 When this instruction is executed under the conditions described above the following will occur The system clock will be stopped and the application program will stop at the HALT instruction but the fSUB clock will be on The Data Memory contents and registers will maintain their present condition The WDT will be cleared and resume counting if the WDT is enabled The I O ports will...

Page 45: ...n external or USB reset An external falling edge on Ports A system interrupt A WDT overflow If the system is woken up by an external or USB reset the device will experience a full system reset however if the device is woken up by a WDT overflow a Watchdog Timer reset will be initiated Although both of these wake up methods will initiate a reset operation the actual source of the wake up can be det...

Page 46: ...llator The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts the actual value being chosen using the WS2 WS0 bits in the WDTC register The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V However it should be noted that this specified internal clock period can vary with VDD temperature and process variations The WDT ...

Page 47: ...d to the Watchdog Timer enable disable function there are five bits WE4 WE0 in the WDTC register to offer additional enable disable and reset control of the Watchdog Timer WDT Enable Disabled using the WDT Control Register The WDT is enabled disabled using the WDT control register the WE4 WE0 values can determine which mode the WDT operates in The WDT will be disabled when the WE4 WE0 bits are set...

Page 48: ...rdware and software reset sources that can be implemented dynamically when the device is running Reset Overview The most important reset condition is after power is first applied to the microcontroller In this case internal circuitry will ensure that the microcontroller after a short delay will be in a well defined state and ready to execute the first program instruction After this power on reset ...

Page 49: ...s a power on reset also ensures that certain other registers are preset to known conditions All the I O port and port control registers will power up in a high condition ensuring that all I O ports will be first set to inputs Power On Reset Timing Chart RES Pin Although the microcontroller has an internal RC reset function if the VDD power supply rise time is not fast enough or does not stabilise ...

Page 50: ...h a specific LVR voltage VLVR If the supply voltage of the device drops to within a range of 0 9V VLVR such as might occur when changing the battery the LVR will automatically reset the device internally and the LVRF bit in the CTRL register will also be set to 1 For a valid LVR signal a low supply voltage i e a voltage in the range between 0 9V VLVR must exist for a time greater than that specifi...

Page 51: ... an MCU reset The reset operation will be activated after 2 3 LIRC clock cycles However in this situation the register contents will be reset to the POR value CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON LVRF LRF WRF R W R W R W R W R W POR 0 x 0 0 x unknown Bit 7 FSYSON fSYS Control in IDLE Mode Described elsewhere Bit 6 3 Unimplemented read as 0 Bit 2 LVRF LVR function reset flag 0 not occur 1 ...

Page 52: ... Time out Reset during Sleep Timing Chart WDTC Register Software Reset A WDTC software reset will be generated when a value other than 10101 or 01010 exist in the highest five bits of the WDTC register The WRF bit in the CTRL register will be set high when this occurs thus indicating the generation of a WDTC software reset WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R W ...

Page 53: ...lear control bit Described elsewhere Reset Initial Conditions The different types of reset described affect the reset flags in different ways These flags known as PDF and TO are located in the status register and are controlled by various microcontroller operations such as the SLEEP or IDLE Mode function or Watchdog Timer The reset flags are shown in the table TO PDF Reset Conditions 0 0 Power on ...

Page 54: ...0 0 0 0 0 0 u u u u u u u u 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PAC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u 1 1 1 1 1 1 1 1 1 1 1 1 ...

Page 55: ... x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u x x x x x x x x x x x x x x x x USB_ STAT 1 1 x x 0 0 0 u u x x 0 0 u u u x x 0 0 u u u x x 0 0 u u u x x 0 0 u u u x x 0 0 u u u x x 0 0 u UINT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u 0 0 0 0 0 0 0 0 0 0 0 0 USC 1 0 0 x 0 x x u u u x u x x u u u x u x x u u u x u x x u u u x u x x u u u 0 1 0 0 u u u 0 1 0 0 ...

Page 56: ...5 4 3 2 1 0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PXWU PELWU PDHWU PDLWU PCHWU PCLWU PBHWU PBLWU PXPU PELPU PDHPU PDLPU PCHPU PCLPU PBHPU PBLPU PB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PC PC7 PC6 PC5 PC4 PC3 PC2 PC1...

Page 57: ...3 PB0 pins Pull High control 0 Disable 1 Enable Port Wake up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power a feature that is important for battery and other low power applications Various methods exist to wake up the microcontroller one of which is to change the logic condition on one of the Port A Port E pins from high to low This function is es...

Page 58: ...er known as PAC PEC to control the input output configuration With this control register each CMOS output or input can be reconfigured dynamically under software control Each pin of the I O ports is directly mapped to a bit in its associated port control register For the I O pin to function as an input the corresponding bit of the control register must be written as a 1 This will then allow the lo...

Page 59: ...CC3 PCC2 PCC1 PCC0 R W R W R W R W R W R W R W R W R W POR 1 1 1 1 1 1 1 1 Bit 7 0 PCC7 PCC0 Port C bit 7 bit 0 Input Output Control 0 Output 1 Input PDC Register Bit 7 6 5 4 3 2 1 0 Name PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 R W R W R W R W R W R W R W R W R W POR 1 1 1 1 1 1 1 1 Bit 7 0 PDC7 PDC0 Port D bit 7 bit 0 Input Output Control 0 Output 1 Input PEC Register Bit 7 6 5 4 3 2 1 0 Name PEC...

Page 60: ...mmed to setup some pins as outputs these output pins will have an initial high output value unless the associated port data registers PA PE are first programmed Selecting which pins are inputs and which are outputs can be achieved byte wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the SET m i and C...

Page 61: ...evice TM0 TM1 HT68FB240 10 bit CTM 10 bit CTM TM Name Type Reference TM Operation The TM offers a diverse range of functions from simple timing operations to PWM signal generation The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre programmed internal comparators When the free running counter has the same v...

Page 62: ...nB output pin is also the pin where the TM generates the PWM output waveform As the TM output pins are pin shared with other function the TM output function must first be setup using registers A single bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function The number of output pins for each TM type and device is ...

Page 63: ...Rev 1 10 63 November 26 2019 HT68FB240 USB Low Speed Flash MCU TM0 TM1 Function Pin Control Block Diagram ...

Page 64: ...ribed above it is recommended to use the MOV instruction to access the CCRA low byte register named TMxAL using the following access procedures Accessing the CCRA low byte register without following these access procedures will result in unpredictable values The following steps show the read and write procedures Writing Data to CCRA Step 1 Write data to Low Byte TMxAL Note that here data is only w...

Page 65: ... and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP is three bits wide whose value is compared the highest three bits in the counter while the CCRA is the ten bits and therefore compares all counter bits The only way of changing the value of the 10 bit counter using the application program is to clear the counter by changing the TnON bit ...

Page 66: ...ndition the TM will remain powered up and continue to consume power The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again Bit 6 4 TnCK2 TnCK0 Select TMn Counter clock 000 fSYS 4 001 fSYS 010 fH 16 011 fH 64 100 fLIRC 101 Undefined 110 TCKn rising edge clock 111 TCKn falling edge clock These th...

Page 67: ...gister n 0 1 Bit 7 6 5 4 3 2 1 0 Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 TnM1 TnM0 Select TMn Operating Mode 00 Compare Match Output Mode 01 Undefined 10 PWM Mode 11 Timer Counter Mode These bits setup the required operating mode for the TM To ensure reliable operation the TM should be switched off before any changes are ma...

Page 68: ... in the PWM Mode It has no effect if the TM is in the Timer Counter Mode In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs In the PWM Mode it determines if the PWM signal is active high or active low Bit 2 TnPOL TPn TPnB Output polarity Control 0 Non invert 1 Invert This bit controls the polarity of the TPn TPnB output pin When the bi...

Page 69: ... POR 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 D9 D8 TMn Counter High Byte Register bit 1 bit 0 TMn 10 bit Counter bit 9 bit 8 TMnAL Register n 0 1 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 D7 D0 TMn CCRA Low Byte Register bit 7 bit 0 TMn 10 bit CCRA bit 7 bit 0 TMnAH Register n 0 1 Bit 7 6 5 4 3 2 1 0 Name D9 D8 R W R W R W ...

Page 70: ...er here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when TnCCLR is high no TnPF interrupt request flag will be generated If the CCRA bits are all zero the counter will overflow when its reaches its maximum 10 bit 3FF Hex value however here the TnAF interrupt request flag will not be generated As the nam...

Page 71: ...0 Output Toggle with TnAF flag Note TnIO 1 0 10 Active High Output select Here TnIO 1 0 11 Toggle Output select Output not affected by TnAF flag Remains High until reset by TnON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when TnPOL is high Compare Match Output Mode TnCCLR 0 n 0 1 Note 1 With TnCCLR 0 a Comparator P match will clear the count...

Page 72: ...ut select Here TnIO 1 0 11 Toggle Output select Output not affected by TnAF flag Remains High until reset by TnON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when TnPOL is high TnPF not generated No TnAF flag generated on CCRA overflow Output does not change Compare Match Output Mode TnCCLR 1 n 0 1 Note 1 With TnCCLR 1 a Comparator A match wi...

Page 73: ...ister is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers An interrupt flag one ...

Page 74: ...er Reset when TnON returns high TnDPX 0 TnM 1 0 10 PWM Duty Cycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts when TnPOL 1 PWM Period set by CCRP TM O P Pin TnOC 0 PWM Mode TnDPX 0 n 0 1 Note 1 Here TnDPX 0 Counter cleared by CCRP 2 A counter clear sets the PWM Period 3 The internal PWM function continues even when TnIO 1 0 00 or 01 4 The TnCCLR ...

Page 75: ...er Reset when TnON returns high TnDPX 1 TnM 1 0 10 PWM Duty Cycle set by CCRP PWM resumes operation Output controlled by other pin shared function Output Inverts when TnPOL 1 PWM Period set by CCRA TM O P Pin TnOC 0 PWM Mode TnDPX 1 n 0 1 Note 1 Here TnDPX 1 Counter cleared by CCRA 2 A counter clear sets the PWM Period 3 The internal PWM function continues even when TnIO 1 0 00 or 01 4 The TnCCLR ...

Page 76: ...ation protocol simplifying the programming requirements when communicating with external hardware devices The communication is full duplex and operates as a slave master type where the device can be either master or slave Although the SPI interface specification can control multiple slave devices from a single master but this device provided only one SCS pin If the master needs to control multiple...

Page 77: ...SPI interface These are the SIMD data register and three registers SIMC0 SIMC2 and SBSC Note that the SIMC1 register is only used by the I2 C interface Register Name Bit 7 6 5 4 3 2 1 0 SIMC0 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMC2 D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF SBSC SIM_WCOL I2CDB1 I2CDB0 SIM Registers List The SIMD register is used to store the data being t...

Page 78: ... I2 C slave mode 111 I O mode These bits setup the overall operating mode of the SIM function As well as selecting if the I2 C or SPI function they are used to control the SPI Master Slave selection and the SPI Master clock frequency The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0 If the SPI Slave Mode is selected then the clock will be supplied by...

Page 79: ... CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated The CKPOLB bit determines the base condition of the clock line if the bit is high then the SCK line will be low when the clock is inactive When the CKPOLB bit is low then the SCK lin...

Page 80: ... SIMEN bit high then in the Master Mode when data is written to the SIMD register transmission reception will begin simultaneously When the data transfer is complete the TRF flag will be set automatically but must be cleared using the application program In the Slave Mode when the clock signal from the master has been received any data in the SIMD register will be transmitted and any data on the S...

Page 81: ...Rev 1 10 81 November 26 2019 HT68FB240 USB Low Speed Flash MCU SPI Slave Mode Timing CKEG 0 SPI Slave Mode Timing CKEG 1 SPI Transfer Control Flowchart ...

Page 82: ... register If in Slave Mode the SCK line will be in a floating condition If the SIMEN bit is low then the bus will be disabled and SCS SDI SDO and SCK will all become I O pins or the other functions In the Master Mode the Master will always generate the clock signal The clock and data transmission will be initiated after data has been written into the SIMD register In the Slave Mode the clock signa...

Page 83: ...uffer until all the data has been received at which point it will be latched into the SIMD register Step 5 Check the WCOL bit if set high then a collision error has occurred so return to step 4 If equal to zero then go to the following step Step 6 Check the TRF bit or wait for a SPI serial bus interrupt Step 7 Read data from the SIMD register Step 8 Clear TRF Step 9 Go to step 4 Error Detection Th...

Page 84: ...er device and one as the slave device Both master and slave can transmit and receive data however it is the master device that has overall control of the bus For this device which only operates in slave mode there are two methods of transferring data on the I2 C bus the slave transmit mode and the slave receive mode There are several configuration options associated with the I2 C interface One of ...

Page 85: ... SIMEN SIMC1 HCF HAAS HBB HTX TXAK SRW IAMWU RXAK SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMA IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 SBSC SIM_WCOL I2CDB1 I2CDB0 I2 C Registers List SIMC0 Register Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN R W R W R W R W R W R W R W R W POR 1 1 1 0 0 0 0 Bit 7 5 SIM2 SIM0 SIM Operating Mode Control 000 SPI master mode SPI clock is fSYS 4 001 SPI m...

Page 86: ...AK SRW IAMWU RXAK R W R R R R W R W R R W R POR 1 0 0 0 0 0 0 1 Bit 7 HCF I2 C Bus data transfer completion flag 0 Data is being transferred 1 Completion of an 8 bit data transfer The HCF flag is the data transfer flag This flag will be zero when data is being transferred Upon completion of an 8 bit data transfer the flag will go high and an interrupt will be generated Bit 6 HAAS I2 C Bus address ...

Page 87: ...lag 0 Slave receive acknowledge flag 1 Slave do not receive acknowledge flag The RXAK flag is the receiver acknowledge flag When the RXAK flag is 0 it means that a acknowledge signal has been received at the 9th clock after 8 bits of data have been transmitted When the slave device in the transmit mode the slave device checks the RXAK flag to determine if the master receiver wishes to receive the ...

Page 88: ...efined When a master device which is connected to the I2 C bus sends out an address which matches the slave address in the SIMA register the slave device will be selected Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface Bit 0 Undefined bit This bit can be read or written by user software program SBSC Register Bit 7 6 5 4 3 2 1 0 Name SIM_WCOL I2C...

Page 89: ...s has been transmitted the following bit which is the 8th bit is the read write bit whose value will be placed in the SRW bit This bit will be checked by the slave device to determine whether to go into transmit or receive mode Before any transfer of data to or from the I2 C bus the microcontroller must initialise the bus the following are steps to achieve this Step 1 Set the SIM2 SIM0 and SIMEN b...

Page 90: ...herefore the slave device must be setup to read data from the I2 C bus as a receiver I2 C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address any slave device on the I2 C bus whose own internal address matches the calling address must generate an acknowledge signal The acknowledge signal will inform the master that a slave device has accepted its calling address...

Page 91: ...on Timing Diagram Note When a slave address is matched the device must be placed in either the transmit mode and then write data to the SIMD register or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line I2 C Bus ISR Flow Chart ...

Page 92: ...upt will also take place Note that this scheme can also be stopped when the I2 C received the STOP bit There are several time out periods can be selected by the I2CTOS0 I2CTOS5 bits in the I2CTOC register I2CTOC Register Bit 7 6 5 4 3 2 1 0 Name I2CTOEN I2CTOF I2CTOS5 I2CTOS4 I2CTOS3 I2CTOS2 I2CTOS1 I2CTOS0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 I2CTOEN I2 C Time Out functio...

Page 93: ...aster mode SPI clock is fSYS 16 010 SPI master mode SPI clock is fSYS 64 011 SPI master mode SPI clock is fLIRC 100 SPI master mode SPI clock is TM0 CCRP match frequency 2 101 SPI slave mode 110 I2 C slave mode 111 I O mode These bits setup the overall operating mode of the SIM function As well as selecting if the I2 C or SPI function they are used to control the SPI Master Slave selection and the...

Page 94: ... the subdivision of the waveform into its sub modulation cycles is implemented automatically within the microcontroller hardware For the device the PWM clock source is the system clock fSYS This method of dividing the original modulation cycle into a further 2 4 sub cycles enables the generation of higher PWM frequencies which allow a wider range of applications to be served As long as the periods...

Page 95: ...esents the overall duty cycle of the PWM waveform is divided into two groups The first group which consists of bit 2 bit 7 is denoted here as the DC value The second group which consists of bit 0 bit 1 is known as the AC value In the 6 2 PWM mode the duty cycle value of each of the four modulation sub cycles is shown in the following table The following diagram illustrates the waveforms associated...

Page 96: ...clock cycles In this mode a modulation frequency increase of two is achieved The 8 bit PWM register value which represents the overall duty cycle of the PWM waveform is divided into two groups The first group which consists of bit 1 bit 7 is denoted here as the DC value The second group which consists of bit 0 is known as the AC value In the 7 1 PWM mode the duty cycle value of each of the two mod...

Page 97: ...output data register will disable The PWM output function and force the output low In this way the Port C data output register can be used as an on off control for the PWM function Note that if the configuration options have selected the PWM function but a 1 has been written to its corresponding bit in the PCC control register to configure the pin as an input then the pin can still function as a n...

Page 98: ...le The first is the INTC0 INTC2 registers which setup the primary interrupts the second is the MFI0 register which setup the Multi function interrupts Finally there is an INTEG register to setup the external interrupt trigger edge type Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request...

Page 99: ...11 both rising and falling edges INTC0 Register Bit 7 6 5 4 3 2 1 0 Name USBF INT1F INT0F USBE INT1E INT0E EMI R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 USBF USB SIE Interrupt Request Flag 0 No request 1 Interrupt request Bit 5 INT1F INT1 Interrupt Request flag 0 No request 1 Interrupt request Bit 4 INT0F INT0 Interrupt Request Flag 0 No request 1 Interr...

Page 100: ...n Interrupt Control 0 Disable 1 Enable Bit 1 UITE USB Endpoint 0 IN Token Interrupt Control 0 Disable 1 Enable Bit 0 USTE USB Setup Token Interrupt Control 0 Disable 1 Enable INTC2 Register Bit 7 6 5 4 3 2 1 0 Name LVF SIMF MF0F LVE SIME MF0E R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 LVF LVD Interrupt Request Flag 0 No request 1 Interrupt request Bit 5 SIMF SI...

Page 101: ...rates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit If the enable bit is set high then the program will jump to its relevant vector if the enable bit is zero then although the interrupt request ﬂag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector The global interrupt enable b...

Page 102: ...terrupt request will not be acknowledged even if the related interrupt is enabled until the Stack Pointer is decremented If immediate service is desired the stack must be prevented from becoming full In case of simultaneous requests the accompanying diagram shows the priority that is applied All of the interrupt request ﬂags when set will wake up the device if it is in SLEEP or IDLE Mode however t...

Page 103: ...errupt request flags USBF is set a situation that will occur when an endpoint except endpoint 0 is accessed To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EMI and USB SIE interrupt enable bit USBE must first be set When the interrupt is enabled the stack is not full and an endpoint is accessed a subroutine call to the USB SIE interrupt vec...

Page 104: ...or interrupt known as the LVD interrupt will take place when the LVD Interrupt request flag LVF is set which occurs when the Low Voltage Detector function detects a low power supply voltage To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EMI and Low Voltage Interrupt enable bit LVE must first be set When the interrupt is enabled the stack i...

Page 105: ...nters the SLEEP or IDLE Mode The interrupt enable bits have no effect on the interrupt wake up function Programming Considerations By disabling the relevant interrupt enable bits a requested interrupt can be prevented from being serviced however once an interrupt request flag is set it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until th...

Page 106: ...ned A low voltage condition is indicated when the LVDO bit is set If the LVDO bit is low this indicates that the VDD voltage is above the preset low voltage value The LVDEN bit is used to control the overall on off function of the low voltage detector Setting the bit high will enable the low voltage detector Clearing the bit to zero will switch off the internal low voltage detector circuits As the...

Page 107: ...slowly at the voltage nears that of VLVD there may be multiple bit LVDO transitions LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multi function interrupts providing an alternative means of low voltage detection in addition to polling the LVDO bit The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high...

Page 108: ...ode The Suspend flag SUSP in the USC register will then be set high and an USB interrupt will be generated to indicate that the device should jump to the suspend state to meet the requirements of the USB suspend current spec In order to meet the requirements of the suspend current the firmware should disable the USB clock by clearing the USBCKEN bit to 0 The suspend current can be further decrease...

Page 109: ...series of registers associated with its operation USB_STAT Register Bit 7 6 5 4 3 2 1 0 Name PS2_CKO PS2_DAO PS2_CKI PS2_DAI SE1 SE0 PU ESD R W W W R R R W R W R W R W POR 1 1 x x 0 0 0 x unknown Hardware did not give ESD bit initial value in power on reset Bit 7 PS2_CKO Output for driving UDP GPIO1 pin when work under 3D PS2 mouse function Default value is 1 Bit 6 PS2_DAO Output for driving UDN G...

Page 110: ...n 0 no accessed 1 accessed Bit 4 EP0F USB endpoint0 accessed detection 0 no accessed 1 accessed Bit 3 Unimplemented read as 0 Bit 2 EP2EN USB endpoint2 interrupt control bit 0 disable 1 enable Bit 1 EP1EN USB endpoint1 interrupt control bit 0 disable 1 enable Bit 0 EP0EN USB endpoint0 interrupt control bit 0 disable 1 enable USC Register Bit 7 6 5 4 3 2 1 0 Name URD SELPS2 SELUSB RESUME URST RMWK ...

Page 111: ...et by SIE an interrupt will be generated to wake up the MCU In order to detect the suspend state the MCU should set USBCKEN and clear SUSP2 in the UCC register to enable the SIE detect function RESUME will be cleared when the SUSP goes to 0 When the MCU is detecting the SUSP the condition of RESUME causes the MCU to wake up should be noted and taken into consideration Bit 2 URST USB reset indicati...

Page 112: ...normal mode 1 in halt mode set this bit to 1 for reducing power consumption Bit 3 USBCKEN USB clock control bit 0 Disable 1 Enable Bit 2 Unimplemented read as 0 Bit 1 0 EPS1 EPS0 Accessing endpoint FIFO selection 00 select endpoint 0 FIFO control 01 select endpoint 1 FIFO 10 11 select endpoint 2 FIFO AWR Register Bit 7 6 5 4 3 2 1 0 Name AD6 AD5 AD4 AD3 AD2 AD1 AD0 WKEN R W R W R W R W R W R W R W...

Page 113: ...eset signal and a setup token event SIES Register Bit 7 6 5 4 3 2 1 0 Name NMI CRCF NAK IN OUT ERR ASET R W R W R W R R R W R W R W POR x x x x x x x x unknown Bit 7 NMI NAK token interrupt mask flag 0 interrupt enable 1 interrupt disable If this bit set when the device sent a NAK token to the host an interrupt will be disabled Otherwise if this bit is cleared when the device sends a NAK token to ...

Page 114: ...successfully read the data from he device by an IN operation Otherwise when this bit is cleared to 0 the SIE will update the device address immediately after an address is written to the AWR register So in order to work properly the firmware has to clear this bit after a next valid SETUP token is received MISC Register Bit 7 6 5 4 3 2 1 0 Name LEN0 READY SETCMD CLEAR TX REQUEST R W R R R W R W R W...

Page 115: ...it 7 6 5 4 3 2 1 0 Name SETO2 SETO1 SETI2 SETI1 DATATG R W R W R W R W R W R W POR 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 SETO2 EP2 output FIFO control bit 0 disable 1 enable Bit 5 SETO1 EP1 output FIFO control bit 0 disable 1 enable Bit 4 3 Unimplemented read as 0 Bit 2 SETI2 EP2 input FIFO control bit 0 disable 1 enable Bit 1 SETI1 EP1 input FIFO control bit 0 disable 1 enable Bit 0 DATAT...

Page 116: ...68FB240 USB Low Speed Flash MCU Application Circuits VDD UBUS VSS 100KΩ RES OCDSCK VDD V33O UDN UDP 300Ω 0 1µF HT68FB240 VBUS D D VSS 0 1µF 0 1µF Key Matrix Input 10µF PA0 OCDSDA I O ICP OCDS Interface VDD RES OCDSCK VSS UDN ICP OCDS ...

Page 117: ...le to implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instructions would be CLR PCL or MOV PCL A For the case of skip instructions it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle if no skip is involved then only one cyc...

Page 118: ...structions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual bits Depending upon the conditions the program will continue with the next instruction or skip over it and jump to the following instruction These instructions are the key to decision making and branching within the program perhaps determined by the condition of cert...

Page 119: ... Z C AC OV DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Memory to ACC 1 Z XOR A m Logical XOR Data Memory to ACC 1 Z ANDM A m Logical AND ACC to Data Memory 1Note Z ORM A m Logical OR ACC to Data Memory 1Note Z XORM A m Logical XOR ACC to Data Memory 1Note Z AND A x Logical AND immediate D...

Page 120: ...tine 2 None RET A x Return from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read TABRD m Read table to TBLH and Data Memory 2Note None TABRDL m Read table last page to TBLH and Data Memory 2Note None Miscellaneous NOP No operation 1 None CLR m Clear Data Memory 1Note None SET m Set Data Memory 1Note None CLR WDT Clear Watchdog Timer 1 TO PDF CLR WDT1 Pr...

Page 121: ... and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C AND A m Logical AND Data Memory to ACC Description Data in t...

Page 122: ...F flags and the WDT are all cleared Operation WDT cleared TO 0 PDF 0 Affected flag s TO PDF CLR WDT1 Pre clear Watchdog Timer Description The TO PDF flags and the WDT are all cleared Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect Repetitively executing this instruction without alternately executing CLR WDT2 will have no e...

Page 123: ... instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Operation m ACC 00H or m ACC 06H or m ACC 60H or m ACC 66H Affected flag s C DEC m Decrement Data Memory Description Data in the specified Data Memory is decremented by 1 Operation m m 1 Affected flag s Z DECA m Decrement Data Memory with result in ACC Description Data in the...

Page 124: ...CC Affected flag s None NOP No operation Description No operation is performed Execution continues with the next instruction Operation No operation Affected flag s None OR A m Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation The result is stored in the Accumulator Operation ACC ACC OR m Affected flag s Z OR A x L...

Page 125: ...mory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6 ACC 0 m 7 Affected flag s None RLC m Rotate Data Memory left through Carry Description The contents of the specified Data Memory and...

Page 126: ...m Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator The result is stored in the Accumulator Note that if the result of subtraction is negative the C flag will be cleared to 0 otherwise if the result is positive or zero the C flag will be set to 1 Operation ACC ACC m C Affected flag...

Page 127: ...ogram proceeds with the following instruction Operation m m 1 Skip if m 0 Affected flag s None SIZA m Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1 If the result is 0 the following instruction is skipped The result is stored in the Accumulator but the specified Data Memory contents remain unchanged As this ...

Page 128: ...nterchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s None SZ m Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetched it is a...

Page 129: ... TBLH Operation m program code low byte TBLH program code high byte Affected flag s None XOR A m Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation The result is stored in the Accumulator Operation ACC ACC XOR m Affected flag s Z XORM A m Logical XOR ACC to Data Memory Description Data in the specified Data Memor...

Page 130: ... intervals users are reminded to consult the Holtek website for the latest version of the Package Carton Information Additional supplementary information with regard to packaging is listed below Click on the relevant section to be transferred to the relevant website page Further Package Information include Outline Dimensions Product Tape and Reel Specifications Packing Meterials Information Carton...

Page 131: ... Symbol Dimensions in mm Min Nom Max A 0 80 0 85 0 90 A1 0 00 0 02 0 04 A3 0 20 b 0 15 0 20 0 25 D 6 45 6 50 6 55 E 4 45 4 50 4 55 e 0 40 D2 5 00 5 10 5 20 E2 3 00 3 10 3 20 L 0 30 0 40 0 50 Package Information 1 May 12 2011 Symbol Dimensions in inch Min Nom Max A 0 031 0 033 0 035 A1 0 000 0 001 0 002 A3 0 08 REF b 0 006 0 008 0 010 D 0 254 0 256 0 258 E 0 175 0 177 0 179 e 0 016 BSC D2 0 197 0 2...

Page 132: ... A 0 354 BSC B 0 276 BSC C 0 354 BSC D 0 276 BSC E 0 020 BSC F 0 007 0 009 0 011 G 0 053 0 055 0 057 H 0 063 I 0 002 0 006 J 0 018 0 024 0 030 K 0 004 0 008 α 0 7 Symbol Dimensions in mm Min Nom Max A 9 00 BSC B 7 00 BSC C 9 00 BSC D 7 00 BSC E 0 50 BSC F 0 17 0 22 0 27 G 1 35 1 40 1 45 H 1 60 I 0 05 0 15 J 0 45 0 60 0 75 K 0 09 0 20 α 0 7 ...

Page 133: ... solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or systems Holtek reserves ...

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