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Rev. 2.50

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Rev. 2.50

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HT66F20/HT66F30/HT66F40/HT66F50/HT66F60

HT66FU30/HT66FU40/HT66FU50/HT66FU60

A/D Flash MCU with EEPROM

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60

HT66FU30/HT66FU40/HT66FU50/HT66FU60

A/D Flash MCU with EEPROM

Co�nter Val�e

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TM O/P Pin

(TnOC=�)

Time

Co�nter cleared

by CCRA

Pa�se Res�me

Co�nter Stop if

TnON bit low

Co�nter Reset when

TnON ret�rns high

TnDPX = �; TnM [�:0] = �0

PWM D�ty Cycle

set by CCRP

PWM res�mes

operation

O�tp�t controlled by

other pin-shared f�nction

O�tp�t Inverts

when TnPOL = �

PWM Period

set by CCRA

TM O/P Pin

(TnOC=0)

PWM Mode – TnDPX=1

Note: 1. Here TnDPX=1 -- Counter cleared by CCRA

2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when TnIO [1:0]=00 or 01
4. The TnCCLR bit has no influence on PWM operation

Summary of Contents for HT66F30

Page 1: ...A D Flash MCU with EEPROM HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 HT66FU30 HT66FU40 HT66FU50 HT66FU60 Revision V2 50 Date June 22 2017...

Page 2: ...Comparator Electrical Characteristics 26 Power on Reset Characteristics 26 System Architecture 27 Clocking and Pipelining 27 Program Counter 28 Stack 29 Arithmetic and Logic Unit ALU 29 Flash Program...

Page 3: ...tor HIRC 53 External 32 768kHz Crystal Oscillator LXT 54 Internal Low Speed Oscillator LIRC 55 Supplementary Oscillators 55 Operating Modes and System Clocks 56 System Clock 56 System Operation Modes...

Page 4: ...Type TM Register Description 124 Standard Type TM Operating Modes 133 Enhanced Type TM ETM 144 Enhanced TM Operation 145 Enhanced Type TM Register Description 145 Enhanced Type TM Operating Modes 152...

Page 5: ...CD 228 LCD Operation 228 LCD Bias Control 229 Configuration Options 231 Application Circuits 232 UART Module Serial Interface 233 UART Module Features 233 UART Module Overview 233 UART Module Block Di...

Page 6: ...tline Dimensions 275 16 pin SSOP 150mil Outline Dimensions 276 20 pin DIP 300mil Outline Dimensions 277 20 pin SOP 300mil Outline Dimensions 279 20 pin SSOP 150mil Outline Dimensions 280 24 pin SKDIP...

Page 7: ...ower down and wake up functions to reduce power consumption Five oscillators External Crystal HXT External 32 768kHz Crystal LXT External RC ERC Internal RC HIRC Internal 32kHz RC LIRC Multi mode oper...

Page 8: ...compare match output PWM output or single pulse output function Serial Interfaces Module SIM for SPI or I2 C Dual Comparator functions Dual Time Base functions for generation of fixed time interrupt...

Page 9: ...tures such as an internalWatchdog Timer Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile elec...

Page 10: ...OP 20DIP SOP SSOP 24SOP SSOP HT66FU30 14 24SOP HT66F40 2 2V 5 5V 4k 15 192 8 128 8 42 2 12 bit 8 10 bit CTM 1 10 bit ETM 1 16 bit STM 1 8 24 28SKDIP SOP SSOP 44LQFP 32 40QFN 48SSOP QFN HT66FU40 34 40Q...

Page 11: ...Rev 2 50 11 June 22 2017 HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 HT66FU30 HT66FU40 HT66FU50 HT66FU60 A D Flash MCU with EEPROM Block Diagram...

Page 12: ...MCU with EEPROM Pin Assignment Note 1 Bracketed pin names indicate non default pinout remapping locations 2 If the pin shared pin functions have multiple outputs simultaneously its pin names at the r...

Page 13: ...D Flash MCU with EEPROM Note 1 Bracketed pin names indicate non default pinout remapping locations 2 If the pin shared pin functions have multiple outputs simultaneously its pin names at the right sid...

Page 14: ...D Flash MCU with EEPROM Note 1 Bracketed pin names indicate non default pinout remapping locations 2 If the pin shared pin functions have multiple outputs simultaneously its pin names at the right sid...

Page 15: ...D Flash MCU with EEPROM Note 1 Bracketed pin names indicate non default pinout remapping locations 2 If the pin shared pin functions have multiple outputs simultaneously its pin names at the right sid...

Page 16: ...5 Port B PBPU ST CMOS PC0 PC3 Port C PCPU ST CMOS AN0 AN7 ADC input ACERL AN PA0 PA7 VREF ADC reference input ADCR1 AN PB5 C0 C1 Comparator 0 1 input CP0C CP1C AN PA3 PC3 C0 C1 Comparator 0 1 input AN...

Page 17: ...PC2 C0X C1X Comparator 0 1 output CMOS PA0 PA5 TCK0 TCK1 TM0 TM1 input ST PA2 PA4 TP0_0 TP0_1 TM0 I O TMPC0 ST CMOS PA0 PC5 TP1A TM1 I O TMPC0 ST CMOS PA1 TP1B_0 TP1B_1 TM1 I O TMPC0 ST CMOS PC0 PC1...

Page 18: ...Comparator 0 1 input CP0C CP1C AN PA3 PC3 C0 C1 Comparator 0 1 input CP0C CP1C AN PA2 PC2 C0X C1X Comparator 0 1 output CP0C CP1C PRM0 CMOS PA0 PA5 or PF0 PF1 TCK0 TCK2 TM0 TM2 input PRM1 ST PA2 PA4...

Page 19: ...s not all of the above listed pins may be present on package types with smaller numbers of pins HT66F50 Pin Name Function OP I T O T Pin Shared Mapping PA0 PA7 Port A PAWU PAPU ST CMOS PB0 PB7 Port B...

Page 20: ...input CO ST PB0 VDD Power supply PWR AVDD ADC power supply PWR VSS Ground PWR AVSS ADC ground PWR Note I T Input type O T Output type OP Optional by configuration option CO or register option PWR Pow...

Page 21: ...C0 PRM2 ST CMOS PA0 PC5 or PC6 PD5 TP1A TM1 I O TMPC0 PRM2 ST CMOS PA1 or PC7 TP1B_0 TP1B_2 TM1 I O TMPC0 PRM2 ST CMOS PC0 PC1 PC5 or PE4 TP2_0 TP2_1 TM2 I O TMPC1 PRM2 ST CMOS PC3 PC4 or PD1 PD4 TP3_...

Page 22: ...VDD VSS is the device ground pin while AVSS is the ADC ground pin The AVSS pin is bonded together internally with VSS As the Pin Description Summary table applies to the package type with the most pin...

Page 23: ...ent HXT ERC HIRC 3V No load ADC off WDT enable fSYS 12MHz on 0 55 0 83 mA 5V 1 30 2 00 mA ISLEEP0 SLEEP0 Mode Standby Current LXT and LIRC off 3V No load ADC off WDT disable 1 A 5V 2 A ISLEEP1 SLEEP1...

Page 24: ...Test Conditions Min Typ Max Unit VDD Conditions fCPU Operating Clock 2 2V 5 5V DC 8 MHz 2 7V 5 5V DC 12 MHz 4 5V 5 5V DC 20 MHz fSYS System Clock HXT 2 2V 5 5V 0 4 8 MHz 2 7V 5 5V 0 4 12 MHz 4 5V 5 5...

Page 25: ...r fERC as the resistor tolerance will influence the frequency a precision resistor is recommended 3 To maintain the accuracy of the internal HIRC oscillator frequency a 0 1 F decoupling capacitor shou...

Page 26: ...h 20 40 60 mV VCM Comparator Common Mode Voltage Range VSS VDD 1 4V V AOL Comparator Open Loop Gain 60 80 dB tPD Comparator Response Time With 100mV overdrive Note 370 560 ns Note Measured with compar...

Page 27: ...dressed The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I O and A D contr...

Page 28: ...quiring jumps to non consecutive addresses such as a jump instruction a subroutine call interrupt or reset etc the microcontroller manages program control by loading the required address into the Prog...

Page 29: ...ubroutine instruction can still be executed which will result in a stack overflow Precautions should be taken to avoid such cases which might cause unpredictable program branching If the stack is over...

Page 30: ...bits The Program Memory is addressed by the Program Counter and also contains data table information and interrupt entries Table data which can be setup in any location within the Program Memory is a...

Page 31: ...er register TBLP and TBHP These registers define the total address of the look up table After setting up the table pointer the table data can be retrieved from the Program Memory using the TABRD m or...

Page 32: ...both the main routine and Interrupt Service Routine use table read instructions If using the table read instructions the Interrupt Service Routines may change the value of the TBLH and subsequently ca...

Page 33: ...ogram Memory and EEPROM data memory can both be programmed serially in circuit using this 5 wire interface Data is downloaded and uploaded serially on a single pin with an additional line for the cloc...

Page 34: ...he General Purpose Data Memory which is reserved for general purpose use All locations within this area are read and write accessible under program control The overall Data Memory is subdivided into s...

Page 35: ...Rev 2 50 35 June 22 2017 HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 HT66FU30 HT66FU40 HT66FU50 HT66FU60 A D Flash MCU with EEPROM HT66F20 Special Purpose Data Memory HT66F30 Special Purpose Data Memory...

Page 36: ...Rev 2 50 36 June 22 2017 HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 HT66FU30 HT66FU40 HT66FU50 HT66FU60 A D Flash MCU with EEPROM HT66F40 Special Purpose Data Memory HT66F50 Special Purpose Data Memory...

Page 37: ...Rev 2 50 37 June 22 2017 HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 HT66FU30 HT66FU40 HT66FU50 HT66FU60 A D Flash MCU with EEPROM HT66F60 Special Purpose Data Memory...

Page 38: ...dressing Registers are not physically implemented reading the Indirect Addressing Registers indirectly will return a result of 00H and writing to the registers indirectly will result in no operation M...

Page 39: ...lecting the required Program and Data Memory area is achieved using the Bank Pointer Bit 5 of the Bank Pointer is used to select Program Memory Bank 0 or 1 while bits 0 2 are used to select Data Memor...

Page 40: ...R W POR 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 DMBP1 DMBP0 Select Data Memory Banks 00 Bank 0 01 Bank 1 10 Bank 2 11 Undefined HT66F60 Bit 7 6 5 4 3 2 1 0 Name PMBP0 DMBP2 DMBP1 DMBP0 R W R W R...

Page 41: ...of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory By manipulating this register direct jumps to other program locations are eas...

Page 42: ...y reflect the status of the latest operations C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation otherwise C is...

Page 43: ...ion Bit 3 OV Overflow flag 0 No overflow 1 An operation results in a carry into the highest order bit but not a carry out of the highest order bit or vice versa Bit 2 Z Zero flag 0 The result of an ar...

Page 44: ...M Data Memory the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory Read and Write operations to the EE...

Page 45: ...EA D5 D4 D3 D2 D1 D0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC WREN WR RDEN RD HT66F40 Name Bit 7 6 5 4 3 2 1 0 EEA D6 D5 D4 D3 D2 D1 D0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC WREN WR RDEN RD HT66F50 HT66F60 Name Bit...

Page 46: ...ted read as 0 Bit 5 0 Data EEPROM address Data EEPROM address bit 5 bit 0 HT66F40 Bit 7 6 5 4 3 2 1 0 Name D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W POR x unknown Bit 7 Unimplemented read a...

Page 47: ...automatically reset to zero by the hardware after the write cycle has finished Setting this bit high will have no effect if the WREN has not first been set high Bit 1 RDEN Data EEPROM Read Enable 0 Di...

Page 48: ...n written into the EEPROM Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt When the write cycle terminat...

Page 49: ...e that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete Otherwise the EEPROM read or write operation will fail Programming Examples Readi...

Page 50: ...has the flexibility to optimize the performance power ratio a feature especially important in power sensitive portable applications Type Name Freq Pins External Crystal HXT 400kHz 20MHz OSC1 OSC2 Exte...

Page 51: ...Rev 2 50 51 June 22 2017 HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 HT66FU30 HT66FU40 HT66FU50 HT66FU60 A D Flash MCU with EEPROM...

Page 52: ...y be necessary to add two small value capacitors C1 and C2 Using a ceramic resonator will usually require two small value capacitors C1 and C2 to be connected as shown for oscillation to occur The val...

Page 53: ...he oscillator will have a frequency of 8MHz within a tolerance of 2 Here only the OSC1 pin is used which is shared with I O pin PB1 leaving pin PB2 free for use as a normal I O pin For oscillator stab...

Page 54: ...ers operational even when the microcontroller is in the SLEEP or IDLE Mode To do this another clock independent of the system clock must be provided However for some crystals to ensure oscillation and...

Page 55: ...t the application program sets the LXTLP bit high about 2 seconds after power on It should be noted that no matter what condition the LXTLP bit is set to the LXT oscillator will always function normal...

Page 56: ...ming a clock system can be configured to obtain maximum application performance The main system clock can come from either a high frequency fH or low frequency fL source and is selected using the HLCL...

Page 57: ...66FU30 HT66FU40 HT66FU50 HT66FU60 A D Flash MCU with EEPROM System Clock Configurations Note When the system clock source fSYS is switched to fL from fH the high speed oscillation will stop to conserv...

Page 58: ...e HXT ERC or HIRC oscillators The high speed oscillator will however first be divided by a ratio ranging from 1 to 64 the actual ratio being selected by the CKS2 CKS0 and HLCLK bits in the SMOD regist...

Page 59: ...r TMs and SIM In the IDLE1 Mode the system oscillator will continue to run and this system oscillator may be high speed or low speed system oscillator In the IDLE1 Mode the Watchdog Timer clock fS wil...

Page 60: ...er on The flag will be low when in the SLEEP or IDLE0 Mode but after a wake up has occurred the flag will change to a high level after 1024 clock cycles if the HXT oscillator is used and after 15 16 c...

Page 61: ...ed then it will take one to two tSUB clock cycles of the LIRC or LXT oscillator for the system to wake up The system will then initially run under the fSUB clock source until 1024 HXT clock cycles hav...

Page 62: ...e Mode Switching from the NORMAL SLOW Modes to the SLEEP IDLE Modes is executed via the HALT instruction When a HALT instruction is executed whether the device enters the IDLE Mode or the SLEEP Mode i...

Page 63: ...W Mode by set the HLCLK bit to 0 and set the CKS2 CKS0 bits to 000 or 001 in the SMOD register This will then use the low speed system oscillator which will consume less power Users may decide to do t...

Page 64: ...To switch back to the NORMAL Mode where the high speed system oscillator is used the HLCLK bit should be set to 1 or HLCLK bit is 0 but CKS2 CKS0 is set to 010 011 100 101 110 or 111 As a certain amou...

Page 65: ...ock and Time Base clock will be stopped and the application program will stop at the HALT instruction but the WDT or LVD will remain with the clock source coming from the fSUB clock The Data Memory co...

Page 66: ...t consumption of the device to as low a value as possible perhaps only in the order of several micro amps except in the IDLE1 Mode there are other considerations which must also be taken into account...

Page 67: ...n the interrupt which woke up the device will not be immediately serviced but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free The other s...

Page 68: ...process variations The LXT oscillator is supplied by an external 32 768kHz crystal The other Watchdog Timer clock source option is the fSYS 4 clock The Watchdog Timer clock source can originate from i...

Page 69: ...able Control Under normal program operation a Watchdog Timer time out will initialise a device reset and set the status bit TO However if the system is in the SLEEP or IDLE Mode when a Watchdog Timer...

Page 70: ...rocontroller is already running the RES line is forcefully pulled low In such a case known as a normal operation reset some of the microcontroller registers remain unchanged allowing the microcontroll...

Page 71: ...crocontroller will begin normal operation The abbreviation SST in the figures stands for System Start up Timer For most applications a resistor connected between VDD and the RES pin and a capacitor co...

Page 72: ...ill automatically reset the device internally The LVR includes the following specifications For a valid LVR signal a low voltage i e a voltage in the range between 0 9V VLVR must exist for greater tha...

Page 73: ...l affect the internal registers of the microcontroller in different ways To ensure reliable continuation of normal program execution after a reset occurs it is important to know what condition the mic...

Page 74: ...111 1111 1111 uuuu uuuu CP0C 1000 0 1 1000 0 1 1000 0 1 uuuu u u CP1C 1000 0 1 1000 0 1 1000 0 1 uuuu u u SIMC0 111 0 0 0 0 111 0 0 0 0 111 0 0 0 0 uuuu uuu SIMC1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0...

Page 75: ...0 0 0 0 0 uuuu uuuu PAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1...

Page 76: ...u TMPC0 1 01 01 1 01 01 1 01 01 u uu uu PRM0 000 000 000 uuu TM1C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TM1C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TM1C2 0 0 0...

Page 77: ...uu MFI1 000 000 000 000 000 000 uuu uuu MFI2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 78: ...MPC0 1001 01 1001 01 1001 01 uuuu uu TMPC1 01 01 01 uu PRM0 0 0 0000 0 0 0000 0 0 0000 u u uuuu PRM1 000 0000 000 0000 000 0000 uuu uuuu PRM2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uu uuuu TM1C0 0 0 0 0...

Page 79: ...0 0 0 0 uuuu uuuu MFI1 000 000 000 000 000 000 uuu uuu MFI2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu MFI3 0 0 0 0 0 0 0 0 0 0 0 0 uu uu PAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 80: ...0 0000 uuu uuuu PRM2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TM1C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TM1C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuu...

Page 81: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu MFI1 000 000 000 000 000 000 uuu uuu MFI2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu MFI3 0 0 0 0 0 0 0 0 0 0 0 0 uu uu PAWU 0 0 0 0 0 0 0 0 0...

Page 82: ...0 0 0 0 0 0 0 0 uuuu uuuu PRM1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PRM2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TM1C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 83: ...ts can be used for input and output operations For input operation these ports are non latching which means the inputs must be ready at the T2 rising edge of instruction MOV A m where m denotes the po...

Page 84: ...D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PBPU D7 D6 D5 D4 D3 D2 D1 D0 PB D7 D6 D5 D4 D3 D2 D1 D0 PBC D7 D6 D5 D4 D3 D2 D1 D0 PCPU D7 D6 D5 D4 D3 D2 D1 D0 PC D7 D6 D5 D4 D3 D2 D1 D...

Page 85: ...D4 D3 D2 D1 D0 PBPU D7 D6 D5 D4 D3 D2 D1 D0 PB D7 D6 D5 D4 D3 D2 D1 D0 PBC D7 D6 D5 D4 D3 D2 D1 D0 PCPU D7 D6 D5 D4 D3 D2 D1 D0 PC D7 D6 D5 D4 D3 D2 D1 D0 PCC D7 D6 D5 D4 D3 D2 D1 D0 PDPU D7 D6 D5 D4...

Page 86: ...sing weak PMOS transistors PAPU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 PBPU Register HT66F40 HT66F50 HT66F60 Bit 7 6 5 4 3 2...

Page 87: ...6 5 4 3 2 1 0 Name D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 0 PBPU Port B bit 5 bit 0 Pull High Control 0 Disable 1 Enable PCPU Register HT66...

Page 88: ...R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 PAWU Port A bit 7 bit 0 Wake up Control 0 Disable 1 Enable I O Port Control Registers Each I O port has its own control register known as PAC PGC to control the...

Page 89: ...D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 1 1 1 1 1 1 1 1 PDC Register HT66F40 HT66F50 HT66F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 1 1...

Page 90: ...PCC Register HT66F20 Bit 7 6 5 4 3 2 1 0 Name D3 D2 D1 D0 R W R W R W R W R W POR 1 1 1 1 Bit 7 4 Unimplemented read as 0 Bit 3 0 PCC Port C bit 3 bit 0 Input Output Control 0 Output 1 Input PFC Regis...

Page 91: ...vice can contain However by allowing the same pins to share several different functions and providing a means of function selection a wide range of different functions can be incorporated into even re...

Page 92: ...gister HT66F40 HT66F50 Bit 7 6 5 4 3 2 1 0 Name C1XPS0 C0XPS0 PDPRM SIMPS1 SIMPS0 PCKPS R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 C1XPS0 C1X Pin Remapping Control...

Page 93: ...rol 00 C0X on PA0 01 C0X on PF0 10 C0X on PG0 11 Undefined Bit 3 PDPRM PD3 PD0 pin shared function Pin Remapping Control 0 No change 1 TCK2 on PD0 change to PB6 TP2_0 on PD1 change to PB7 TCK0 on PD2...

Page 94: ...OR 0 0 0 0 0 0 0 Bit 7 TCK2PS TCK2 Pin Remapping Control 0 TCK2 on PC2 1 TCK2 on PD0 Bit 6 TCK1PS TCK1 Pin Remapping Control 0 TCK1 on PA4 1 TCK1 on PD3 Bit 5 TCK0PS TCK0 Pin Remapping Control 0 TCK0...

Page 95: ...t 7 TCK2PS TCK2 Pin Remapping Control 0 TCK2 on PC2 1 TCK2 on PD0 Bit 6 TCK1PS TCK1 Pin Remapping Control 0 TCK1 on PA4 1 TCK1 on PD3 Bit 5 TCK0PS TCK0 Pin Remapping Control 0 TCK0 on PA2 1 TCK0 on PD...

Page 96: ...Bit 7 6 Unimplemented read as 0 Bit 5 TP21PS TP2_1 Pin Remapping Control 0 TP2_1 on PC4 1 TP2_1 on PD4 Bit 4 TP20PS TP2_0 Pin Remapping Control 0 TP2_0 on PC3 1 TP2_0 on PD1 Bit 3 TP1B2PS TP1B_2 Pin...

Page 97: ...rol 0 TP3_1 on PD0 1 TP3_1 on PE3 Bit 6 TP30PS TP3_0 Pin Remapping Control 0 TP3_0 on PD3 1 TP3_0 on PE5 Bit 5 TP21PS TP2_1 Pin Remapping Control 0 TP2_1 on PC4 1 TP2_1 on PD4 Bit 4 TP20PS TP2_0 Pin R...

Page 98: ...lustrate the internal structures of some generic I O pin types As the exact logical construction of the I O pin will differ from these drawings they are supplied as a guide only to assist with the fun...

Page 99: ...r Modules TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time To implement time related functions each device includes several Timer Modul...

Page 100: ...ps also change the condition of the TM output pin The internal TM counter is driven by a user selectable clock source which can be an internal clock or an external pin TM Clock Source The clock source...

Page 101: ...ccurs The external TPn output pin is also the pin where the TM generates the PWM output waveform As the TM output pins are pin shared with other function the TM output function must first be setup usi...

Page 102: ...pin as a TM input output if reset to zero the pin will retain its original other function Registers Device Bit 7 6 5 4 3 2 1 0 TMPC0 HT66F20 T1CP1 T1CP0 T0CP0 TMPC0 HT66F30 T1ACP0 T1BCP1 T1BCP0 T0CP1...

Page 103: ...P 0 P A 0 O u t p u t F u n c t i o n 0 1 P A 0 1 0 P A 0 T P 0 _ 0 T 0 C P 0 P C 1 O u t p u t F u n c t i o n 0 1 P C 1 1 0 C C R B O u t p u t C C R B C a p t u r e I n p u t P A 4 T C K 1 T C K I...

Page 104: ...A 0 T P 0 _ 0 T 0 C P 0 P C 4 O u t p u t F u n c t i o n 0 1 P C 4 1 0 O u t p u t C a p t u r e I n p u t P C 2 T C K 2 T C K I n p u t 1 0 P C 4 T P 2 _ 1 T 2 C P 1 T 2 C P 1 P C 3 O u t p u t F u...

Page 105: ...u t C C R B C a p t u r e I n p u t P A 4 T C K 1 T C K I n p u t 1 0 P C 5 T P 1 B _ 2 T 1 B C P 2 T 1 B C P 2 P C 1 O u t p u t F u n c t i o n 0 1 P C 1 1 0 1 0 P C 1 T P 1 B _ 1 T 1 B C P 1 T 1 B...

Page 106: ...u t P C 2 T C K 2 T C K I n p u t 1 0 P C 4 T P 2 _ 1 T 2 C P 1 T 2 C P 1 P C 3 O u t p u t F u n c t i o n 0 1 P C 3 1 0 1 0 P C 3 T P 2 _ 0 T 2 C P 0 T 2 C P 0 T C K I n p u t P C 4 T C K 3 P D 0 O...

Page 107: ...C R B C a p t u r e I n p u t P A 4 T C K 1 T C K I n p u t 1 0 P C 5 T P 1 B _ 2 T 1 B C P 2 T 1 B C P 2 P C 1 O u t p u t F u n c t i o n 0 1 P C 1 1 0 1 0 P C 1 T P 1 B _ 1 T 1 B C P 1 T 1 B C P 1...

Page 108: ...Control 0 Disable 1 Enable Bit 3 1 Unimplemented read as 0 Bit 0 T0CP0 TP0_0 pin Control 0 Disable 1 Enable HT66F30 Bit 7 6 5 4 3 2 1 0 Name T1ACP0 T1BCP1 T1BCP0 T0CP1 T0CP0 R W R W R W R W R W R W PO...

Page 109: ...1 T1BCP0 T0CP1 T0CP0 R W R W R W R W R W R W R W POR 1 0 0 1 0 1 Bit 7 T1ACP0 TP1A pin Control 0 Disable 1 Enable Bit 6 T1BCP2 TP1B_2 pin Control 0 Disable 1 Enable Bit 5 T1BCP1 TP1B_1 pin Control 0 D...

Page 110: ...2CP1 TP2_1 pin Control 0 Disable 1 Enable Bit 0 T2CP0 TP2_0 pin Control 0 Disable 1 Enable HT66F50 HT66F60 Bit 7 6 5 4 3 2 1 0 Name T3CP1 T3CP0 T2CP1 T2CP0 R W R W R W R W R W POR 0 1 0 1 Bit 7 6 Unim...

Page 111: ...lowing diagram and accessing these register pairs is carried out in a specific way as described above it is recommended to use the MOV instruction to access the CCRA and CCRB low byte registers named...

Page 112: ...bit count up counter which is driven by a user selectable internal or external clock source There are also two internal comparators with the names Comparator A and Comparator P These comparators will...

Page 113: ...DL D7 D6 D5 D4 D3 D2 D1 D0 TMnDH D9 D8 TMnAL D7 D6 D5 D4 D3 D2 D1 D0 TMnAH D9 D8 Compact TM Register List n 0 or 3 TMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R R R R R R R R P...

Page 114: ...trols the overall on off function of the TM Setting the bit high enables the counter to run clearing the bit disables the TM Clearing this bit to zero will stop the counter from counting and turn off...

Page 115: ...pon in which mode the TM is running In the Compare Match Output Mode the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A The TM out...

Page 116: ...high the TM output pin will be inverted and not inverted when the bit is zero It has no effect if the TM is in the Timer Counter Mode Bit 1 TnDPX TMn PWM period duty Control 0 CCRP period CCRA duty 1...

Page 117: ...o the counter will overflow when its reaches its maximum 10 bit 3FF Hex value however here the TnAF interrupt request flag will not be generated As the name of the mode suggests after a comparison is...

Page 118: ...pin set to initial Level Low if TnOC 0 O tp t Toggle with TnAF flag Note TnIO 0 0 Active High O tp t select Here TnIO 0 Toggle O tp t select O tp t not affected by TnAF flag Remains High ntil reset b...

Page 119: ...lag Note TnIO 0 0 Active High O tp t select Here TnIO 0 Toggle O tp t select O tp t not affected by TnAF flag Remains High ntil reset by TnON bit O tp t Pin Reset to Initial val e O tp t controlled by...

Page 120: ...X bit in the TMnC1 register The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers An interrupt flag one for each of the CCRA and CCRP will...

Page 121: ...e Co nter Stop if TnON bit low Co nter Reset when TnON ret rns high TnDPX 0 TnM 0 0 PWM D ty Cycle set by CCRA PWM res mes operation O tp t controlled by other pin shared f nction O tp t Inverts when...

Page 122: ...me Co nter Stop if TnON bit low Co nter Reset when TnON ret rns high TnDPX TnM 0 0 PWM D ty Cycle set by CCRP PWM res mes operation O tp t controlled by other pin shared f nction O tp t Inverts when T...

Page 123: ...selectable internal or external clock source There are also two internal comparators with the names Comparator A and Comparator P These comparators will compare the value in the counter with CCRP and...

Page 124: ...rent operating and control modes as well as the three or eight CCRP bits Register Name Bit 7 6 5 4 3 2 1 0 TM1C0 T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 TM1C1 T1M1 T1M0 T1IO1 T1IO0 T1OC T1POL T...

Page 125: ...is bit controls the overall on off function of the TM Setting the bit high enables the counter to run clearing the bit disables the TM Clearing this bit to zero will stop the counter from counting and...

Page 126: ...are used to determine how the TM output pin changes state when a certain condition is reached The function that these bits select depends upon in which mode the TM is running In the Compare Match Out...

Page 127: ...t is set high the TM output pin will be inverted and not inverted when the bit is zero It has no effect if the TM is in the Timer Counter Mode Bit 1 T1DPX TM1 PWM period duty Control 0 CCRP period CCR...

Page 128: ...6 5 4 3 2 1 0 Name D9 D8 R W R R POR 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 TM1DH TM1 Counter High Byte Register bit 1 bit 0 TM1 10 bit Counter bit 9 bit 8 TM1AL Register 10 bit STM Bit 7 6 5 4 3...

Page 129: ...used to select the clock source for the TM Selecting the Reserved clock input will effectively disable the internal counter The external pin clock source can be chosen to be active on the rising or fa...

Page 130: ...are used to determine how the TM output pin changes state when a certain condition is reached The function that these bits select depends upon in which mode the TM is running In the Compare Match Out...

Page 131: ...it is set high the TM output pin will be inverted and not inverted when the bit is zero It has no effect if the TM is in the Timer Counter Mode Bit 1 T2DPX TM2 PWM period duty Control 0 CCRP period CC...

Page 132: ...W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 TM2AH TM2 CCRA High Byte Register bit 7 bit 0 TM2 16 bit CCRA bit 15 bit 8 TM2RP Register 16 bit STM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D...

Page 133: ...TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A However here only the TnAF interrupt request flag will be generated even if the value of the CCRP...

Page 134: ...IO0 11 Toggle Output Select Now TnIO1 TnIO0 10 Active High Output Select Output not affected by TnAF flag Remains High until reset by TnON bit TnCCLR 0 TnM 1 0 00 TnPAU bit Resume Stop Time CCRP 0 CCR...

Page 135: ...elect Now TnIO1 TnIO0 10 Active High Output Select TnPAU bit Resume Stop Time TnPF not generated No TnAF flag generated on CCRA overflow Output does not change CCRA 0 Output inverts when TnPOL is high...

Page 136: ...be controlled the choice of generated waveform is extremely flexible In the PWM mode the TnCCLR bit has no effect as the PWM period Both of the CCRAand CCRP registers are used to generate the PWM wav...

Page 137: ...it STM PWM Mode Edge aligned Mode TnDPX 0 CCRP 1 255 0 Period CCRP 256 65536 Duty CCRA If fSYS 16MHz TM clock source is fSYS 4 CCRP 2 and CCRA 128 The STM PWM output frequency fSYS 4 2 256 fSYS 2048 7...

Page 138: ...nter Stop if TnON bit low Co nter Reset when TnON ret rns high TnDPX 0 TnM 0 0 PWM D ty Cycle set by CCRA PWM res mes operation O tp t controlled by other pin shared f nction O tp t Inverts when TnPO...

Page 139: ...o nter Stop if TnON bit low Co nter Reset when TnON ret rns high TnDPX TnM 0 0 PWM D ty Cycle set by CCRP PWM res mes operation O tp t controlled by other pin shared f nction O tp t Inverts when TnPOL...

Page 140: ...e the Single Pulse output When the TnON bit transitions to a high level the counter will start running and the pulse leading edge will be generated The TnON bit should remain high when the pulse is in...

Page 141: ...nIO 1 0 11 Pulse Width set by CCRA Output Inverts when TnPOL 1 No CCRP Interrupts generated TM O P Pin TnOC 0 TCKn pin Software Trigger Cleared by CCRA match TCKn pin Trigger Auto set by TCKn pin Soft...

Page 142: ...ed Irrespective of what events occur on the TPn_0 or TPn_1 pin the counter will continue to free run until the TnON bit changes from high to low When a CCRP compare match occurs the counter will reset...

Page 143: ...apt re Pin TPn_x YY TnIO 0 Val e 00 Rising edge 0 Falling edge Disable Capt re Active edge Active edge XX 0 Both edges edge YY TnM 0 0 Active Capture Input Mode Note 1 TnM 1 0 01 and active edge set b...

Page 144: ...pture Input Single Pulse Output and PWM Output modes The Enhanced TM can also be controlled with an external input pin and can drive three or four external output pins ETM Name TM No TM Input Pin TM O...

Page 145: ...these conditions occur a TM interrupt signal will also usually be generated The Enhanced Type TM can operate in a number of different operational modes can be driven by different clock sources includ...

Page 146: ...Off 1 On This bit controls the overall on off function of the TM Setting the bit high enables the counter to run clearing the bit disables the TM Clearing this bit to zero will stop the counter from...

Page 147: ...determine how the TM output pin changes state when a certain condition is reached The function that these bits select depends upon in which mode the TM is running In the Compare Match Output Mode the...

Page 148: ...larity of the TP1A output pin When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero It has no effect if the TM is in the Timer Counter Mode Bit 1 T1CDN TM1...

Page 149: ...nused These two bits are used to determine how the TM output pin changes state when a certain condition is reached The function that these bits select depends upon in which mode the TM is running In t...

Page 150: ...he Timer Counter Mode In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs In the PWM Mode it determines if the PWM signal is active high o...

Page 151: ...e Register bit 1 bit 0 TM1 10 bit Counter bit 9 bit 8 TM1AL Register 10 bit ETM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 TM1AL T...

Page 152: ...operate in one of five operating modes Compare Match Output Mode PWM Output Mode Single Pulse Output Mode Capture Input Mode or Timer Counter Mode The operating mode is selected using the TnAM1 and T...

Page 153: ...Therefore when TnCCLR is high no TnPF interrupt request flag will be generated As the name of the mode suggests after a comparison is made the TM output pin will change state The TM output pin condit...

Page 154: ...set to initial Level Low if TnAOC 0 O tp t Toggle with TnAF flag Note TnAIO 0 0 Active High O tp t select Here TnAIO 0 Toggle O tp t select O tp t not affected by TnAF flag Remains High ntil reset by...

Page 155: ...set to initial Level Low if TnBOC 0 O tp t Toggle with TnBF flag Note TnBIO 0 0 Active High O tp t select Here TnBIO 0 Toggle O tp t select O tp t not affected by TnBF flag Remains High ntil reset by...

Page 156: ...e TnAIO 0 0 Active High O tp t select Here TnAIO 0 Toggle O tp t select O tp t not affected by TnAF flag Remains High ntil reset by TnON bit O tp t Pin Reset to Initial val e O tp t controlled by othe...

Page 157: ...le with TnBF flag Note TnBIO 0 0 Active High O tp t select Here TnBIO 0 Toggle O tp t select O tp t not affected by TnBF flag Remains High ntil reset by TnON bit O tp t Pin Reset to Initial val e O tp...

Page 158: ...he PWM period is controlled With the TnCCLR bit set high the PWM period can be finely controlled using the CCRA registers In this case the CCRB registers are used to set the PWM duty value for TPnB ou...

Page 159: ...25 The TP1B_n PWM output frequency fSYS 4 512 fSYS 2048 7 8125kHz duty 256 512 50 If the Duty value defined by CCRA or CCRB register is equal to or greater than the Period value then the PWM output d...

Page 160: ...to Initial val e O tp t controlled by other pin shared f nction O tp t Inverts when TnAPOL is high CCRB CCRP Int Flag TnPF TPnB Pin TnBOC TPnB Pin TnBOC 0 D ty Cycle set by CCRA D ty Cycle set by CCR...

Page 161: ...rolled by other pin shared f nction O tp t Inverts when TnBPOL is high CCRB CCRP Int Flag TnPF TPnB Pin TnBOC TPnB Pin TnBOC 0 D ty Cycle set by CCRB PWM Period set by CCRA ETM PWM Mode Edge Aligned N...

Page 162: ...ion O tp t Inverts when TnAPOL is high CCRB CCRP Int Flag TnPF TPnB Pin TnBOC TPnB Pin TnBOC 0 D ty Cycle set by CCRA D ty Cycle set by CCRB PWM Period set by CCRP ETM PWM Mode Centre Aligned Note 1 H...

Page 163: ...ction CCRB TPnB Pin TnBOC TPnB Pin TnBOC 0 D ty Cycle set by CCRB PWM Period set by CCRA O tp t Inverts when TnBPOL is high CCRP Int Flag TnPF ETM PWM Mode Centre Aligned Note 1 Here TnCCLR 1 therefor...

Page 164: ...rated The TnON bit should remain high when the pulse is in its active state The generated pulse trailing edge of TPnA and TPnB will be generated when the TnON bit is cleared to zero which can be imple...

Page 165: ...RB O tp t Inverts when TnBPOL TCKn pin Software Trigger Cleared by CCRA match TCKn pin Trigger A to set by TCKn pin Software Trigger Software Clear Software Trigger Software Trigger TnBPOL TPnA Pin Tn...

Page 166: ...ive of what events occur on the TPnA and TPnB_0 TPnB_1 TPnB_2 pins the counter will continue to free run until the TnON bit changes from high to low When a CCRP compare match occurs the counter will r...

Page 167: ...in TPnA XX Co nter Stop TnAIO 0 Val e XX YY XX YY Active edge Active edge Active edge 00 Rising edge 0 Falling edge 0 Both edges Disable Capt re ETM CCRA Capture Input Mode Note 1 TnAM 1 0 01 and acti...

Page 168: ...IO0 Val e 00 Rising edge 0 Falling edge Disable Capt re Active edge Active edge XX 0 Both edges Active edges YY TnBM TnBM0 0 Time Co nter Val e ETM CCRB Capture Input Mode Note 1 TnBM 1 0 01 and activ...

Page 169: ...t these signals directly into either a 12 bit digital value Part No Input Channels A D Channel Select Bits Input Pins HT66F20 HT66F30 HT66F40 HT66F50 8 ACS4 ACS2 ACS0 AN0 AN7 HT66F60 12 ACS4 ACS3 ACS0...

Page 170: ...ADCR0 ADCR1 ACERL ACERH To control the function and operation of the A D converter three or four control registers known as ADCR0 ADCR1 ACERL and ACERH are provided These 8 bit registers define funct...

Page 171: ...is bit should be cleared to zero to enable the A D converter If the bit is set high then the A D converter will be switched off reducing the device power consumption As the A D converter will consume...

Page 172: ...o enable the A D converter If the bit is set high then the A D converter will be switched off reducing the device power consumption As the A D converter will consume a limited amount of power even whe...

Page 173: ...he bandgap voltage 1 25V can be used by the A D converter If 1 25V is not used by the A D converter and the LVR LVD function is disabled then the bandgap reference circuit will be automatically switch...

Page 174: ...A D input AN4 Bit 3 ACE3 Define PA3 is A D input or not 0 Not A D input 1 A D input AN3 Bit 2 ACE2 Define PA2 is A D input or not 0 Not A D input 1 A D input AN2 Bit 1 ACE1 Define PA1 is A D input or...

Page 175: ...to or greater than 4MHz For example if the system clock operates at a frequency of 4MHz the ADCK2 ADCK0 bits should not be set to 000 Doing so will give A D clock periods that are less than the minim...

Page 176: ...register will be overridden The A D converter has its own reference voltage pin VREF however the reference voltage can also be supplied from the power supply pin a choice which is made through the VR...

Page 177: ...the conversion value As an alternative method if the interrupts are enabled and the stack is not full the program can wait for an A D interrupt to occur Note When checking for the end of the conversi...

Page 178: ...in power consumption A D Transfer Function As the devices contain a 12 bit A D converter its full scale converted digitised value is equal to FFFH Since the full scale analog input value is equal to t...

Page 179: ...C interrupt mov a 03H mov ADCR1 a select fSYS 8 as A D clock and switch off 1 25V clr ADOFF mov a 0Fh setup ACERL and ACERH to configure pins AN0 AN3 mov ACERL a mov a 00h mov ACERH 00h ACERH is only...

Page 180: ...ion clr START high pulse on START bit to initiate conversion set START reset A D clr START start A D clr ADF clear ADC interrupt request flag set ADE enable ADC interrupt set EMI enable global interru...

Page 181: ...ator The comparator output is recorded via a bit in their respective control register but can also be transferred out onto a shared I O pin Additional comparator functions include output polarity hyst...

Page 182: ...lt these two pins will lose their I O pin functions Any pull high configuration options associated with the comparator shared pins will also be automatically disconnected Bit 6 C0EN Comparator On Off...

Page 183: ...0 I O pin select 1 Comparator pin select This is the Comparator pin or I O pin select bit If the bit is high the comparator will be selected and the two comparator input pins will be enabled As a res...

Page 184: ...e of the output bit changes state its relevant interrupt flag will be set and if the corresponding interrupt enable bit is set then a jump to its relevant interrupt vector will be executed Note that i...

Page 185: ...e where the device can be either master or slave Although the SPI interface specification can control multiple slave devices from a single master but this device provided only one SCS pin If the maste...

Page 186: ...f certain control bits such as CSEN and SIMEN There are several configuration options associated with the SPI interface One of these is to enable the SIM function which selects the SIM pins rather tha...

Page 187: ...l data to be transmitted must be placed in the SIMD register After the data is received from the SPI bus the device can read it from the SIMD register Any transmission or reception of data from the SP...

Page 188: ...PCKP0 Select PCK output pin frequency 00 fSYS 01 fSYS 4 10 fSYS 8 11 TM0 CCRP match frequency 2 Bit 1 SIMEN SIM Control 0 Disable 1 Enable The bit is the overall on off control for the SIM interface W...

Page 189: ...the SCK line will be low when the clock is inactive When the CKPOLB bit is low then the SCK line will be high when the clock is inactive The CKEG bit determines active clock edge type which depends up...

Page 190: ...nal from the master has been received any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register The master should output an SCS signal to ena...

Page 191: ...Rev 2 50 191 June 22 2017 HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 HT66FU30 HT66FU40 HT66FU50 HT66FU60 A D Flash MCU with EEPROM SPI Slave Mode Timing CKEG 1 SPI Transfer Control Flowchart...

Page 192: ...and slave can transmit and receive data however it is the master device that has overall control of the bus For these devices which only operates in slave mode there are two methods of transferring d...

Page 193: ...ction is used to store the data being transmitted and received on the I2 C bus Before the microcontroller writes data to the I2 C bus the actual data to be transmitted must be placed in the SIMD regis...

Page 194: ...1 PCKP0 Select PCK output pin frequency 00 fSYS 01 fSYS 4 10 fSYS 8 11 TM0 CCRP match frequency 2 Bit 1 SIMEN SIM Control 0 Disable 1 Enable The bit is the overall on off control for the SIM interface...

Page 195: ...ransmit acknowledge flag 0 Slave send acknowledge flag 1 Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag After the slave device receipt of 8 bits of data this bit will...

Page 196: ...bus the actual data to be transmitted must be placed in the SIMD register After the data is received from the I2 C bus the device can read it from the SIMD register Any transmission or reception of d...

Page 197: ...outine the slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8 bit data transfer Durin...

Page 198: ...devices after receiving this 7 bit address data will compare it with their own 7 bit slave address If the address sent out by the master matches the internal address of the microcontroller slave devic...

Page 199: ...if it is to be a transmitter or a receiver If the SRW flag is high the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to 1 If the SRW flag is low t...

Page 200: ...CU with EEPROM Note When a slave address is matched the devices must be placed in either the transmit mode and then write data to the SIMD register or in the receive mode where it must implement a dum...

Page 201: ...ock is fSYS 16 010 SPI master mode SPI clock is fSYS 64 011 SPI master mode SPI clock is fTBC 100 SPI master mode SPI clock is TM0 CCRP match frequency 2 101 SPI slave mode 110 I2 C slave mode 111 Unu...

Page 202: ...le bits by the application program is controlled by a series of registers located in the Special Purpose Data Memory as shown in the accompanying table The number of registers depends upon the device...

Page 203: ...LVE XPE SIME HT66F30 Name Bit 7 6 5 4 3 2 1 0 INTEG INT1S1 INT1S0 INT0S1 INT0S0 INTC0 CP0F INT1F INT0F CP0E INT1E INT0E EMI INTC1 ADF MF1F MF0F CP1F ADE MF1E MF0E CP1E INTC2 MF3F TB1F TB0F MF2F MF3E T...

Page 204: ...T0PF T2AE T2PE T0AE T0PE MFI1 T1BF T1AF T1PF T1BE T1AE T1PE MFI2 DEF LVF XPF SIMF DEE LVE XPE SIME MFI3 T3AF T3PF T3AE T3PE HT66F60 Name Bit 7 6 5 4 3 2 1 0 INTEG INT3S1 INT3S0 INT2S1 INT2S0 INT1S1 I...

Page 205: ...e 10 Falling edge 11 Rising and falling edges HT66F60 Bit 7 6 5 4 3 2 1 0 Name INT3S1 INT3S0 INT2S1 INT2S0 INT1S1 INT1S0 INT0S1 INT0S0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 I...

Page 206: ...0 0 Bit 7 Unimplemented read as 0 Bit 6 CP0F Comparator 0 interrupt request flag 0 No request 1 Interrupt request Bit 5 INT1F INT1 interrupt request flag 0 No request 1 Interrupt request Bit 4 INT0F...

Page 207: ...nimplemented read as 0 Bit 6 INT2F INT2 interrupt request flag 0 No request 1 Interrupt request Bit 5 INT1F INT1 interrupt request flag 0 No request 1 Interrupt request Bit 4 INT0F INT0 interrupt requ...

Page 208: ...lag 0 No request 1 Interrupt request Bit 6 MF1F Multi function Interrupt 1 Request Flag 0 No request 1 Interrupt request Bit 5 MF0F Multi function Interrupt 0 Request Flag 0 No request 1 Interrupt req...

Page 209: ...g 0 No request 1 Interrupt request Bit 6 CP1F Comparator 1 Interrupt Request Flag 0 No request 1 Interrupt request Bit 5 CP0F Comparator 0 Interrupt Request Flag 0 No request 1 Interrupt request Bit 4...

Page 210: ...quest Flag 0 No request 1 Interrupt request Bit 6 TB1F Time Base 1 Interrupt Request Flag 0 No request 1 Interrupt request Bit 5 TB0F Time Base 0 Interrupt Request Flag 0 No request 1 Interrupt reques...

Page 211: ...rrupt request Bit 6 MF3F Multi function Interrupt 3 Request Flag 0 No request 1 Interrupt request Bit 5 MF2F Multi function Interrupt 2 Request Flag 0 No request 1 Interrupt request Bit 4 MF1F Multi f...

Page 212: ...No request 1 Interrupt request Bit 6 TB1F Time Base 1 interrupt request flag 0 No request 1 Interrupt request Bit 5 TB0F Time Base 0 interrupt request flag 0 No request 1 Interrupt request Bit 4 MF4F...

Page 213: ...isable 1 Enable HT66F40 HT66F50 HT66F60 Bit 7 6 5 4 3 2 1 0 Name T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PE R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 T2AF TM2 Comparator A match inter...

Page 214: ...it 0 T1PE TM1 Comparator P match interrupt control 0 Disable 1 Enable HT66F30 HT66F40 HT66F50 HT66F60 Bit 7 6 5 4 3 2 1 0 Name T1BF T1AF T1PF T1BE T1AE T1PE R W R W R W R W R W R W R W POR 0 0 0 0 0 0...

Page 215: ...1 Interrupt request Bit 3 DEE Data EEPROM Interrupt Control 0 Disable 1 Enable Bit 2 LVE LVD Interrupt Control 0 Disable 1 Enable Bit 1 XPE External Peripheral Interrupt Control 0 Disable 1 Enable Bit...

Page 216: ...rupt service routine must be terminated with a RETI which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point wh...

Page 217: ...terrupt Name HT66F30 only MF3F M Funct 3 MF3E XPF PINT Pin XPE EMI 2CH LVF LVD LVE DEF EEPROM DEE EMI EMI EMI EMI EMI EMI EMI EMI EMI SIMF SIM SIME T1BF TM1 B T1BE T1AF TM1 A T1AE T1PF TM1 P T1PE T0AF...

Page 218: ...T1AF TM1 A T1AE T1PF TM1 P T1PE TP0AF TM0 A T0AE TP0AF TM0 P T0PE INT0F INT0 Pin INT0E INT1F INT1 Pin INT1E CP0F Comp 0 CP0E CP1F Comp 1 CP1E MF0F M Funct 0 MF0E MF1F M Funct 1 MF1E ADF A D ADE EMI M...

Page 219: ...VD LVE DEF EEPROM DEE EMI EMI EMI EMI EMI EMI EMI EMI EMI SIMF SIM SIME T1BF TM1 B T1BE T1AF TM1 A T1AE T1PF TM1 P T1PE T0AF TM0 A T0AE T0PF TM0 P T0PE INT0F INT0 Pin INT0E INT1F INT1 Pin INT1E CP0F C...

Page 220: ...l comparators A comparator interrupt request will take place when the comparator interrupt request flags CP0F or CP1F are set a situation that will occur when the comparator output bit changes state T...

Page 221: ...internal interrupt They are controlled by the overflow signals from their respective timer functions When these happens their respective interrupt request flags TB0F or TB1F will be set To allow the...

Page 222: ...R 0 0 1 1 0 1 1 1 Bit 7 TBON TB0 and TB1 Control 0 Disable 1 Enable Bit 6 TBCK Select fTB Clock 0 fTBC 1 fSYS 4 Bit 5 4 TB11 TB10 Select Time Base 1 Time out Period 00 4096 fTB 01 8192 fTB 10 16384 fT...

Page 223: ...ector address the global interrupt enable bit EMI external peripheral interrupt enable bit XPE and associated Multi function interrupt enable bit must first be set When the interrupt is enabled the st...

Page 224: ...The Compact and Standard Type TMs have two interrupts each while the Enhanced Type TM has three interrupts All of the TM interrupts are contained within the Multi function Interrupts For each of the...

Page 225: ...t then when the interrupt service routine is executed as only the Multi function interrupt request flags MF0F MF5F will be automatically cleared the individual request flag for the function needs to b...

Page 226: ...tage condition will be detemined A low voltage condition is indicated when the LVDO bit is set If the LVDO bit is low this indicates that the VDD voltage is above the preset low voltage value The LVDE...

Page 227: ...stabilise before reading the LVDO bit Note also that as the VDD voltage may rise and fall rather slowly at the voltage nears that of VLVD there may be multiple bit LVDO transitions LVD Operation The L...

Page 228: ...her output ports lines as segment pins The LCD driver function is controlled using the SCOMC register which in addition to controlling the overall on off function also controls the bias voltage setup...

Page 229: ...2 1 0 Name D7 ISEL1 ISEL0 SCOMEN COM3EN COM2EN COM1EN COM0EN R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 Reserved Bit 0 Correct level bit must be reset to zero for correct operation...

Page 230: ...0 0 Bit 7 Reserved Bit 0 Correct level bit must be reset to zero for correct operation 1 Unpredictable operation bit must not be set high Bit 6 5 ISEL1 ISEL0 Select SCOM typical bias current VDD 5V 00...

Page 231: ...unction the details of which are shown in the table No Options Oscillator Options 1 High Speed System Oscillator Selection fH 1 HXT 2 ERC 3 HIRC 2 Low Speed System Oscillator Selection fL 1 LXT 2 LIRC...

Page 232: ...th EEPROM No Options 13 I2 C Debounce Time Selection 1 No debounce 2 1 system clock debounce 3 2 system clock debounce Application Circuits Note It is recommended that this component is added for adde...

Page 233: ...ceiver data buffer Transmit and Receive Multiple Interrupt Generation Sources Transmitter Empty Transmitter Idle Receiver Full Receiver Overrun Address Mode Detect TX pin is high impedance when the UA...

Page 234: ...Rev 2 50 234 June 22 2017 HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 HT66FU30 HT66FU40 HT66FU50 HT66FU60 A D Flash MCU with EEPROM Pin Assignment...

Page 235: ...Rev 2 50 235 June 22 2017 HT66F20 HT66F30 HT66F40 HT66F50 HT66F60 HT66FU30 HT66FU40 HT66FU50 HT66FU60 A D Flash MCU with EEPROM...

Page 236: ...lave SPI Serial Data Out Output Signal Internally connected to the MCU Master SPI SDI input signal SCK I Internal Slave SPI Serial Clock Input Signal Internally connected to the MCU Master SPI SCK out...

Page 237: ...nput Low Voltage for RX Ports 0 0 3VDD V VIH Input High Voltage for RX Ports 0 7VDD VDD V IOL TX Port Sink Current 3 0V VO 0 1VDD 2 5 5 0 mA 5 0V 10 0 25 0 mA IOH RX Port Source Current 3 0V VO 0 9VDD...

Page 238: ...function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the dat...

Page 239: ...are transmitted SCS should not return to a high level Instead SCS must remain at a low level until the whole 16 bit data transaction is completed If SCS is de asserted that is returned to a high level...

Page 240: ...1 register and TXEN in UCR2 register are set to 1 If the control bit UARTEN or TXEN is equal to zero the TX pin is in the state of high impedance Similarly the RX pin is the UART receiver serial data...

Page 241: ...Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read FIFO 0 0 0 0 0 Read Register 0 0 0 1 0 A2 A1 A0 Write FIFO 0 0 0 0 1 Write Register 0 0 0 1 1 A2 A1 A0 Note here stands for don t care UART Status and Control Regis...

Page 242: ...read to the status register USR followed by an access to the RXR data register Bit 5 FERR Framing error flag 0 No framing error is detected 1 Framing error is detected The FERR flag is the framing err...

Page 243: ...ag is known as the transmission complete flag When this read only flag is 0 it indicates that a transmission is in progress This flag will be set to 1 when the TXIF flag is 1 and when there is no tran...

Page 244: ...its in UCR1 UCR2 and BRG registers will remain unaffected If the UART is active and the UARTEN bit is cleared all pending transmissions and receptions will be terminated and the module will be reset a...

Page 245: ...The register also serves to control the baud rate speed receiver wake up function enable and the address detect function enable Further explanation on each of the bits is given below Bit 7 6 5 4 3 2...

Page 246: ...led This bit enables or disables the receiver wake up function If this bit is equal to 1 and the MCU is in IDLE or SLEEP mode a falling edge on the RX input pin will wake up the device If this bit is...

Page 247: ...ed baud rate generator The baud rate is controlled by its own internal free running 8 bit timer the period of which is determined by two factors The first of these is the value placed in the baud rate...

Page 248: ...r BRGH 0 fCLKI 4MHz fCLKI 3 579545MHz fCLKI 7 159MHz BRG Kbaud Error BRG Kbaud Error BRG Kbaud Error 0 3 207 0 300 0 16 185 0 300 0 00 1 2 51 1 202 0 16 46 1 190 0 83 92 1 203 0 23 2 4 25 2 404 0 16 2...

Page 249: ...ta is transmitted and received LSB first Although the transmitter and receiver of the UART are functionally independent they both use the same data format and baud rate In all cases stop bits will be...

Page 250: ...ord length will be set to 9 bits In this case the 9th bit which is the MSB needs to be stored in the TX8 bit in the UCR1 register At the transmitter core lies the Transmitter Shift Register more commo...

Page 251: ...a If the TEIE bit is set then the TXIF flag will generate an interrupt During a data transmission a write instruction to the TXR register will place the data into the TXR register which will be copied...

Page 252: ...a is serially shifted in on the external RX input pin to the shift register with the least significant bit LSB first The RXR register is a four byte deep FIFO data buffer where four bytes can be held...

Page 253: ...ains only zeros with the FERR flag set The break character will be loaded into the buffer and no further data will be received until stop bits are received It should be noted that the RIDLE read only...

Page 254: ...incoming data and noise If noise is detected within a frame the following will occur The read only noise flag NF in the USR register will be set on the rising edge of the RXIF bit Data will be transfe...

Page 255: ...t condition which is also a UART interrupt source does not have an associated flag but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the...

Page 256: ...EN bit in the UCR1 register to disable the UART Module circuitry after which the SCS internal line can be set high to disable the SPI interface circuits When the UART and SPI interfaces are powered do...

Page 257: ...e HT66FU30 PRM0 Register PCK and PINT pin remap setup Bit 1 0 Name SIMPS0 PCKPS Setting value 1 1 HT66FU40 HT66FU50 PRM0 Register PCK and PINT pin remap setup Bit 2 1 0 Name SIMPS1 SIMPS0 PCKPS Settin...

Page 258: ...S 8 11 PCK output frequency is TM0 CCRP match frequency 2 PCK output enable control bit PCKEN in the SIMC0 Register Bit 4 Name PCKEN value 1 0 Disable PCK output 1 Enable PCK output After the above se...

Page 259: ...PCL will also take one more cycle to implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instru...

Page 260: ...tremely useful set of branch instructions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual bits Depending upon the conditions t...

Page 261: ...rry result in Data Memory 1Note Z C AC OV DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Mem...

Page 262: ...e RET A x Return from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read Operation TABRD m Read table specific page to TBLH and Data Memory 2Note None TABRDC...

Page 263: ...The contents of the Accumulator and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C ADDM A m Add ACC to Data Memory Descrip...

Page 264: ...dog Timer Description The TO PDF flags and the WDT are all cleared Operation WDT cleared TO 0 PDF 0 Affected flag s TO PDF CLR WDT1 Pre clear Watchdog Timer Description The TO PDF flags and the WDT ar...

Page 265: ...C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Operation m ACC 00H or m ACC 06H or m ACC 60H...

Page 266: ...ified Data Memory Operation m ACC Affected flag s None NOP No operation Description No operation is performed Execution continues with the next instruction Operation No operation Affected flag s None...

Page 267: ...lag s None RLA m Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored i...

Page 268: ...C m 0 Affected flag s C SBC A m Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator...

Page 269: ...n If the result is not 0 the program proceeds with the following instruction Operation m m 1 Skip if m 0 Affected flag s None SIZA m Skip if increment Data Memory is zero with result in ACC Descriptio...

Page 270: ...the specified Data Memory are interchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s No...

Page 271: ...ble last page to TBLH and Data Memory Description The low byte of the program code last page addressed by the table pointer TBLP is moved to the specified Data Memory and the high byte moved to TBLH O...

Page 272: ...ation may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package Carton Information Additional supplementary information with regard to...

Page 273: ...Lead Packages See Fig 1 Symbol Dimensions in inch Min Nom Max A 0 780 0 790 0 800 B 0 240 0 250 0 280 C 0 115 0 130 0 195 D 0 115 0 130 0 150 E 0 014 0 018 0 022 F 0 045 0 060 0 070 G 0 1 BSC H 0 300...

Page 274: ...ions in mm Min Nom Max A 18 92 19 43 19 94 B 6 99 7 24 7 49 C 3 05 3 43 3 81 D 2 79 3 30 3 81 E 0 36 0 46 0 56 F 1 14 1 27 1 52 G 2 54 BSC H 7 62 7 87 8 26 I 10 92 See Fig 2 Type 2 Symbol Dimensions i...

Page 275: ...16 pin NSOP 150mil Outline Dimensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 012 0 020 C 0 390 BSC D 0 069 E 0 050 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 0 8 Symbol...

Page 276: ...16 pin SSOP 150mil Outline Dimensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 008 0 012 C 0 193 BSC D 0 069 E 0 025 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 0 8 Symbol D...

Page 277: ...Lead Packages See Fig 1 Symbol Dimensions in inch Min Nom Max A 0 980 1 030 1 060 B 0 240 0 250 0 280 C 0 115 0 130 0 195 D 0 115 0 130 0 150 E 0 014 0 018 0 022 F 0 045 0 060 0 070 G 0 100 BSC H 0 30...

Page 278: ...in inch Min Nom Max A 0 945 0 965 0 985 B 0 275 0 285 0 295 C 0 120 0 135 0 150 D 0 110 0 130 0 150 E 0 014 0 018 0 022 F 0 045 0 050 0 060 G 0 1 BSC H 0 300 0 310 0 325 I 0 430 Symbol Dimensions in...

Page 279: ...pin SOP 300mil Outline Dimensions Symbol Dimensions in inch Min Nom Max A 0 406 BSC B 0 295 BSC C 0 012 0 020 C 0 504 BSC D 0 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 0 8 Symbol Dime...

Page 280: ...20 pin SSOP 150mil Outline Dimensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 155 BSC C 0 008 0 012 C 0 341 BSC D 0 069 E 0 025 BSC F 0 004 0 0098 G 0 016 0 05 H 0 004 0 01 0 8 Symbol Di...

Page 281: ...2 Lead Packages See Fig1 Symbol Dimensions in inch Min Nom Max A 1 230 1 250 1 280 B 0 240 0 250 0 280 C 0 115 0 130 0 195 D 0 115 0 130 0 150 E 0 014 0 018 0 022 F 0 045 0 060 0 070 G 0 1 BSC H 0 300...

Page 282: ...ions in mm Min Nom Max A 29 46 30 10 30 35 B 6 10 6 35 7 11 C 2 92 3 30 4 95 D 2 92 3 30 3 81 E 0 36 0 46 0 56 F 1 14 1 52 1 78 G 2 54 BSC H 7 62 7 87 8 26 I 10 92 See Fig2 Symbol Dimensions in inch M...

Page 283: ...4 pin SOP 300mil Outline Dimensions Symbol Dimensions in inch Min Nom Max A 0 406 BSC B 0 295 BSC C 0 012 0 020 C 0 606 BSC D 0 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 0 8 Symbol Dim...

Page 284: ...4 pin SSOP 150mil Outline Dimensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 008 0 012 C 0 341 BSC D 0 069 E 0 025 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 0 8 Symbol Di...

Page 285: ...pin SKDIP 300mil Outline Dimensions Symbol Dimensions in inch Min Nom Max A 1 380 1 420 B 0 280 0 310 C 0 060 0 130 D 0 125 0 200 E 0 015 0 022 F 0 045 0 065 G 0 1 BSC H 0 300 0 325 I 0 400 Symbol Dim...

Page 286: ...8 pin SOP 300mil Outline Dimensions Symbol Dimensions in inch Min Nom Max A 0 406 BSC B 0 295 BSC C 0 012 0 020 C 0 705 BSC D 0 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 0 8 Symbol Dim...

Page 287: ...28 pin SSOP 150mil Outline Dimensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 008 0 012 C 0 390 BSC D 0 069 E 0 025 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 0 8 Symbol D...

Page 288: ...0 028 0 030 0 031 A1 0 000 0 001 0 002 A3 0 008 REF b 0 007 0 010 0 012 D 0 193 0 197 0 201 E 0 193 0 197 0 201 e 0 020 BSC D2 0 122 0 126 0 130 E2 0 122 0 126 0 130 L 0 014 0 016 0 018 K 0 008 Symbol...

Page 289: ...Max A 0 028 0 030 0 031 A1 0 000 0 001 0 002 A3 0 008 REF b 0 007 0 010 0 012 D 0 232 0 236 0 240 E 0 232 0 236 0 240 e 0 020 BSC D2 0 173 0 177 0 181 E2 0 173 0 177 0 181 L 0 014 0 016 0 018 K 0 008...

Page 290: ...ymbol Dimensions in inch Min Nom Max A 0 472 BSC B 0 394 BSC C 0 472 BSC D 0 394 BSC E 0 0315 BSC F 0 012 0 015 0 018 G 0 053 0 055 0 057 H 0 063 I 0 002 0 006 J 0 018 0 024 0 030 K 0 004 0 008 0 7 Sy...

Page 291: ...ns Symbol Dimensions in inch Min Nom Max A 0 395 0 42 B 0 291 0 295 0 299 C 0 008 0 014 C 0 620 0 625 0 630 D 0 095 0 102 0 11 E 0 025 BSC F 0 008 0 012 0 016 G 0 020 0 040 H 0 005 0 010 0 8 Symbol Di...

Page 292: ...s in inch Min Nom Max A 0 031 0 033 0 035 A1 0 000 0 001 0 002 A3 0 008 REF b 0 008 0 010 0 012 D 0 276 BSC E 0 276 BSC e 0 020 BSC D2 0 219 0 222 0 226 E2 0 219 0 222 0 226 L 0 014 0 016 0 018 Symbol...

Page 293: ...ol Dimensions in inch Min Nom Max A 0 354 BSC B 0 276 BSC C 0 354 BSC D 0 276 BSC E 0 020 BSC F 0 007 0 009 0 011 G 0 053 0 055 0 057 H 0 063 I 0 002 0 006 J 0 018 0 024 0 030 K 0 004 0 008 0 7 Symbol...

Page 294: ...tions mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommend...

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