HOLT ADK-35850 User Manual Download Page 26

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XOUT

XOUT32

XIN32

DFSDM

DFSDP

XIN

XIN32

XOUT32

VBG

VREF

+3V3

VOUT

VUTMI

VANA

+3V3

VUTMI

VANA

+3V3

nRST

NRSTB

TDI

TDO

TMS

TCK

DHSDM

DHSDP

Title

Size

Document Number

Rev

Date:

Sheet

CM3 BOARD REV C.DSN

ARM CORTEX M3 MICROCONTROLLER BOARD

Thursday, October 06, 2011

Title

Size

Document Number

Rev

Date:

Sheet

CM3 BOARD REV C.DSN

ARM CORTEX M3 MICROCONTROLLER BOARD

Thursday, October 06, 2011

Title

Size

Document Number

Rev

Date:

Sheet

CM3 BOARD REV C.DSN

ARM CORTEX M3 MICROCONTROLLER BOARD

Thursday, October 06, 2011

PROVISIONAL

ARM CORTEX M3 MCU

NEXT BOARD REVISION:

CONNECT R1 TO GND, NOT VCC.
MAKE R1 1K, NOT PROVISIONAL.

CONNECT U1 PIN 138 (TEST) TO
NEW 1K PULL-DOWN RESISTOR.

SOT-23

0805 MURATA LQM21FN100M70

HOLT INTEGRATED CIRCUITS, Mission Viejo, CA, USA

C29

100nF

C29

100nF

C12

10uF

C12

10uF

4.7uF

C17

100nF

C17

100nF

C20

4.7uF

C20

4.7uF

JP1

6.8K 1%

10uH/100mA

C28

100nF

C28

100nF

C11

100nF

C11

100nF

10uF

C14

20pF

C14

20pF

VR1

LM4040-2.5

VR1

LM4040-2.5

R3 4.7K

C26

100nF

C26

100nF

C30

10uF

C30

10uF

39R

C19

100nF

C19

100nF

100K

39R

100nF

C16

100nF

C16

100nF

C23
10pF

100nF

C25

20pF

C25

20pF

C24

100nF

C24

100nF

C13

100nF

C13

100nF

C27

20pF

C27

20pF

C22

100nF

C22

100nF

C10

100nF

C10

100nF

C31

4.7uF

C31

4.7uF

100nF

C32

4.7uF

C32

4.7uF

C21

20pF

C21

20pF

U1B

SAM3U

U1B

SAM3U

NRST

TDI

TDO/TRACESWO

TMS/SWDIO

TCK/SWCLK

VBG

DHSDP

DHSDM

DFSDM

DFSDP

FWUP

135

SHDN

136

ERASE

137

TEST

138

NRSTB

141

XIN32

144

XOUT32

143

XIN

XOUT

ADVREF

AD12BVREF

VDDCORE1

VDDCORE2

VDDCORE3

VDDCORE4

VDDCORE5

VDDCORE6

125

VDDOUT

VDDIN

VDDIO1

GND1

GNDPLL

VDDUTMI

GNDUT

VDDIO2

GND2

GND3

VDDANA

GNDANA

VDDIO3

GND4

VDDIO4

104

GND5

126

VDDIO5

127

VDDBU

139

GNDBU

140

VDDPLL

JTAGSEL

142

C18

100nF

C18

100nF

PROV

12.000MHz

C15

100nF

C15

100nF

32.768KHz

100nF

10uH/100mA

100nF

10nF

Summary of Contents for ADK-35850

Page 1: ...AN 35850 Rev New Holt Integrated Circuits HI 35850 ARINC 429 Protocol IC 1x RECEIVER 1x TRANSMITTER ADK 35850 Application Development Kit Users Guide January 25 2021...

Page 2: ...AN 35850 2 Holt Integrated Circuits REVISION HISTORY Revision Date Description of Change AN 35850 Rev New 01 25 2021 Initial Release...

Page 3: ...board so no other USB programming adapters are needed This guide describes how to set up and run the pre programmed demos Additional support material and all required project software are found in the...

Page 4: ...Cortex M3 16 32 bit microprocessor debug interface and regulated 3 3VDC power supply The HI 35850 daughter card is separable and useable for user prototyping on other platforms Hardware Block Diagram...

Page 5: ...ction on SPI trouble shooting towards the end of this document SW2 Transmits maximum number of FIFO messages 32 continuously Press q to quit DIP SW1 SWITCHES SWITCH DEFAULT DESCRIPTION SW 1 ON ON SPI...

Page 6: ...lator takes 3 3V and generates 5V for the HI 35850 This is meant for demonstration purposes See Analog Devices website for performance data and suitability for the intended application In summary it o...

Page 7: ...ugh the inter board headers See the External Host interface header pin description for the pin list in the previous section The lower ARM Cortex M3 board is based on the flash programmable Microchip A...

Page 8: ...teraterm 4 71 exe installer program from the Holt CD Accept the license agreement stating redistribution is permitted provided that copyright notice is retained The notice can be displayed from the T...

Page 9: ...es Press 2 Load Transmit FIFO with 8 messages Press 3 Reads ARINC RX FIFO and displays Press 4 Reads ARINC RX FIFO and displays in Loop mode Press M Write Label Memory Press m Read and Display Label M...

Page 10: ...puts the display will show both TX and RX data To simplify the transmit and receive demos below command t will be entered first which will enable the HI 35850 Self Test feature This causes the transmi...

Page 11: ...messages in the transmit FIFO with an incrementing data pattern Transmissions should begin immediately and can be viewed with an oscilloscope on J5 or J6 pins 1 and 2 To read the messages from the Rec...

Page 12: ...tween the ACLK divisor selections listed in the data sheet Once this has been invoked the Divisor is in use The Holt daughter card has an on board 1MHz oscillator so a divisor of 1 should be used To u...

Page 13: ...ta sheet To use the feature the look up table must be initialized before enabling CR2 otherwise un initialized table contents will cause unpredictable reception filtering When writing to the memory lo...

Page 14: ...ected Command l toggles the CR2 Enable Label Recognition bit high in the Control Word the first time l is pressed To disable Label recognition press l again When Label recognition is enabled this demo...

Page 15: ...d New Hardware message should appear for the J Link device After several seconds Windows should load the appropriate driver and advise Your hardware is ready for use An internet connection is required...

Page 16: ...ab Diagnostics Suppress these diagnostics add Pe068 to list 7 RAM based projects are not supported due to the limited amount of RAM on the MCU By design the Cortex M3 runs slower in RAM than in Flash...

Page 17: ...ode 0x0A and review the value for clues to the problem The nCE CLK SI and SO should look similar to the analyzer plot shown below Final Tips for new host interfacing 1 The preferred ACLK rate is 1MHz...

Page 18: ...ization and transmitting and receiving ARINC messages Some of these functions may not be used in this demo main c The primary program entry and main loop in main Holt_Board c Contains macros for SPI i...

Page 19: ...k source The SPI block divides this by 4 for a 12MHz SPI clock rate which is the maximum for the HI 35850 There is no lower frequency limit but most application should use at least a 1MHz rate for rea...

Page 20: ...R9 P330ACT ND Panasonic ERJ 6GEYJ331V 11 2 Res 40 2K 1 1 8W 0805 SMD R12 R13 P40 2KCCT ND Panasonic ERJ 6ENF4022V 11 1 Res 53 6K 1 1 8W 0805 SMD R2 P53 6KCCT ND Panasonic ERJ 6ENF5362V 14 1 Res 100K...

Page 21: ...P3 C8 0 1uF TP10 5V R1 162K R3 100K TP9 VDD TP13 J2 CON2 1 2 TP6 TP12 ACLK TP8 3 2 1 4 ON CLOSED SW1 SMD 4 POS DIP Switch 1 2 3 4 8 7 6 5 5V R15 51 J_3 Header 2x20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15...

Page 22: ...009 213R 561 14 1 Jack DC Power 2 5mm ID x 2 1mm pin J7 CP 102AH ND CUI PJ 102AH 15 2 Receptacle Female 2x20 0 1 Pitch 8 5mm Height 3 2mm Solder Tails J3 J4 S6104 ND Sullins PPTC202LFBN RC 16 1 Recept...

Page 23: ...03 C59 490 1415 1 ND Murata GRM1885C1H330JA01D 48 2 Capacitor Ceramic 15pF 5 50V C0G 0603 C60 C61 490 1407 1 ND Murata GRM1885C1H150JA01D 49 2 Capacitor Ceramic 10pF 5 50V C0G 0603 C62 C63 490 1403 1...

Page 24: ...RD A 1 7 Thursday October 06 2011 Title Size Document Number Rev Date Sheet of CM3 BOARD REV C DSN C ARM CORTEX M3 MICROCONTROLLER BOARD A 1 7 Thursday October 06 2011 SERIAL PORT USB2 0 PORT ARM CORT...

Page 25: ...WKUP1 111 PA2 WKUP2 113 PA3 CK 115 PA4 CDA 117 PA5 DA0 119 PA6 DA1 121 PA7 DA2 123 PA8 DA3 128 PA9 TWD0 130 PA10 TWCK0 132 PA11 URXD 133 PA12 UTXD 134 PA13 MISO 87 PA14 MOSI 88 PA15 SPCK 91 PA16 NPCS...

Page 26: ...C11 100nF C11 100nF R7 1R R7 1R C3 10uF C3 10uF C14 20pF C14 20pF VR1 LM4040 2 5 VR1 LM4040 2 5 2 1 3 R3 4 7K R3 4 7K C26 100nF C26 100nF C30 10uF C30 10uF R4 39R R4 39R C19 100nF C19 100nF R2 100K R2...

Page 27: ...A 4 7 Thursday October 06 2011 Title Size Document Number Rev Date Sheet of CM3 BOARD REV C DSN C ARM CORTEX M3 MICROCONTROLLER BOARD A 4 7 Thursday October 06 2011 Title Size Document Number Rev Dat...

Page 28: ...TED TXD1 RXD1 RTS1 CTS1 USB RS 232 SERIAL HOLT INTEGRATED CIRCUITS Mission Viejo CA USA U3 MAX3232CSE U3 MAX3232CSE T1IN 11 T2IN 10 R1OUT 12 R2OUT 9 T1OUT 14 T2OUT 7 R1IN 13 R2IN 8 V 2 C1 1 C1 3 C2 4...

Page 29: ...Document Number Rev Date Sheet of CM3 BOARD REV C DSN C ARM CORTEX M3 MICROCONTROLLER BOARD A 6 7 Thursday October 06 2011 POWER SOT 223 POWER SUPPLY HOLT INTEGRATED CIRCUITS Mission Viejo CA USA C45...

Page 30: ...GGER IF ABOVE CIRCUITRY IS NOT POPULATED OR IS DISABLED BY JUMPER JP2 NOT PART OF A CUSTOMER DESIGN THIS BLOCK IS COMPRISED OF U8 Y3 C47 C53 C55 C58 C62 C65 R30 R32 R35 R37 R39 R41 AND R43 RESET SEGGE...

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