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Hitachi HTS548020M9AT00, Specifications

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Hitachi HTS548020M9AT00 Specifications Download Page 165

Travelstar 5K80 Hard Disk Drive Specification

149

 

Note 1. When the Feature register is 03h (= Set Transfer mode) the Sector Count Register specifies the transfer 
mechanism. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value.

When the Feature Register is 05h (=Enable Advanced Power Management) the Sector Count Register specifies the 
Advanced Power Management level.

 

Note 2.

 If the number of auto reassigned sectors reaches the device's reassignment capacity, the write cache func-

tion will be automatically disabled. Although the device still accepts the Set Features command (with Feature reg-
ister = 02h) without error, the write cache function will remain disabled. For the current write cache function status, 
refer to the Identify Device Information (129 word) by the Identify Device command.

Hard reset or power off must not be done during the first 5 seconds after write command completion when write 
cache is enabled.

Note 3.

 When the Feature register is 85h (=Disable Advanced Power Management), the deepest Power Saving 

mode becomes Active Idle.

PIO Default Transfer Mode

00000 000

PIO Default Transfer Mode, Disable IORDY

00000 001

PIO Flow Control Transfer Mode X

00001 nnn (nnn=000,001,010,011,100)

Multiword DMA mode x

00100 nnn (nnn=000,001,010)

Ultra DMA mode x

01000 nnn (nnn=000,001,010,011,100)

C0h-FEh

The deepest Power Saving Mode is Active Idle

80h-BFh

The deepest Power Saving Mode is Low Power Idle

01h-7Fh

The deepest Power Saving Mode is Standby

00h, FFh

Aborted

Summary of Contents for HTS548020M9AT00

Page 1: ...k Drive Specification Hitachi Travelstar 5K80 2 5 inch ATA IDE hard disk drive Models HTS548080M9AT00 HTS548060M9AT00 HTS548040M9AT00 HTS548030M9AT00 HTS548020M9AT00 Revision 2 1 17 November 2003 Document Part S13G 1056 21 Publication Number 1560 ...

Page 2: ......

Page 3: ...ard Disk Drive Specification Hitachi Travelstar 5K80 2 5 inch ATA IDE hard disk drive Models HTS548080M9AT00 HTS548060M9AT00 HTS548040M9AT00 HTS548030M9AT00 HTS548020M9AT00 Revision 2 1 17 November 2003 S13K 1056 21 Publication Number 1560 ...

Page 4: ...ccuracies or typographical errors Changes are periodically made to the information herein these changes will be incorporated in new editions of the publication Hitachi may make improvements or changes in any products or programs described in this publication at any time It is possible that this publication may contain reference to or information about Hitachi products machines and programs program...

Page 5: ...11 4 3 Cylinder allocation 12 4 4 Performance characteristics 13 4 4 1 Command overhead 13 4 4 2 Mechanical positioning 13 4 4 3 Operating modes 15 5 0 Data integrity 17 5 1 Data loss at power off 17 5 2 Write Cache 17 5 3 Equipment status 17 5 4 WRITE safety 18 5 5 Data buffer test 18 5 6 Error recovery 18 5 7 Automatic reallocation 18 5 7 1 Nonrecovered write errors 18 5 7 2 Nonrecoverable read ...

Page 6: ...Operating shock 31 6 5 4 Nonoperating shock 31 6 6 Acoustics 32 6 6 1 Sound power levels 32 6 6 2 Discrete tone penalty 32 6 7 Identification labels 33 6 8 Electromagnetic compatibility 33 6 8 1 CE mark 33 6 8 2 C TICK mark 33 6 8 3 BSMI mark 33 6 8 4 MIC mark 33 6 9 Safety 33 6 9 1 UL and CSA approval 34 6 9 2 IEC compliance 34 6 9 3 German safety mark 34 6 9 4 Flammability 34 6 9 5 Secondary cir...

Page 7: ...0 4 Device Control Register 61 10 5 Drive Address Register 61 10 6 Device Register 62 10 7 Error Register 62 10 8 Features Register 63 10 9 LBA High Register 63 10 10 LBA Low Register 63 10 11 LBA Mid Register 63 10 12 Sector Count Register 63 10 13 Status Register 63 11 0 General 65 11 1 Reset response 65 11 2 Register initialization 66 11 3 Diagnostic and Reset considerations 67 11 4 Power off c...

Page 8: ... 11 10 1 Example for operation In LBA Mode 79 11 10 2 Set Max security extension commands 80 11 11 Address Offset Feature vendor specific 81 11 11 1 Enable Disable Address Offset Mode 81 11 11 2 Identify Device Data 82 11 11 3 Exceptions in Address Offset Mode 82 11 12 Seek Overlap 83 11 13 Write Cache function 83 11 14 Reassign Function 84 11 14 1 Auto Reassign Function 84 11 15 48 bit Address Fe...

Page 9: ...35 13 24 Recalibrate 1xh 137 13 25 Security Disable Password F6h 138 13 26 Security Disable Password F6h 139 13 27 Security Erase Unit F4h 140 13 28 Security Freeze Lock F5h 142 13 29 Security Set Password F1h 143 13 30 Security Unlock F2h 145 13 31 Seek 7xh 146 13 32 Sense Condition F0h vendor specific 147 13 33 Set Features EFh 148 13 34 Set Max ADDRESS F9h 150 13 35 Set Max ADDRESS EXT 37h 152 ...

Page 10: ... EXT 39h 181 13 47 Write Sectors 30h 31h 183 13 48 Write Sectors s EXT 34h 185 13 49 Write Verify 3Ch vendor specific 186 14 0 Time out values 187 15 0 Appendix 189 15 1 Commands Support Coverage 189 15 2 SET FEATURES Commands Support Coverage 191 15 3 Changes from the Travelstar 80GN 192 Index 195 ...

Page 11: ...dom Vibration PSD Profile Breakpoints nonoperating 31 Table 21 Operating shock 31 Table 22 Nonoperating shock 31 Table 23 Weighted sound power 32 Table 24 Signal definitions 36 Table 25 Special signal definitions for Ultra DMA 37 Table 26 PIO cycle timings 41 Table 27 Multiword DMA cycle timings 42 Table 28 Ultra DMA cycle timings Initiating Read 43 Table 29 Ultra DMA cycle timings Host Pausing Re...

Page 12: ...ce Diagnostic command 90h 101 Table 65 Flush Cache command E7h 102 Table 66 Flush Cache command E7h 103 Table 67 Format Track command 50h 104 Table 68 Format Unit command F7h 105 Table 69 Identify Device command ECh 106 Table 70 Identify device information Part 1 of 7 107 Table 71 Identify device information Part 2 of 7 108 Table 72 Identify device information Part 3 of 7 109 Table 73 Identify dev...

Page 13: ...Set Max ADDRESS EXT Command 37h 152 Table 108 Set Multiple command C6h 154 Table 109 Sleep E6h 99h 155 Table 110 S M A R T Function Set B0h 156 Table 111 Device Attribute Data Structure 161 Table 112 Status Flag definitions 163 Table 113 Device Attribute Thresholds Data Structure 166 Table 114 Individual Threshold Data Structure 166 Table 115 Command data structure 167 Table 116 Command data struc...

Page 14: ...Travelstar 5K80 Hard Disk Drive Specification x ...

Page 15: ...3 Abbreviations Abbreviation Meaning 32 KB 32 x 1024 bytes 64 KB 64 x 1024 bytes A Ampere AC alternating current AT Advanced Technology ATA Advanced Technology Attachment BIOS Basic Input Output System C Celsius CSA Canadian Standards Association C UL Canadian Underwriters Laboratory Cyl cylinder DC Direct Current DFT Drive Fitness Test DMA Direct Memory Access ECC error correction code EEC Europe...

Page 16: ...utput ISO International Standards Organization KB 1 000 bytes Kbpi 1000 bits per inch kgf cm kilogram force centimeter KHz kilohertz LBA logical block addressing Lw unit of A weighted sound power m meter max maximum MB 1 000 000 bytes Mbps 1 000 000 bits per second MHz megahertz MLC Machine Level Control mm millimeter ms millisecond us ms microsecond No number O Output OD Open Drain Programmed Inp...

Page 17: ...Underwriters Laboratory V volt VDE Verband Deutscher Electrotechniker W watt 3 state transistor transistor tristate logic 1 4 Caution Do not apply force to the top cover See figure below Do not cover the breathing hole on the top cover See figure below Do not touch the interface connector pins or the surface of the printed circuit board This drive can be damaged by electrostatic discharge ESD Any ...

Page 18: ...Travelstar 5K80 Hard Disk Drive Specification 4 1 5 Drive handling precautions Do not press on the drive cover during handling ...

Page 19: ...Interleaved Reed Solomon Code 5 bytes per interleave On The Fly correction Segmented Buffer with write cache 8192 KB Upper 294 KB is used for firmware Fast data transfer rate up to 100 MB s Media data transfer rate max 450 Mb s Average seek time 12 ms for read Closed loop actuator servo Embedded Sector Servo Rotary voice coil motor actuator Load Unload mechanism Mechanical latch Adaptive power sav...

Page 20: ...Travelstar 5K80 Hard Disk Drive Specification 6 ...

Page 21: ...Travelstar 5K80 Hard Disk Drive Specification 7 Part 1 Functional specification ...

Page 22: ...Travelstar 5K80 Hard Disk Drive Specification 8 ...

Page 23: ...unctions AT Interface Protocol Embedded Sector Servo No ID TM formatting Multizone recording Code 96 102 ECC On The Fly Enhanced Adaptive Battery Life Extender 3 2 Head disk assembly data The following technologies are used in the drive Pico Slider Textured laminated AFC glass disk GMR head Integrated lead suspension ILS Load unload mechanism Mechanical latch ...

Page 24: ...Travelstar 5K80 Hard Disk Drive Specification 10 ...

Page 25: ... 16 16 16 16 16 Number of Sectors track 63 63 63 63 63 Number of Cylinders 16 383 16 383 16 383 16 383 16 383 Number of sectors 156 301 488 117 210 240 78 140 160 58 605 120 39 070 080 Total logical data bytes 80 026 361 856 60 011 642 880 40 007 761 920 30 005 821 440 20 003 880 960 Table 2 Data sheet Rotational Speed RPM 5400 Data transfer rates buffer to from media Mbps 450 Data transfer rates ...

Page 26: ...ck Data Zone 0 0 3 923 885 Data Zone 1 3 924 7 847 855 Data Zone 2 7 848 12 643 825 Data Zone 3 12 644 17 439 792 Data Zone 4 17 440 23 979 740 Data Zone 5 23 980 28 339 705 Data Zone 6 28 340 31 827 680 Data Zone 7 31 828 37 059 640 Data Zone 8 37 060 39 675 624 Data Zone 9 39 676 43 599 600 Data Zone 10 43 600 47 959 555 Data Zone 11 47 960 51 011 525 Data Zone 12 51 012 54 063 504 Data Zone 13 ...

Page 27: ... application The following table gives a typical value for each parameter The detailed descriptions are found in Section 5 0 Data integrity beginning on page 17 4 4 1 Command overhead Command overhead time is defined as the interval from the time that a drive receives a command to the time that the actuator starts its motion 4 4 2 Mechanical positioning 4 4 2 1 Average seek time including settling...

Page 28: ... used to correct arrival problems The average seek time is measured as the weighted average of all possible seek combinations max Σ m10 n Tnin Tnout n 1 Weighted Average max 1 max where max maximum seek length n seek length 1 to max Tnin inward measured seek time for an n track seek Tnout outward measured seek time for an n track seek 4 4 2 2 Full stroke seek time Full stroke seek is measured as t...

Page 29: ...ing mode Description Spin up Start up time period from spindle stop or power down Seek Seek operation mode Write Write operation mode Read Read operation mode Performance Idle The device is capable of responding immediately to idle media access requests All electronic components remain powered and the full frequency servo remains opera tional Active idle The device is capable of responding immedia...

Page 30: ...ing to the access pattern of the host system The transient timing from Low Power Idle mode to Standby mode is also controlled adaptively if it is allowed by Set Features Enable Adavanced Power Management subcommand Standby The device interface is capable of accepting commands The spindle motor is stopped All circuitry except the host interface is in power saving mode The execution of com mands is ...

Page 31: ...ot yet written onto the disk In order to prevent this data loss confirm the completion of the actual write operation prior to the power off by issuing a Soft reset Hard reset Flush Cache command Standby command Standby Immediate command Sleep command Confirm the command s completion 5 3 Equipment status The equipment status is available to the host system whenever the drive is not ready to read wr...

Page 32: ...hen specific conditions are met The drive does not report any auto reallocation to the host system The conditions for auto reallocation are described below 5 7 1 Nonrecovered write errors When a write operation cannot be completed after the Error Recovery Procedure ERP is fully carried out the sectors are reallocated to the spare location An error is reported to the host system only when the write...

Page 33: ...it of the byte is bad Table 12 Examples of error cases On The Fly Correctable Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Error byte for each interleave Interleave A B C D A B C D A B C D A B C D A B C D A B C D A B C D Error pattern x x x x x x x x x x x x x x x x x x x x 0 0 0 0 5 5 5 5 Error pattern x x x x x x x x x x x x 0 0 0 0 x x x x x x x x 5 5 5 5 Uncorrectable Byt...

Page 34: ...Travelstar 5K80 Hard Disk Drive Specification 20 ...

Page 35: ...bly The maximum storage period in the shipping package is one year Table 13 Environmental condition Operating conditions Temperature 5 to 55ºC See note below Relative humidity 8 to 90 non condensing Maximum wet bulb temperature 29 4ºC non condensing Maximum temperature gradient 20ºC hour Altitude 300 to 3 048 m 10 000 ft Non operating conditions Temperature 40 to 65ºC Relative humidity 5 to 95 non...

Page 36: ...gure 1 Limits of temperature and humidity Specification Environment 0 10 20 30 40 50 60 70 80 90 100 45 35 25 15 5 5 15 25 35 45 55 65 Temperature degC Relative Humidity Operating Non Operating WetBulb 40 C WetBulb29 4 C 41 C 95 31 C 90 65 C 23 55 C 15 ...

Page 37: ...current of up to 45 mA p p is applied through a 50 ohm resistor connected to any two mounting screw holes 6 1 4 Magnetic fields The disk drive will withstand radiation and conductive noise within the limits shown below The test method is defined in the Noise Susceptibility Test Method specification P N 95F3944 6 2 DC power requirements Connection to the product should be made in a safety extra low...

Page 38: ...6 2 1 Power consumption efficiency Note Power consumption efficiency is calculated as Power Consumption of Low Power Idle in Watts Capacity GB 6 3 Reliability 6 3 1 Data Reliability Probability of not recovering data is 1 in 1013 bits read ECC implementation On the fly correction performed as a part of read channel function recovers up to 20 symbols of error in one sector 1 symbol is 8 bits Active...

Page 39: ...n the top cover of the drive should not be covered Force should not be applied to the cover of the drive The specified power requirements of the drive should be satisfied The drive frame should be grounded electrically to the system through four screws The drive should be mounted with the recommended screw depth and torque The interface physical and electrical requirements of the drive should sati...

Page 40: ...rive is as follows Step 1 Issue one of the following commands Standby Standby immediate Sleep Note Do not use the Flush Cache command for the power off sequence because this command does not invoke Unload Step 2 Wait until the Command Complete status is returned In a typical case 350 ms are required for the command to finish completion however the BIOS time out value needs to be 30 seconds conside...

Page 41: ...ds through the interface not by power cycling the drive Simple power cycling of the drive invokes the emergency unload mechanism and subjects the HDD to nontypical mechan ical stress Power cycling testing may be required to test the boot up function of the system In this case Hitachi recommends that the power off portion of the cycle contain the sequence specified in Section 6 3 6 2 Required Power...

Page 42: ... 1 Physical dimensions and weight The following table lists the dimensions of the drive Table 17 Physical dimensions and weight 80GB 60GB models 40GB 30GB 20GB models Height mm 9 5 0 2 9 5 0 2 Width mm 69 85 0 25 69 85 0 25 Length mm 100 2 0 25 100 2 0 25 Weight grams maximum 102 95 ...

Page 43: ...n page 51 Connector specifications are included in Section 7 2 Interface connector on page 35 6 4 4 Mounting orientation The drive will operate in all axes six directions and will stay within the specified error rates when tilted 5degrees from these positions Performance and error rate will stay within specification limits if the drive is operated in the other permissible ori entations from which ...

Page 44: ...nting hardware to mount the drive securely enough to prevent excessive motion or vibration of the drive at seek operation or spindle rotation 6 4 5 Load unload mechanism The head load unload mechanism is provided to protect the disk data during shipping movement or storage Upon power down a head unload mechanism secures the heads at the unload position See Section 6 5 4 Nonoperating shock on page ...

Page 45: ...bration The test consists of 30 minutes of random vibration using the power spectral density PSD levels below The vibration test level is 6 57 m sec2 RMS Root Mean Square 0 67 G RMS 6 5 1 2 Swept sine vibration 6 5 2 Nonoperating vibration The disk drive withstands the vibration levels described below without any loss or permanent damage Table 18 Random vibration PSD profile breakpoints operating ...

Page 46: ...al of 60 There must be a minimum delay of 3 seconds between shock pulses The disk drive will operate without a hard error while subjected to the following half sine shock pulse The input level shall be applied to the normal disk drive subsystem mounting points used to secure the drive in a normal system 6 5 4 Nonoperating shock The drive withstands the following half sine shock pulse without any d...

Page 47: ...n disks spinning track following unit ready to receive and respond to control line com mands Operating mode Continuous random cylinder selection and seek operation of the actuator with a dwell time at each cylinder The seek rate for the drive is calculated with the following formula Ns 0 4 Tt T1 where Ns average seek rate in seeks s Tt published seek time from one random track to another without i...

Page 48: ...15 RFI Japan VCCI Requirements of Hitachi products EU EMC Directive Technical Requirements and Conformity Assessment Procedures 6 8 1 CE mark The product is certified for compliance with EC directive 89 336 EEC The EC marking for the certification appears on the drive 6 8 2 C TICK mark The drive complies with the Australian EMC standard Limits and methods of measurement of radio disturbance charac...

Page 49: ...bility The printed circuit boards used in this drive are made of material with a UL recognized flammability rating of V 1 or better The flammability rating is marked or etched on the board Except for small mechanical parts all other parts not considered electrical components are made of material with a UL recognized flammability rating of V 1 or better 6 9 5 Secondary circuit protection This produ...

Page 50: ...Travelstar 5K80 Hard Disk Drive Specification 36 ...

Page 51: ...hment is designed to mate with Dupont part number 69764 044 or equivalent The figure below and Figure 2 Mounting hole locations on page 29 show the connector and pin location Figure 3 Interface connector pin assignments Figure 1 Interface connector pin assignments Pin position 20 is left blank for correct connector insertion Pin positions A B C and D are used for the drive address setting Refer to...

Page 52: ...TL 02 GND 03 DD07 I O 3 state 04 DD08 I O 3 state 05 DD06 I O 3 state 06 DD09 I O 3 state 07 DD05 I O 3 state 08 DD10 I O 3 state 09 DD04 I O 3 state 10 DD11 I O 3 state 11 DD03 I O 3 state 12 DD12 I O 3 state 13 DD02 I O 3 state 14 DD13 I O 3 state 15 DD01 I O 3 state 16 DD14 I O 3 state 17 DD00 I O 3 state 18 DD15 I O 3 state 19 GND 20 Key 21 DMARQ O 3 state 22 GND 23 DIOW I TTL 24 GND 25 DIOR I...

Page 53: ...ected RESET This line is used to reset the drive It shall be kept at a Low logic state during power up and kept High thereafter DIOW The rising edge of this signal holds data from the data bus to a register or data register of the drive DIOR When this signal is low it enables data from a register or data register of the drive onto the data bus The data on the bus shall be latched on the rising edg...

Page 54: ...DIAG within 30 seconds to indicate that it is no longer busy and is able to provide status Following the receipt of a valid Execute Drive Diagnostics command device 1 shall negate PDIAG within 1 ms to indicate to device 0 that it is busy and has not yet passed its drive diagnostics If device 1 is present then device 0 shall wait up to 6 seconds from the receipt of a valid Execute Drive Diagnostics...

Page 55: ...ra DMA data in transfers The host may negate HDMARDY to pause an Ultra DMA data in transfer HSTROBE Ultra DMA This signal is used only for Ultra DMA data transfers between host and drive The signal HSTROBE is the data out strobe signal from the host for an Ultra DMA data out transfer Both the rising and falling edge of HSTROBE latch the data from DD 15 0 into the device The host may stop toggling ...

Page 56: ... Inputs Voltage Input high ViH Voltage input low ViL 2 0 V min 5 5 V max 0 5 V min 0 8 V max Outputs Voltage output high at IoH min VoH Voltage output low at IoL min VoL 2 4 V min 0 5 V max Current Driver Sink Current IoL Driver Source Current IoH 16mA min 400 µA min PARAMETER DESCRIPTION Min µs Max µs t1 RESET high to Not BUSY 9 5 t10 RESET low width 25 t10 t1 RESET BUSY ...

Page 57: ...p 25 t2 DIOR DIOW pulse width 70 t2i DIOR DIOW recovery time 25 t3 DIOW data setup 20 t4 DIOW data hold 10 t5 DIOR data setup 20 t6 DIOR data hold 5 t6z DIOR data tristate 30 t9 DIOR DIOW to address valid hold 10 tRD Read data valid to IORDY active 0 tA IORDY setup width 35 tB IORDY pulse width 1 250 IOCS16 t9 t0 t2 t2i t3 t4 t5 t8 t7 t1 tB Read data DD 15 0 DIOR DIOW CS 1 0 DA 2 0 W rite data DD ...

Page 58: ...ime 120 tD DIOR DIOW asserted pulse width 70 tE DIOR data access 50 tF DIOR data hold 5 tG DIOR DIOW data setup 20 tH DIOW data hold 10 tI DMACK to DIOR DIOW setup 0 tJ DIOR DIOW to DMACK hold 5 tKR tKW DIOR negated pulse width DIOW negated pulse width 25 tLR tLW DIOR to DMARQ delay DIOW to DMARQ delay 35 tZ DMACK to read data released 25 WRITEDD 15 0 READDD 15 0 DMACK DMARQ DIOR DIOW t0 tLR tLW t...

Page 59: ...0 20 tENV Envelope time 20 70 20 70 20 70 20 55 20 55 20 50 tZIORDY Minimum time before driv ing IORDY 0 0 0 0 0 0 tFS First DSTROBE time 0 230 0 200 0 170 0 130 0 120 0 90 tCYC Cycle time 112 73 54 39 25 16 8 t2CYC Two cycle time 230 154 115 86 57 38 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 tZAD Drivers to assert 0 0 0 0 0 0 tDS Data setup time at host 15 10 7 7 5 ...

Page 60: ...re data words after HDMARDY is negated Table 29 Ultra DMA cycle timings Host Pausing Read PARAMETER DESCRIPTION MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns tSR DSTROBE to HDMARDY time 50 30 20 tRFS HDMARDY to final DSTROBE time 75 70 60 60 60 50 DSTROBE HDMARDY DMACK DMARQ tSR STOP tRFS ...

Page 61: ... 0 150 0 150 0 150 0 100 0 100 0 75 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 tZAH Minimum delay time required for output 20 20 20 20 20 20 tMLI Interlock time with mini mum 20 20 20 20 20 20 tDS CRC word setup time at device 15 10 7 7 5 4 tDH CRC word hold time at device 5 5 5 5 5 4 6 tACK Hold time for DMACK negation 20 20 20 20 20 20 tIORDYZ Maximum time before re...

Page 62: ... 150 0 150 0 100 0 100 0 75 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 tZAH Maximum delay time required for output 20 20 20 20 20 20 tMLI Interlock time with mini mum 20 20 20 20 20 20 tDS CRC word setup time at device 15 10 7 7 5 4 tDH CRC word hold time at device 5 5 5 5 5 4 6 tACK Hold time for DMACK negation 20 20 20 20 20 tIORDYZ Maximum time before releasing IOR...

Page 63: ...ACK 20 20 20 20 20 20 tENV Envelope time 20 70 20 70 20 70 20 55 20 55 20 55 tZIORDY Minimum time before driv ing IORDY 0 0 0 0 0 0 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tCYC Cycle time 112 73 54 39 25 16 8 t2CYC Two cycle time 230 154 115 86 57 38 tDS Data setup time at device 15 10 7 7 5 4 tDH Data Hold time at device 5 5 5 5 5 4 6 HSTROBE DDMARDY DMACK DMARQ STOP tUI tAC...

Page 64: ...e data words after DDMARDY is negated Table 33 Ultra DMA cycle timing Device Pausing Write PARAMETER DESCRIPTION MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns tSR HSTROBE to DDMARDY time 50 30 20 tRFS DDMARDY to final HSTROBE time 75 70 60 60 60 50 HSTROBE DDMARDY DMACK DMARQ tSR STOP tRFS ...

Page 65: ...0 60 50 tRP Ready to pause time 160 125 100 100 100 85 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tMLI Interlocking time with mini mum 20 20 20 20 20 20 tDS CRC word setup time at device 15 10 7 7 5 4 tDH CRC word hold time at device 5 5 5 5 5 4 6 tACK Hold time for DMACK negation 20 20 20 20 20 20 tIORDYZ Maximum time before releasing IORDY 20 20 20 20 20 20 HSTROBE DDMARDY DMA...

Page 66: ...dge to assertion of STOP 50 50 50 50 50 50 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tMLI Interlock time with mini mum 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 4 tCH CRC word hold time at device 5 5 5 5 5 4 6 tACK Hold time for DMACK 20 20 20 20 20 20 tIORDYZ Maximum time before releasing IORDY 20 20 20 20 20 20 HSTROBE DDMARDY DMACK DMARQ STOP tMLI DD 15...

Page 67: ...er no jumper is used Setting 2 Device 1 Slave Setting 3 Cable Select Setting 4 Do not attach a jumper here Setting 5 Do not attach a jumper here The default setting at shipment is Setting 1 no jumper When pin C is grounded the drive does not spin up at POR When the drive address is Cable Select the address depends on the condition of pin 28 of the AT interface cable If pin 28 is ground or low the ...

Page 68: ...CS0 is used to address the Command Block registers while the CS1 is used to address Con trol Block registers The following table shows the I O address map CS0 CS1 DA02 DA01 DA00 DIOR 0 Read DIOW 0 Write Command Block Registers 0 1 0 0 0 Data Reg Data Reg 0 1 0 0 1 Error Reg Features Reg 0 1 0 1 0 Sector count Reg Sector count Reg 0 1 0 1 1 LBA low Reg LBA low Reg 0 1 1 0 0 LBA mid Reg LBA mid Reg ...

Page 69: ...Travelstar 5K80 Hard Disk Drive Specification 53 Part 2 Interface specification ...

Page 70: ...Travelstar 5K80 Hard Disk Drive Specification 54 ...

Page 71: ...001 with certain limitations described in Section 9 0 Deviations from standard on page 57 The drive supports the following functions as Vendor Specific Functions Address Offset Feature Format Unit Function SENSE CONDITION command 8 2 Terminology Device The Travelstar 5K80 drive Host Host indicates the system that the device is attached to First Command The first command which is executed after the...

Page 72: ...Travelstar 5K80 Hard Disk Drive Specification 56 ...

Page 73: ...Sector Count register shall be used to determine the time programmed into the Standby timer If the Sector Count register is zero the Standby timer is automatically set to 109 minutes Write Verify WRITE VERIFY command does not include read verification after write operation The function is the same as WRITE SECTORS command S M A R T Return Status S M A R T RETURN STATUS subcommand does not check ad...

Page 74: ...Travelstar 5K80 Hard Disk Drive Specification 58 ...

Page 75: ...ate status Addresses Functions CS0 CS1 DA2 DA1 DA0 READ DIOR WRITE DIOW N N x x x Data bus high impedence Not used Control block registers N A 0 x x Data bus high impedance Not used N A 1 0 x Data bus high impedance Not used N A 1 1 0 Alternate Status Device Control N A 1 1 1 Device Address Not used Command block registers A N 0 0 0 Data Data A N 0 0 1 Error Register Features A N 0 1 0 Sector Coun...

Page 76: ...mmediately after this register is written The command set is shown in Table 58 Command Set 1 of 2 on page 97 and Table 59 Command Set 2 of 2 on page 98 All other registers required for the command must be set up before writ ing to the Command Register 10 3 Data Register This register is used to transfer data blocks between the device data buffer and the host It is also the register through which s...

Page 77: ...t 5 ms before setting RST 0 IEN Interrupt Enable When IEN 0 and the device is selected the device interrupts to the host will be enabled When IEN 1 or the device is not selected the device interrupts to the host will be disabled 7 6 5 4 3 2 1 0 HIZ WTG H3 H2 H1 H0 DS1 DS0 Bit Definitions HIZ High Impedance This bit is not a device and will always be in a high impedance state WTG Write Gate This bi...

Page 78: ...n DRV 0 device 0 Master is selected When DRV 1 device 1 Slave is selected HS3 HS2 HS1 HS0 These contain bits 24 27 of the LBA At command completion these bits are updated to reflect the current LBA bits 24 27 7 6 5 4 3 2 1 0 CRC UNC 0 IDNF 0 ABRT TK0N AMN ICRCE CRC Interface CRC Error When CRC 1 it indicates that a CRC error has occurred on the data bus during a Ultra DMA transfer UNC Uncorrectabl...

Page 79: ...contains Bits 8 15 At the end of the command this register is updated to reflect the current LBA Bits 8 15 When 48 bit addressing commands are used the most recently written content contains LBA Bits 8 15 and the previous content contains Bits 32 39 10 12 Sector Count Register This register contains the number of sectors of data requested to be transferred on a read or write operation between the ...

Page 80: ...pleted and the device head is settled over a track Bit DSC is set to 0 by the device just before a Seek begins When an error occurs this bit is not changed until the Status Register is read by the host and at that time the bit again indicates the current Seek complete status When the device enters into or is in Standby mode or Sleep mode this bit is set by device in spite of the drive not spinning...

Page 81: ...ft reset Aborting Host interface o o Aborting Device operation 1 1 Initialization of hardware o x x Internal diagnostic o x x Starting spindle motor 6 x x Initialization of registers 2 o o o DASP handshake o o x PDIAG handshake o o o Reverting programmed parameters to default Number of CHS set by Initialize Device Parameters Multiple mode Write Cache Read look ahead ECC bytes Volatile max address ...

Page 82: ...wer on hard reset or the Execute Device Diagnostic command are shown in the following table Table 44 Default Register Values Register Default Value Error Diagnostic Code Sector Count 01h LBA Low 01h LBA Mid 00h LBA High 00h Device A0h Status 50h Alternate Status 50h Table 45 Diagnostic codes Code Description 01h No error detected 02h Formatter device error 03h Sector buffer error 04h ECC circuitry...

Page 83: ...bit whenever it is ready to accept commands Device 0 may assert DASP to indicate device activity If Device 1 is not present Device 0 does not Assert DASP at POR Soft Reset If Device 1 is present Device 0 shall read PDIAG to determine when it is valid to clear the BSY bit and whether Device 1 has reset without any errors otherwise Device 0 shall simply reset and clear the BSY bit DASP is asserted b...

Page 84: ...nload is intended to be invoked in rare situations Because this operation is inherently uncontrolled it is more mechanically stressful than a normal unload A single emergency unload operation is more stressful than 100 normal unloads Use of emergency unload reduces the start stop life of the drive at a rate at least 100 times faster than that of normal unload and may damage the drive 11 4 3 Requir...

Page 85: ...umbered from 1 to the maximum value allowed by the current CHS translation mode but cannot exceed 255 0FFh Heads are numbered from 0 to the maximum value allowed by the current CHS translation mode but cannot exceed 15 0Fh Cylinders are numbered from 0 to the maximum value allowed by the current CHS translation mode but cannot exceed 65535 0FFFFh When the host selects a CHS translation mode using ...

Page 86: ...ed to move a device out of sleep mode When a device exits sleep mode it will enter standby mode The Standby and Standby Immediate commands move a device to standby mode immediately from the active or idle modes The standby command also sets the standby timer count 11 6 3 Standby Sleep command completion time 1 Confirm the completion of writing cached data in the buffer to media 2 Unload the heads ...

Page 87: ...ers and the validity of INTRQ is guaranteed for two seconds after the Sleep command is completed After this period the contents of interface registers may be lost Since the contents of interface registers may be invalid the host should NOT check the Status register nor the Alternate Status register prior to issuing a soft reset to wake up a device 11 6 7 Initial Power Mode at Power On After power ...

Page 88: ...nsumption is 45 55 less than that of Performance Idle mode Additional electronics are powered off and the head is parked near the mid diameter of the disk without servoing Recovery time to Active mode is about 20 ms 11 7 3 Low Power Idle Mode Power consumption is 60 65 less than that of Performance Idle mode The heads are unloaded on the ramp but the spindle is still rotated at the full speed Reco...

Page 89: ... that particular device The specific set of attributes being used and the identity of these attributes is vendor specific and proprietary 11 8 2 Attribute values Attribute values are used to represent the relative reliability of individual performance or calibration attributes Higher attribute values indicate that the analysis algorithms being used by the device are predicting a lower proba bility...

Page 90: ...ed 11 9 2 Security level The following security levels are provided Security Set Password F1 h Security Unlock F2 h Security Erase Prepare F3 h Security Erase Unit F4 h Security Freeze Lock F5 h Security Disable Password F6 h Device Locked Mode The device disables media access commands after power on Media access commands are enabled by either a Security Unlock command or a Security Erase Unit com...

Page 91: ... FFFFh are reserved 11 9 4 1 Master Password setting The system manufacturer or dealer can set an initial Master Password using the Security Set Password command without enabling the Device Lock Function 11 9 4 2 User Password setting When a User Password is set the device will automatically enter lock mode the next time the device is powered on Table 48 Initial setting Master Password When the Ma...

Page 92: ...s to the commands in Table 51 Command table for device lock operation on page 78 POR Device Locked mode Unlock CMD Command 1 Command 1 Password Erase Unit Password Match Reject Complete Complete Erase Unit Lock function Disable Normal operation All commands are available Freeze Lock command Enter Device Frozen mode Normal Operation expect Set Password Disable Password Erase Unit Unlock commands En...

Page 93: ...TY UNLOCK command has an attempt limit the purpose of which is to prevent someone from attempting to unlock the drive with various passwords numerous times The device counts the password mismatch If the password does not match the device counts it without distinguishing the Master password and the User password If the count reaches 5 EXPIRE bit bit 4 of Word 128 in Identify Device information is s...

Page 94: ...o o o S M A R T Enable Disable automatic off line o o o Initialize Device Parameters o o o S M A R T Enable Disable Attribute Autosave o o o Read Buffer o o o S M A R T Enable Operations o o o Read DMA x o o S M A R T Exectue Off line Immdeiate o o o Read DMA EXT x o o S M A R T Read Attribute Values o o o Read Long x o o S M A R T Read Attribute Thresholds o o o Read Multiple x o o S M A R T Read...

Page 95: ...the device has been tested to have a capacity of 536 MB flagging the media defects not visible by the system 2 Preparing drives at system manufacturer Special utility software is required to define the size of the protected area and to store the data in it The sequence is Issue Read Native Max ADDRESS command to get the real device max of LBA CYL Returned value shows that native device Max LBA is ...

Page 96: ...is command requests a transfer of a single sector of data from the host The following figure defines the content of this sector of information The password is retained by the device until the next power cycle When the device accepts this command the device is in Set Max Unlocked mode The Set Max LOCK command allows the host to disable the Set Max commands except Set Max UNLOCK and Set Max FREEZE L...

Page 97: ...an be removed by a Set Max Address command to move the Set Max pointer to the end of the drive But any commands which access sectors across the original native maximum LBA are rejected with error even if this protection is removed by a Set Max Address command 11 11 1 Enable Disable Address Offset Mode Subcommand code 09h Enable Address Offset Mode offsets address Cylinder 0 Head 0 Sector 1 LBA 0 t...

Page 98: ... Data Identify Device data word 83 bit 7 indicates the device supports the Address Offset Feature Identify Device data word 86 bit 7 indicates the device is in Address Offset mode 11 11 3 Exceptions in Address Offset Mode Any commands which access sectors across the original native maximum LBA are rejected with error even if the access protection is removed by a Set Max Address command Read Look A...

Page 99: ...r of seeks is large this overhead can be ignored Table 55 Seek overlap 11 13 Write Cache function Write cache is a performance enhancement whereby the device reports completion of the write command Write Sector s and Write Multiple to the host as soon as the device has received all of the data in its buffer The device assumes responsibility to write the data subsequently onto the disk Writing data...

Page 100: ...nder 0 The conditions for auto reallocation are described below Nonrecovered write errors When a write operation can not be completed after the Error Recovery Procedure ERP is fully carried out the sector s are reallocated to the spare location An error is reported to the host system only when the write cache is disabled and the auto reallocation fails If the number of available spare sectors reac...

Page 101: ...nt location The host may read the previous content of the Features the Sector Count the LBA Low Mid High registers by first setting the High Order Bit HOB bit 7 of the Device control register to one and then reading the desired register If HOB in the Device Control register is cleared to zero the host reads the most recently written content when the register is read A write to any Command Block re...

Page 102: ...Travelstar 5K80 Hard Disk Drive Specification 86 ...

Page 103: ...rrupts are cleared when the host reads the Status Register issues a reset or writes to the Command Register See Section 14 0 Time out values on page 191 for the device time out values 12 1 Data In commands The following are Data In commands Device Configuration Identify Identify Device Read Buffer Read Long Read Multiple Read Multiple EXT Read Sector s Read Sector s EXT S M A R T Read Attribute Va...

Page 104: ...ng BSY 0 ERR 1 ABT 1 and inter rupting the host If an error occurs the device sets BSY 0 ERR 1 and DRQ 1 The device then stores the error status in the Error Register and interrupt the host The registers will contain the location of the sector in error The error location will be reported using CHS mode or LBA mode The mode is decided by the mode select bit bit 6 of the Device Head register upon is...

Page 105: ...ncluding ECC bytes via the Data Register c The device sets BSY 1 after it has received the sector d After processing the sector of data the device sets BSY 0 and interrupts the host e In response to the interrupt the host reads the Status Register f The device clears the interrupt in response to the Status Register being read The Write Multiple command transfers one block of data for each interrup...

Page 106: ...ve S M A R T Enable Disable Automatic Off line S M A R T Enable Operations S M A R T Execute Off line Immediate S M A R T Return Status S M A R T Save Attribute Values Standby Standby Immediate Execution of these commands involves no data transfer a The host writes any required parameters to the Features Sector Count LBA High LBA Mid LBA Low and Device Registers b The host writes the command code ...

Page 107: ...tor commands The host resets the DMA channel prior to reading status from the device The DMA protocol allows high performance multitasking operating systems to eliminate processor overhead asso ciated with PIO transfers 1 The host initializes the Slave DMA channel 2 The host writes any required parameters to the Features Sector Count LBA High LBA Mid LBA Low and Device registers 3 The host writes ...

Page 108: ...Travelstar 5K80 Hard Disk Drive Specification page 92 ...

Page 109: ...1 1 0 0 0 1 1 3 Idle 97 1 0 0 1 0 1 1 1 3 Idle Immediate E1 1 1 1 0 0 0 0 1 3 Idle Immediate 95 1 0 0 1 0 1 0 1 3 Initialize Device Parameters 91 1 0 0 1 0 0 0 1 1 Read Buffer E4 1 1 1 0 0 1 0 0 4 Read DMA C8 1 1 0 0 1 0 0 0 4 Read DMA C9 1 1 0 0 1 0 0 1 4 Read DMA EXT 25 0 0 1 0 0 1 0 1 1 Read Long 22 0 0 1 0 0 0 1 0 1 Read Long 23 0 0 1 0 0 0 1 1 1 Read Multiple C4 1 1 0 0 0 1 0 0 3 Read Native ...

Page 110: ...Execute Off line Immediate B0 1 0 1 1 0 0 0 0 1 S M A R T Read Attribute Values B0 1 0 1 1 0 0 0 0 1 S M A R T Read Attribute Thresholds B0 1 0 1 1 0 0 0 0 1 S M A R T Read Log Sector B0 1 0 1 1 0 0 0 0 3 S M A R T Return Status B0 1 0 1 1 0 0 0 0 3 S M A R T Save Attribute Values B0 1 0 1 1 0 0 0 0 2 S M A R T Write Log Sector B0 1 0 1 1 0 0 0 0 3 Standby E2 1 1 1 0 0 0 1 0 3 Standby 96 1 0 0 1 0...

Page 111: ... Operations B0 D9 S M A R T Return Status B0 DA S M A R T Enable Disable Automatic Off line B0 DB Set Features Enable Write Cache EF 02 Set Transfer mode EF 03 Enable Advanced Power Management feature EF 05 Enable Address Offset mode EF 09 40 bytes of ECC apply on Read Write Long EF 44 Disable read look ahead feature EF 55 Disable reverting to power on defaults EF 66 Disable write cache EF 82 Disa...

Page 112: ...input parameter Out put registers 0 This indicates that the bit must be set to 0 1 This indicates that the bit must be set to 1 D The device number bit This indicates that the device number bit of the Device Register should be specified Zero selects the master device and one selects the slave device H Head number This indicates that the head number part of the Device Head Register is an output par...

Page 113: ...r if the spindle motor is at speed and the device is not in Standby or Sleep mode Other wise the Sector Count Register is set to 0 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count V V V V V V V V LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 D Device Command 1 1 ...

Page 114: ...e Con figuration Overlay settings After successful execution of a DEVICE CONFIGURATION FREEZE LOCK com mand all DEVICE CONFIGURATION SET DEVICE CONFIGURATION FREEZE LOCK DEVICE CONFIGURATION IDENTIFY and DEVICE CONFIGURATION RESTORE commands are aborted by the device The DEVICE CONFIGURATION FREEZE LOCK condition shall be cleared by a power down The DEVICE CONFIGURATION FREEZE LOCK condition shall...

Page 115: ...t If a bit is set in the overlay transmitted by the device that is not set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command no action is taken for that bit The format of the overlay transmitted by the device is described in the table in Table 62 Device Configuration Overlay Data structure on page 100 The restrictions on changing these bits is described in the text following tha...

Page 116: ... below are supported 4 1 Ultra DMA mode 4 and below are supported 3 1 Ultra DMA mode 3 and below are supported 2 1 Ultra DMA mode 2 and below are supported 1 1 Ultra DMA mode 1 and below are supported 0 1 Ultra DMA mode 0 is supported 3 6 Maximum LBA address 7 Command set feature set supported 15 8 Reserved 7 1 Host Protected Area feature set supported 6 4 Reserved 3 1 Security feature set support...

Page 117: ...o this command Instead the register contains a diagnostic code See Table 46 Diagnostic codes on page 70 for the definition Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 Device Command 1 0 0 1 0 0 0 0 Status see bel...

Page 118: ... written to the disk media Return a successful completion Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 D Device Command 1 1 1 0 0 1 1 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1...

Page 119: ...ter 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current Sector Count HOB 0 Previous HOB 1 LBA Low Current LBA Low HOB 0 Previous HOB 1 LBA Mid Current LBA Mid HOB 0 Previous HOB 1 LBA High Current LBA High HOB 0 Previous HOB 1 Device Head D Device Head Command 1 1 1 0 1 0 1 0 Status See below Error Register St...

Page 120: ...A mode this reg ister specifies that LBA address bits 24 27 are to be formatted L 1 Input parameters from the device LBA Low In LBA mode this register specifies the current LBA address bits as 0 7 L 1 LBA High Mid In LBA mode this register specifies the current LBA address bits as 8 15 Mid and bits 16 23 High H In LBA mode this register specifies the current LBA address bits as 24 27 L 1 In LBA mo...

Page 121: ...rior to the Format Unit command If the device receives a Format Unit command without a prior Security Erase Prepare command the device aborts the Format Unit command If the Feature register is NOT 11h the device returns an Abort error to the host This command does not request a data transfer Output parameters to the device Feature This indicates the Destination code for this command 11H The merge ...

Page 122: ...formation in Table 70 beginning on page 107 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 D Device Command 1 1 1 0 1 1 0 0 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 I...

Page 123: ...plete 1 1 1 hard sectored 0 0 Reserved 01 Note 1 Number of cylinders in default translate mode 02 xxxxH Specific configuration C837h SET FEATURES subcommand is not required to spin up and IDENTIFY DEVICE response is complete 37C8h SET FEATURES subcommand is required to spin up and IDENTIFY DEVICE response is complete 03 Note 1 Number of heads in default translate mode 04 05 0 Reserved 06 003FH Num...

Page 124: ...iming mode Refer Word 62 and 63 53 0007H Validity flag of the word 15 3 0 Reserved 2 1 1 Word 88 is Valid 1 1 1 Word 64 70 are Valid 0 1 1 Word 54 58 are Valid 54 XXXXH Number of current cylinders 55 XXXXH Number of current heads 56 XXXXH Number of current sectors per track 57 58 XXXXH Current capacity in sectors Word 57 specifies the low word of the capacity 59 0XXXH Current Multiple setting Bit ...

Page 125: ... time in nanoseconds 240 ns 8 3 MB s 68 0078H Minimum PIO Transfer Cycle Time With IORDY Flow Control 15 0 78h Cycle time in nanoseconds 120 ns 16 6 MB s 69 79 0000H Reserved 80 007CH Major version number ATA 1 2 3 and ATA ATAPI 4 5 6 81 0019h Minor version number ATA ATAPI 6 T13 1410D Revision 3a 82 746BH Command set supported 15 0 Reserved 14 1 1 NOP command supported 13 1 1 READ BUFFER command ...

Page 126: ...Feature Set supported 3 1 1 Advanced Power Management Feature Set supported 2 0 1 CFA Feature Set supported 1 0 1 READ WRITE DMA QUEUED supported 0 0 1 DOWNLOAD MICROCODE command supported 84 4023H Command set feature supported extension 15 0 Always 14 1 Always 13 6 0 Reserved 5 1 1 General Purpose Logging feature set supported 4 2 0 Reserved 1 1 1 SMART self test supported 0 1 1 SMART error loggi...

Page 127: ... Power management Feature Set enabled 2 0 1 CFA Feature Set supported 1 0 1 READ WRITE DMA QUEUED command supported 0 0 1 DOWNLOAD MICROCODE command supported 87 4023H Command set feature enabled 15 0 Always 14 1 Always 13 6 0 Reserved 5 1 1 General Purpose Logging feature set supported 4 2 0 Reserved 1 1 1 SMART self test supported 0 1 1 SMART error logging supported 88 XX3FH Ultra DMA Transfer m...

Page 128: ... X How Device 1 determined the device number 00 Reserved 01 a jumper was used 10 the CSEL signal was used 11 some other method used or method unknown 8 1 Always 7 0 Device 0 hardware reset result Device 1 clears these bits to 0 7 0 Reserved 6 X 1 Semi duplex mode is enabled 5 X 1 Device 0 detected Device 1 4 X 1 Device 1 passed diagnostic 3 X 1 Device 0 passed diagnostic 2 1 X how Device 0 determi...

Page 129: ...e supported 4 0 1 Security count expired 3 0 1 Security Frozen 2 0 1 Security Locked 1 0 1 Security Enabled 0 0 1 Security Support 129 000XH Current Set Feature Option Bit assignments 15 4 0 Reserved 3 X 1 Auto reassign enabled 2 X 1 Reverting enabled 1 X 1 Read Look ahead enabled 0 X 1 Write Cache enabled 130 XXXXH Reserved 131 000XH Initial Power Mode Selection Bit assignments 15 2 0 Reserved 1 ...

Page 130: ...sectors 950F8B0h HTS548060M9AT00 Number of cylinders 3FFFh Number of heads 10h Buffer size 3D8Ah 7 887KB Total number of user addressable sectors 6FC7C80h HTS548040M9AT00 Number of cylinders 3FFFh Number of heads 10h Buffer size 3D8Ah 7 887KB Total number of user addressable sectors 4A85300h HTS548030M9AT00 Number of cylinders 3FFFh Number of heads 10h Buffer size 3D8Ah 7 887KB Total number of use...

Page 131: ...or Count This indicates the Time out Parameter If it is zero the time out interval Standby Timer is NOT disabled and the time out interval is set automatically for 109 minutes If it is other than zero the time out interval is set for Time out Parameter 5 seconds The device will enter Standby mode automatically if the time out interval expires with no device access from the host The time out interv...

Page 132: ...to respond to the host commands immediately The Idle Immediate command will not affect the auto power down time out parameter Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 D Device Command 1 1 1 0 0 0 0 1 Status se...

Page 133: ...n of CCh is set Output parameters to the device Sector Count This indicates the number of sectors per track Zero 0 indicates 0 sectors per track instead of 256 sectors per track It means that there are no sectors per track H This indicates the number of heads minus 1 per cylinder The minimum is 0 and the maxi mum is 15 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3...

Page 134: ...fer command The contents of the sector may be different if any reads or writes have occurred since the Write Buffer command was issued Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 D Device Command 1 1 1 0 0 1 0 0 ...

Page 135: ...t sector to be transferred L 0 In LBA mode this register specifies that LBA address bits 0 7 are to be transferred L 1 LBA High Mid This indicates the cylinder number of the first sector to be transferred L 0 In LBA mode this register specifies LBA address bits 8 15 Mid and 16 23 High to be transferred L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this ...

Page 136: ...dicates the sector number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 0 7 L 1 LBA High Low This indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Mid and bits16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains ...

Page 137: ...s 15 8 If 0000h in the Sector Count register is specified 65 536 sectors will be transferred LBA Low Current LBA 7 0 LBA Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 LBA High Current LBA 23 16 LBA High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High ...

Page 138: ... Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 139: ...BA Low This indicates the sector number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 0 7 L 1 LBA High Mid This indicates the cylinder number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 24 27 L...

Page 140: ...e this register contains current LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 The device internally uses 40 bytes of ECC data on all data written or read from the disk The 4 byte mode of oper ation is provided by means of an emulation Use of the 40 byte ECC mode is recommended for testi...

Page 141: ... L 0 In LBA mode this register contains LBA bits 8 15 Mid 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains LBA bits 24 27 L 1 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred This number is zero unless an unrecoverable error occurs LBA Low This indicates the secto...

Page 142: ...ndicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Mid 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 ...

Page 143: ...s of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error Table 86 Read Multiple EXT 29h Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previou...

Page 144: ...ister contains the native max LBA bits 0 7 L 1 In CHS mode this register contains the native max LBA Low L 0 LBA High Mid In LBA mode this register contains the native max LBA bits 8 15 Mid and bits 16 23 High L 1 In CHS mode this register contains the native max cylinder number L 0 H In LBA mode this register contains the native max LBA bits 24 27 L 1 In CHS mode this register contains the native...

Page 145: ... max areas LBA High HOB 1 LBA 47 40 of the address of the Native max areas Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current Sector Count HOB 0 Previous HOB 1 LBA Low Current LBA Low HOB 0 V V V V V V V V Previous HOB 1 V V V V V V V V LBA...

Page 146: ...the retry bit this bit is ignored Input parameters from the device Sector Count This is the number of requested sectors not transferred This will be zero unless an unre coverable error occurs LBA Low This is the sector number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 0 7 L 1 LBA High Low This is the cylinder number of the last transferred sector L 0...

Page 147: ...Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 LBA High Current LBA 23 16 LBA High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V V...

Page 148: ... Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 149: ...LBA mode this register contains the LBA bits 8 15 Mid and bits 16 23 High L 1 H This is the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This is the retry bit this bit is ignored Input parameters from the device Sector Count This is the number of requested sectors not transferred This number will be zero unless an unrecoverable e...

Page 150: ... the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Mid and bits 16 23 High L 1 H This is the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 151: ...transferred LBA Low Current LBA 7 0 LBA Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 LBA High Current LBA 23 16 LBA High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sec...

Page 152: ... Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 153: ... be set in the Error Register Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 D Device Command 0 0 0 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY R...

Page 154: ...formation for Security Disable Password command The device will compare the password sent from this host with that specified in the control word Identifier Zero indicates that the device should check the supplied password against the user pass word stored internally One indicates that the device should check the given password against the master password stored internally Command Block Output Regi...

Page 155: ...Command This com mand is to prevent accidental erasure of the device This command does not request the transfer of data Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 D Device Command 1 1 1 1 0 0 1 1 Status see belo...

Page 156: ...sables the security mode feature device lock func tion After completing of this command all the user data will be initialized to zero with a write operation At this time the data write is not verified with a read operation to determine if the data sector is initialized correctly At this time the defective sector information and the reassigned sector information for the device are not updated The s...

Page 157: ...ter when a new user password is set If you execute this command on disabling the security mode feature device lock function the password sent by the host is NOT compared with the Master Password and the User Password The device only erases all user data The execution time of this command for each model is shown below IC25N080ATMR04 0 66 IC25N060ATMR04 0 50 IC25N040ATMR04 0 34 IC25N030ATMR04 0 26 I...

Page 158: ...e is in frozen mode Refer to Table 53 Command table for device lock operation on page 82 Security Set Password Security Unlock Security Disable Password Security Erase Unit Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device...

Page 159: ...nction of this command Table 101 Security Set Password information Identifier Zero indicates that the device should check the supplied password against the user password stored internally One indicates that the device should check the given password against the master password stored internally Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3...

Page 160: ...The setting of the Identifier and Security level bits interact as follows Identifier User Security level High The password supplied with the command will be saved as the new user password The security mode feature lock function will be enabled from the next power on The drive may then be unlocked by either the user password or the previously set master password Identifier Master Security level Hig...

Page 161: ... is decremented for each password mismatch When this counter reaches zero all password protected commands are rejected until there is a hard reset or a power off Identifier A zero indicates that the device regards Password as the User Password A one indicates that the device regards Password as the Master Password The user can detect if the attempt to unlock the device has failed due to a mismatch...

Page 162: ...r seek L 1 Input parameters from the device LBA Low In LBA mode this register contains the current LBA bits 0 7 L 1 LBA High Mid In LBA mode this register contains the current LBA bits 8 15 Mid and bits16 23 High L 1 H In LBA mode this register contains the current LBA bits 24 27 L 1 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data...

Page 163: ...put parameters from the device Sector Count The Sector Count register contains result value Value Description 00h Temperature is equal to or lower than 20 C 01h FEh Temperature is Value 2 20 C FFh Temperature is higher than 107 C N Not recommendable condition for start up If over stressed condition is detected this bit will be set to one Command Block Output Registers Command Block Input Registers...

Page 164: ...LBA Mid LBA Mid LBA High LBA High Device 1 1 D Device Command 1 1 1 0 1 1 1 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 V Write cache Enable ECC bytes 4 bytes Read look ahead Enable Reverting to power on defaults Disable Address Offset mode Disable 02H Enable write cache See not...

Page 165: ...the write cache function will remain disabled For the current write cache function status refer to the Identify Device Information 129 word by the Identify Device command Hard reset or power off must not be done during the first 5 seconds after write command completion when write cache is enabled Note 3 When the Feature register is 85h Disable Advanced Power Management the deepest Power Saving mod...

Page 166: ... and LBA Low are ignored The default value see default CHS in Identify device information is used for that In LBA mode the Head number of Device LBA High LBA Mid and LBA Low specify the max LBA This com mand sets this LBA as the max LBA of the device After a successful command completion Identify Device response words 61 60 shall reflect the maximum address set with this command If the 48 bit Addr...

Page 167: ... register is ignored L 0 LBA High Mid In LBA mode this register contains LBA bits 8 15 Mid 16 23 High which is to be set L 1 In CHS mode this register contains max cylinder number which is to be set L 0 H In LBA mode this register contains LBA bits 24 27 which are to be input L 1 In CHS mode this register is ignored L 0 L This indicates the LBA addressing mode L 0 specifies the CHS mode and L 1 sp...

Page 168: ...Address Ext command or the device is in the Set Max Locked or Set Max Frozen state the device shall return command aborted If the device in Address Offset mode receives this command with the nonvolatile option the device returns aborted error to the host The device returns the command aborted for a second non volatile Set Max Address Ext command until next power on or hardware reset Command Block ...

Page 169: ...mand will be lost by POR B 1 is not valid when the device is in Address Offset mode LBA Low Current Set Max LBA 7 0 LBA Low Previous Set Max LBA 31 24 LBA Mid Current Set Max LBA 15 8 LBA Mid Previous Set Max LBA 39 32 LBA High Current Set Max LBA 23 16 LBA High Previous Set Max LBA 47 40 Input parameters from the device LBA Low HOB 0 Set Max LBA 7 0 LBA Low HOB 1 Set Max LBA 31 24 LBA Mid HOB 0 S...

Page 170: ...iple commands will be disabled Output parameters to the device Sector Count This indicates the block size to be used for the Read Multiple and the Write Multiple com mands Valid block sizes can be selected from 0 2 4 8 or 16 If 0 is specified then the Read Multiple and the Write Multiple commands are disabled Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Reg...

Page 171: ...set The use of hardware reset to recover from Sleep Mode may be incompatible with continued operation of the host system If the device is already spun down the spin down sequence is not executed Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LB...

Page 172: ...e listed below Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature V V V V V V V V Error see below Sector Count V V V V V V V V Sector Count LBA Low LBA Low LBA Mid 0 1 0 0 1 1 1 1 LBA Mid LBA High 1 1 0 0 0 0 1 0 LBA High Device 1 1 D Device Command 1 0 1 1 0 0 0 0 Status see below Error Register Status Register 7 6 5 4 ...

Page 173: ...re to be disabled The state of the Attribute Autosave feature either enabled or disabled will be preserved by the device across the power cycle A value of 00h written by the host into the device s Sector Count Register before issuing the S M A R T Enable Disable Attribute Autosave subcommand will cause this feature to be disabled Disabling this feature does not preclude the device from saving Attr...

Page 174: ... sector contents to the host The 512 bytes of data are returned at a command and the Sector Count value shall be set to one The LBA Low shall be set to specify the log sector address 13 38 1 7 S M A R T Write Log Sector subcommand D6h This command writes 512 bytes of data to the specified log sector The 512 bytes of data are transferred at a com mand and the LBA Low value shall be set to one The L...

Page 175: ... in the device s Attribute Data Sectors If the device is re enabled these Attribute Values will be updated as needed upon receipt of a S M A R T Read Attribute Values or a S M A R T Save Attribute Values command 13 38 1 10 S M A R T Return Status subcommand DAh This subcommand is used to communicate the reliability status of the device to the host s request Upon receipt of the S M A R T Return Sta...

Page 176: ...cally if the off line read scanning feature is disabled A value of F8h written by the host into the device s Sector Count register before issuing this subcommand shall cause the automatic Off line data collection feature to be enabled A value of F9 written by the host into the device s Sector Count register before issuing this subcommand shall cause the off line read scanning feature to be enabled...

Page 177: ...ich version of this data structure is implemented by the device This revision number will be set to 0005h This revision number identifies both the Attribute Value and Attribute Threshold Data structures Description Byte Offset Format Value Data Structure Revision Number 2 00h binary 0010h 1st Device Attribute 12 02h 1 2 30th Device Attribute 12 15Eh 1 2 Off line data collection status 1 16Ah 1 2 S...

Page 178: ...alue valid values from 01h to FEh 1 03h binary 00h invalid for attribute value not to be used 01h minimum value 64h initial value for all attributes prior to any data collection FDh maximum value FEh value is not valid FFh invalid for attribute value not to be used Reserved may not be 0 1 04h binary Reserved may not be 0 6 05h binary Reserved 00h 1 0Bh binary Total Bytes 12 ID Attribute Name 0 Ind...

Page 179: ...c Off line Data Collection Status Bit 7 Automatic Off line Data Collection Status 0 Automatic Off line Data Collection is disabled 1 Automatic Off line Data Collection is enabled Bits 0 6 represent a hexadecimal status value reported by the device Value Definition 0 Off line data collection never started 2 All segments completed without errors In this case the current segment pointer is equal to t...

Page 180: ... implemented 2 Abort restart off line by host bit 0 The device will suspend off line data collection activity after an interrupting command and resume it after a vendor specific event 1 The device will abort off line data collection activity upon receipt of a new command Bit Definition 0 3 Percent Self test remaining An approximation of the percent of the self test routine remaining until completi...

Page 181: ...ower mode attribute saving capability If bit 1 the device will save its Attribute Values prior to going into a power saving mode Standby or Sleep mode 1 Attribute auto save capability If bit 1 the device supports the S M A R T ENABLE DISABLE ATTRIBUTE AUTOSAVE command 2 15 Reserved 0 13 38 2 9 Error logging capability Bit Definition 7 1 Reserved 0 0 The Error Logging support bit If bit 1 the devic...

Page 182: ...ructure 13 38 3 2 Individual Thresholds Data Structure The following defines the 12 bytes that make up the information for each Threshold entry in the Device Attribute Thresholds Data Structure Attribute entries in the Individual Threshold Data Structure are in the same order and correspond to the entries in the Individual Attribute Data Structure Description Byte Offset Format Value Data Structur...

Page 183: ... byte ordering 13 38 4 1 S M A R T error log version This value is set to 01h 13 38 4 2 Error log pointer This points to the most recent error log data structure Only values 1 through 5 are valid 13 38 4 3 Device error count This field contains the total number of errors The value will not roll over 13 38 4 4 Error log data structure The data format of each error log structure is shown below Table...

Page 184: ...h Sector count register 1 02h LBA Low register 1 03h LBA Mid register 1 04h LBA High register 1 05h Device register 1 06h Command register 1 07h Time stamp milliseconds from Power On 4 08h 12 Description Byte Offset Reserved 1 00h Error register 1 01h Sector count register 1 02h LBA Low register 1 03h LBA Mid register 1 04h LBA High register 1 05h Device register 1 06h Status register 1 07h Extend...

Page 185: ...ructure is capable to contain up to 21 descriptors After 21 descriptors has been recorded the oldest descriptor will be overwritten with the new descriptor The self test log pointer points to the most recent descriptor When there is no descriptor the value is 0 When there are descriptor s the value is 1 through 21 Description Byte Offset Data structure revision 2 00h Self test number 1 n 18h 02h S...

Page 186: ...loaded into the LBA High and LBA Mid registers 51h 04h A S M A R T FUNCTION SET command was received by the device with a subcommand value in the Features Regis ter that is either invalid or not supported by this device 51h 04h A S M A R T FUNCTION SET command subcommand other than S M A R T ENABLE OPERATIONS was received by the device while the device was in a S M A R T Disabled state 51h 04h The...

Page 187: ...ector Count The Time out Parameter If it is zero the time out interval Standby Timer is NOT disabled but is automatically set to 109 minutes If it is other than zero the time out interval is set for Time out Parameter 5 seconds When the automatic power down sequence is enabled the device will enter the Standby mode automatically if the time out interval expires with no device access from the host ...

Page 188: ...ecuted During the Standby mode the device will respond to commands however there will be a delay while waiting for the spindle to reach operating speed The Standby Immediate command will not affect the auto power down time out parameter Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Secto...

Page 189: ...ized such that sequential Write Buffer and Read Buffer commands access the same 512 byte within the buffer Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device 1 1 D Device Command 1 1 1 0 1 0 0 0 Status see below Error Regis...

Page 190: ... register contains the LBA bits 0 7 L 1 LBA High Mid This indicates number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 8 15 Mid and bits 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This indicates the retry bit but this bit is ignored Input paramete...

Page 191: ...gister contains the current LBA bits 0 7 L 1 LBA High Mid This indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Mid and bits 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 192: ... be transferred high order bits 15 8 If zero is speci fied in the Sector Count register then 65 536 sectors will be transferred LBA Low Current LBA 7 0 LBA Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Erro...

Page 193: ...irst unrecoverable error LBA Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 194: ...1 LBA High Mid This indicates the cylinder number of the sector to be transferred L 0 In LBA mode this register contains the LBA bits 8 15 Mid and bits 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R The retry bit but this bit is ignored Input parameters from the device Sector Count This indicates the n...

Page 195: ... sector to be transferred L 0 In LBA mode this register contains current the LBA bits 24 27 L 1 The drive internally uses 40 bytes of ECC on all data read or writes The 4 byte mode of operation is provided via an emulation technique As a consequence of this emulation it is recommended that 40 byte ECC mode is used for all tests to confirm the operation of the ECC hardware of the drive Unexpected r...

Page 196: ... LBA mode this register contains the LBA bits 24 27 L 1 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred The Sector Count will be zero unless an unrecoverable error occurs LBA Low This indicates the sector number of the last transferred sector L 0 In LBA mode this register contains current the LBA bits 0 7 L 1 LBA High Mid This indicates ...

Page 197: ... transferred LBA Low Current LBA 7 0 LBA Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 LBA High Current LBA 23 16 LBA High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Se...

Page 198: ... Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 199: ...15 Mid and bits 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This indicates the retry bit this bit is ignored Input parameters from the device Sector Count This indicates the number of requested sectors not transferred The Sector Count will be zero unless an unrecoverable error occurs LBA Low T...

Page 200: ... the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Mid and bits 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 201: ...Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 LBA High Current LBA 23 16 LBA High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V V...

Page 202: ...le error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error 13 49 Write Verify 3Ch vendor specific In the implementation of the drive the Write Verify command is exactly the same as the Write Sectors command 30h Read verification is ...

Page 203: ...r BSY 0 and RDY 1 31 sec Data In Com mand Device Busy After Com mand Code Out OUT To Command Register Status Register BSY 1 400 ns Interrupt DRQ For Data Transfer In Status Register BSY 1 Status Register BSY 0 and DRQ 1 Interrupt 30 sec Device Busy After Data Transfer In 256th Read From Data Register Status Register BSY 1 10 µs Data Out Com mand Device Busy After Com mand Code Out OUT to Command R...

Page 204: ...time is referred to 13 27 Security Erase Unit F4h on page 144 Note 2 For FORMAT UNIT command the execution time is referred to 13 7 Format Unit F7h vendor specific on page 109 Note 3 When the initial power mode at power on is Standby mode and when the following commands are issued by the host as First Command the command s time out value of the field is 10 seconds Security Disable Password Securit...

Page 205: ...bsoleted 30h WRITE SECTOR S Yes Mandatory 31h WRITE SECTOR S Yes Obsoleted 32h WRITE LONG Yes Obsoleted 33h WRITE LONG Yes Obsoleted 38h CFA TRANSLATE SECTORS W O ERASE No Optional Note 7 3Ch WRITE VERIFY 2 Vendor specific Obsoleted 40h READ VERIFY SECTOR S Yes Mandatory 41h READ VERIFY SECTOR S Yes Obsoleted 50h FORMAT TRACK Yes Obsoleted 7xh SEEK Yes Mandatory 87h CFA TRANSLATE SECTORS No Option...

Page 206: ... STANDBY IMMEDIATE Yes Mandatory E1h IDLE IMMEDIATE Yes Mandatory E2h STANDBY Yes Mandatory E3h IDLE Yes Mandatory E4h READ BUFFER Yes Optional E5h CHECK POWER MODE Yes Mandatory E6h SLEEP Yes Mandatory E7h FLUSH CACHE Yes Mandatory E8h WRITE BUFFER Yes Optional ECh IDENTIFY DEVICE Yes Mandatory EDh MEDIA EJECT No Optional Note 7 EEh IDENTIFY DEVICE DMA No Obsoleted EFh SET FEATURES Yes Mandatory ...

Page 207: ...2 SET FEATURES command coverage Features Register Features Name Implementation for Travelstar 5K80 02h Enable write cache Yes 03h Set transfer mode Yes 05h Enable Advanced Power Management Yes 09h Enable Address Offset mode Yes 44h Set vendor specific bytes ECC Yes 55h Disable read look ahead feature Yes 5Dh Enable release interrupt No 5Eh Enable SERVICE interrupt No 66h Disable reverting to power...

Page 208: ...Travelstar 5K80 Hard Disk Drive Specification 192 15 3 Changes from the Travelstar 80GN The changes between the Travelstar 5K80 and the Travelstar 80GN are listed below Identify device information data ...

Page 209: ...Travelstar 5K80 Hard Disk Drive Specification 193 ...

Page 210: ...Travelstar 5K80 Hard Disk Drive Specification 194 ...

Page 211: ...7 Device Configuration Overlay 98 Device Control Register 61 Discrete tone penalty 32 Drive Address Register 61 Drive address setting 51 Drive characteristics 11 Drive handling precautions 4 Drive ready time 15 E Electrical interface specification 35 Electromagnetic compatibility 33 Emergency unload 26 Environment 21 Execute Device Diagnostic 101 F Failure prediction S M A R T 25 Features Register...

Page 212: ...6 Register set 59 Reset response 65 Reset timings 40 S S 156 S M A R T Function 73 Safety 33 Secondary circuit protection 34 Sector Addressing Mode 69 Sector Count Register 63 Sectors Track 12 Security Disable Password 138 Security Erase Unit 140 Security Set Password 143 Security Unlock 145 Seek 146 Seek Overlap 83 Seek time average 13 full stroke 14 single track 14 Sense Condition 147 Service li...

Page 213: ...stered trade marks of their respective companies References in this publication to Hitachi Global Storage Technologies products programs or services do not imply that Hitachi Global Storage Technologies intends to make these available in all countries in which Hitachi Global Storage Technologies operates Product information is provided for information pur poses only and does not constitute a warra...

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