Hitachi HTS421210H9AT00 Specifications Download Page 78 | Manualshive

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Travelstar 4K120 Hard Disk Drive Specification

64

10.1 Alternate Status Register

Table 41: Alternate Status Register

This register contains the same information as the Status Register. The only difference between this register and the
Status Register is that reading the Alternate Status Register does not imply an interrupt acknowledge or a clear of a
pending interrupt. See Section 10.13 "Status Register," on page 67 for the definition of the bits in this register.

10.2 Command Register

This register contains the command code being sent to the device. Command execution begins immediately after
this register is written. The command set is shown in Table 60: "Command Set (1 of 2)," on page 97 and Table
61: "Command Set (2 of 2)," on page 99. All other registers required for the command must be set up before writ-
ing to the Command Register.

10.3 Data Register

This register is used to transfer data blocks between the device data buffer and the host. It is also the register
through which sector information is transferred on a Format Track command and the configuration information is
transferred on an Identify Device command.

All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide. Data transfers are PIO
only.

The register contains valid data only when DRQ = 1 is in the Status Register.

7

6

5

4

3

2

1

0

BSY

RDY

DF

DSC

DRQ

COR

IDX

ERR

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Summary of Contents for HTS421210H9AT00

Page 1: ...orage Technologies Hard Disk Drive Specification Hitachi Travelstar 4K120 2 5 inch ATA IDE hard disk drive Models HTS421212H9AT00 HTS421210H9AT00 HTS421280H9AT00 HTS421260H9AT00 HTS421240H9AT00 Revision 1 2 12 July 2006 ...

Page 2: ......

Page 3: ...orage Technologies Hard Disk Drive Specification Hitachi Travelstar 4K120 2 5 inch ATA IDE hard disk drive Models HTS421212H9AT00 HTS421210H9AT00 HTS421280H9AT00 HTS421260H9AT00 HTS421240H9AT00 Revision 1 2 12 July 2006 ...

Page 4: ... incorporated in new editions of the publication Hitachi may make improvements or changes in any products or programs described in this publication at any time It is possible that this publication may contain reference to or information about Hitachi products machines and programs programming or services that are not announced in your country Such references or information must not be construed to...

Page 5: ...ning 17 4 4 3 Operating modes 19 5 0 Data integrity 21 5 1 Data loss at power off 21 5 2 Write Cache 21 5 3 Equipment status 21 5 4 WRITE safety 22 5 5 Data buffer test 22 5 6 Error recovery 22 5 7 Automatic reallocation 22 5 7 1 Nonrecovered write errors 22 5 7 2 Nonrecoverable read error 22 5 7 3 Recovered read errors 22 5 8 ECC 23 6 0 Specification 25 6 1 Environment 25 6 1 1 Temperature and hu...

Page 6: ... 6 8 Electromagnetic compatibility 37 6 8 1 CE mark 37 6 8 2 C TICK mark 37 6 8 3 BSMI mark 38 6 8 4 MIC mark 38 6 9 Safety 38 6 9 1 UL and CSA approval 38 6 9 2 IEC compliance 38 6 9 3 German safety mark 38 6 9 4 Flammability 38 6 9 5 Secondary circuit protection 38 6 10 Packaging 38 7 0 Electrical interface specification 39 7 1 Cabling 39 7 2 Interface connector 39 7 3 Signal definitions 40 7 4 ...

Page 7: ...us Register 67 11 0 General 69 11 1 Reset response 69 11 2 Register initialization 70 11 3 Diagnostic and Reset considerations 71 11 4 Power off considerations 72 11 4 1 Load Unload 72 11 4 2 Emergency unload 72 11 4 3 Required power off sequence 72 11 5 Sector Addressing Mode 73 11 5 1 Logical CHS addressing mode 73 11 5 2 LBA addressing mode 73 11 6 Power management features 74 11 6 1 Power mode...

Page 8: ...k Overlap 87 11 13 Write Cache function 87 11 14 Reassign Function 88 11 14 1 Auto Reassign Function 88 11 15 48 bit Address Feature Set 89 12 0 Command protocol 91 12 1 Data In commands 91 12 2 Data Out Commands 92 12 3 Non data commands 93 12 4 DMA Data Transfer commands 95 13 0 Command descriptions 97 13 1 Check Power Mode E5h 98h 103 13 2 Device Configuration Overlay B1h 104 13 2 1 DEVICE CONF...

Page 9: ...28 Security Erase Unit F4h 155 13 29 Security Freeze Lock F5h 157 13 30 Security Set Password F1h 158 13 31 Security Unlock F2h 160 13 32 Seek 7xh 161 13 33 Sense Condition F0h vendor specific 162 13 34 Set Features EFh 163 13 35 Set Max ADDRESS F9h 165 13 36 Set Max ADDRESS EXT 37h 167 13 37 Set Multiple C6h 169 13 38 Sleep E6h 99h 170 13 39 S M A R T Function Set B0h 171 13 39 1 S M A R T Functi...

Page 10: ...9h 202 13 50 Write Multiple FUA Ext CEh 204 13 51 Write Sectors 30h 31h 206 13 52 Write Sectors s EXT 34h 208 13 53 Write Verify 3Ch vendor specific 209 14 0 Timings 211 15 0 Appendix 213 15 1 Commands Support Coverage 213 15 2 SET FEATURES Commands Support Coverage 215 15 3 Changes from the Travelstar 5K100 217 ...

Page 11: ...le 21 Physical dimensions and weight 31 Table 22 Random vibration PSD profile breakpoints operating 34 Table 23 Swept sine vibration 34 Table 24 Random Vibration PSD Profile Breakpoints nonoperating 35 Table 25 Operating shock 35 Table 26 Nonoperating shock 35 Table 27 Weighted sound power 36 Table 28 Signal definitions 40 Table 29 SpecMial signal definitions for Ultra DMA 41 Table 30 PIO cycle ti...

Page 12: ...register values 104 Table 66 Device Configuration Overlay Data structure 106 Table 67 DCO error information definition 106 Table 68 Execute Device Diagnostic command 90h 107 Table 69 Flush Cache command E7h 108 Table 70 Flush Cache command E7h 109 Table 71 Format Track command 50h 110 Table 72 Format Unit command F7h 111 Table 73 Identify Device command ECh 112 Table 74 Identify device information...

Page 13: ...ity Erase Unit F4h 155 Table 109 Erase Unit information 155 Table 110 Security Freeze Lock F5h 157 Table 111 Security Set Password F1h 158 Table 112 Security Set Password information 158 Table 113 Security Unlock F2h 160 Table 114 Seek 7xh 161 Table 115 Sense Condition F0h vendor specific 162 Table 116 Set Features EFh 163 Table 117 Set Max ADDRESS F9h 165 Table 118 Set Max ADDRESS EXT Command 37h...

Page 14: ...h 199 Table 140 Write Multiple C5h 201 Table 141 Write Multiple EXT 39h 202 Table 142 Write Multiple FUA Ext CEh 204 Table 143 Write Sectors Command 30h 31h 206 Table 144 Write Sector s EXT Command 34h 208 Table 145 Time out values 211 Table 146 Command coverage 1 of 2 213 Table 147 Command coverage 2 of 2 214 Table 148 SET FEATURES command coverage 215 ...

Page 15: ...3 Abbreviations Abbreviation Meaning 32 KB 32 x 1024 bytes 64 KB 64 x 1024 bytes A Ampere AC alternating current AT Advanced Technology ATA Advanced Technology Attachment BIOS Basic Input Output System C Celsius CSA Canadian Standards Association C UL Canadian Underwriters Laboratory Cyl cylinder DC Direct Current DFT Drive Fitness Test DMA Direct Memory Access ECC error correction code EEC Europe...

Page 16: ...Output ISO International Standards Organization KB 1 000 bytes Kbpi 1000 bits per inch kgf cm kilogram force centimeter KHz kilohertz LBA logical block addressing Lw unit of A weighted sound power m meter max maximum MB 1 000 000 bytes Mbps 1 000 000 bits per second MHz megahertz MLC Machine Level Control mm millimeter ms millisecond us ms microsecond No number O Output OD Open Drain Programmed In...

Page 17: ... Underwriters Laboratory V volt VDE Verband Deutscher Electrotechniker W watt 3 state transistor transistor tristate logic 1 4 Caution Do not apply force to the top cover See figure below Do not cover the breathing hole on the top cover See figure below Do not touch the interface connector pins or the surface of the printed circuit board This drive can be damaged by electrostatic discharge ESD Any...

Page 18: ...Travelstar 4K120 Hard Disk Drive Specification 4 1 5 Drive handling precautions Do not press on the drive cover during handling ...

Page 19: ...ction Included 2 symbol system ECC Segmented Buffer with write cache 8192 KB Upper 428 KB is used for firmware 2048 KB Upper 428 KB is used for firmware HTS421240H9AT00 Fast data transfer rate up to 100 MB s Media data transfer rate max 376 Mb s Average seek time 11 ms for read Closed loop actuator servo Embedded Sector Servo Rotary voice coil motor actuator Load Unload mechanism Mechanical latch ...

Page 20: ...Travelstar 4K120 Hard Disk Drive Specification 6 ...

Page 21: ...Travelstar 4K120 Hard Disk Drive Specification 7 Part 1 Functional specification ...

Page 22: ...Travelstar 4K120 Hard Disk Drive Specification 8 ...

Page 23: ... functions AT Interface Protocol Embedded Sector Servo No ID TM formatting Multizone recording Code 100 106 System ECC Enhanced Adaptive Battery Life Extender 3 2 Head disk assembly data The following technologies are used in the drive Pico Slider Textured laminated AFC glass disk GMR head Integrated lead suspension ILS Load unload mechanism Mechanical latch ...

Page 24: ...Travelstar 4K120 Hard Disk Drive Specification 10 ...

Page 25: ...3 Number of sec tors 234 441 648 195 371 568 156 301 488 117 210 240 78 140 160 Total logical data bytes 120 034 123 776 100 030 242 816 80 026 361 856 60 011 642 880 40 007 761 920 Table 2 Data sheet Rotational Speed RPM 120GB 100GB 80GB 60GB 40GB Data transfer rates buffer to from media Mbps 4200 4200 4200 4200 4200 Data transfer rates ULTRA DMA 100 Mbyte sec 376 354 366 373 344 Recording densit...

Page 26: ...r Sec Track 0 0 7423 1008 1 7424 11519 966 2 11520 16127 936 3 16128 18431 924 4 18432 22655 896 5 22656 26111 868 6 26112 26879 861 7 26880 32127 840 8 32128 33023 819 9 33024 35839 798 10 35840 40319 768 11 40320 43519 744 12 43520 46591 728 13 46592 49919 700 14 49920 50815 693 15 50816 55551 672 16 55552 56703 651 17 56704 59391 630 18 59392 61823 616 19 61824 65919 588 20 65920 67711 567 21 6...

Page 27: ...76 16007 861 4 16008 21111 840 5 21112 22039 819 6 22040 24939 798 7 24940 29463 768 8 229464 31667 756 9 31668 35495 728 10 35496 36887 714 11 36888 39439 696 12 39440 44311 672 13 44312 45355 651 14 45356 48023 630 15 48024 50459 616 16 50460 52315 600 17 52316 56259 567 18 56260 58579 552 19 58580 61827 525 20 61828 66119 504 21 66120 66815 483 22 66816 67627 476 23 67628 69599 456 ...

Page 28: ...3 13920 17879 896 4 17880 21239 868 5 21240 22079 861 6 22080 26999 840 7 27000 27839 819 8 27840 32999 784 9 33000 36959 756 10 36960 38759 735 11 38760 40799 720 12 40800 43799 700 13 43800 44639 693 14 44640 49319 672 15 49320 50399 651 16 50400 53039 630 17 53040 55439 616 18 55440 59279 588 19 59280 61079 567 20 61080 63359 552 21 63360 66479 525 22 66480 70559 504 23 70560 71999 476 ...

Page 29: ...3 18048 19967 918 4 19968 23167 900 5 23168 25727 882 6 25728 29951 864 7 29952 33663 828 8 33664 35711 816 9 35712 39423 792 10 39424 41343 774 11 41344 43519 756 12 43520 45951 738 13 45952 50431 720 14 50432 51839 696 15 51840 55423 672 16 55424 58879 648 17 58880 60671 630 18 60672 63231 612 19 63232 65151 594 20 65152 68735 576 21 68736 70015 552 22 70016 72575 528 23 72576 76799 486 ...

Page 30: ... 7252 12151 840 4 12152 15581 816 5 15582 18815 792 6 18816 21755 768 7 21756 22539 756 8 22540 24793 738 9 24794 28517 720 10 28518 30085 696 11 30086 33319 672 12 33320 36357 648 13 36358 38317 630 14 38318 40473 612 15 40474 42335 594 16 42336 45765 576 17 45766 47137 552 18 47138 48607 540 19 48608 49881 528 20 49882 52527 504 21 52528 54585 480 22 54586 55369 468 23 55370 58799 432 ...

Page 31: ... application The following table gives a typical value for each parameter The detailed descriptions are found in Section 5 0 Data integrity beginning on page 21 4 4 1 Command overhead Command overhead time is defined as the interval from the time that a drive receives a command to the time that the actuator starts its motion 4 4 2 Mechanical positioning 4 4 2 1 Average seek time including settling...

Page 32: ...sed to correct arrival problems The average seek time is measured as the weighted average of all possible seek combinations max Σ Max 1 n Tn in Tn out n 1 Weighted Average max 1 max where max maximum seek length n seek length 1 to max Tnin inward measured seek time for an n track seek Tnout outward measured seek time for an n track seek 4 4 2 2 Full stroke seek time Full stroke seek is measured as...

Page 33: ...al self diagnostics Table 14 Description of operating modes Operating mode Description Spin up Start up time period from spindle stop or power down Seek Seek operation mode Write Write operation mode Read Read operation mode Performance Idle The device is capable of responding immediately to idle media access requests All electronic components remain powered and the full frequency servo remains op...

Page 34: ...ng from Low Power Idle mode to Standby mode is also controlled adaptively if it is allowed by Set Features Enable Advanced Power Management subcommand Low power idle The head is unloaded onto the ramp position The spindle motor is rotating at full speed Standby The device interface is capable of accepting commands The spindle motor is stopped All circuitry except the host interface is in power sav...

Page 35: ...not yet written onto the disk In order to prevent this data loss confirm the completion of the actual write operation prior to the power off by issuing a Soft reset Hard reset Flush Cache command Standby command Standby Immediate command Sleep command Confirm the command s completion 5 3 Equipment status The equipment status is available to the host system whenever the drive is not ready to read w...

Page 36: ...hen specific conditions are met The drive does not report any auto reallocation to the host system The conditions for auto reallocation are described below 5 7 1 Nonrecovered write errors When a write operation cannot be completed after the Error Recovery Procedure ERP is fully carried out the sectors are reallocated to the spare location An error is reported to the host system only when the write...

Page 37: ...pa bility The first 6 symbol of ECC are 4 check symbols for user data and the 2 symbol system ECC The other 34 symbols are Read Solomon ECC Hardware logic corrects up to 16 symbols 20 bytes errors on the fly 2 symbol System ECC is generated when HDC receives user data from HOST and can correct up to 1 symbol 10 bit error on the fly when one transfers to HOST ...

Page 38: ...Travelstar 4K120 Hard Disk Drive Specification 24 ...

Page 39: ...mbly The maximum storage period in the shipping package is one year Table 16 Environmental condition Operating conditions Temperature 5 to 55ºC See note below Relative humidity 8 to 90 non condensing Maximum wet bulb temperature 29 4ºC non condensing Maximum temperature gradient 20ºC hour Altitude 300 to 3 048 m 10 000 ft Non operating conditions Temperature 40 to 65ºC Relative humidity 5 to 95 no...

Page 40: ...able 17 Limits of temperature and humidity Specification Environment 0 10 20 30 40 50 60 70 80 90 100 45 35 25 15 5 5 15 25 35 45 55 65 Temperature degC Relative Humidity Operating Non Operating WetBulb 40 C WetBulb29 4 C 41 C 95 31 C 90 65 C 23 55 C 15 ...

Page 41: ...y two of the mounting screw holes of the drive when an AC current of up to 45 mA p p is applied through a 50 ohm resistor connected to any two mounting screw holes 6 2 DC power requirements Connection to the product should be made in a safety extra low voltage SELV circuits The voltage specifications are applied at the power connector of the drive Table 18 Magnetic flux density limits Frequency KH...

Page 42: ...ower Consumption of Low Power Idle in Watts Capacity GB 6 3 Reliability 6 3 1 Data Reliability Probability of not recovering data is 1 in 1013 bits read ECC implementation On the fly correction performed as a part of read channel function recovers up to 16 symbols of error in one sector 1 symbol is 10 bits 6 3 2 Failure prediction S M A R T The drive supports the Self Monitoring Analysis and Repor...

Page 43: ...tem through four screws The drive should be mounted with the recommended screw depth and torque The interface physical and electrical requirements of the drive should satisfy ATA 7 The power off sequence of the drive should comply with the required power off sequence described in Sec tion 6 3 6 2 Required Power Off Sequence on page 30 Service life of the drive is approximately 5 years or 20 000 po...

Page 44: ...er to the drive This power down sequence should be followed for entry into any system power down state system suspend state or system hibernation state In a robustly designed system emergency unload is limited to rare scenarios such as battery removal during operation 6 3 6 3 Power Switch design considerations In systems that use this drive consideration should be given to the design of the system...

Page 45: ... 1 Physical dimensions and weight The following table lists the dimensions of the drive Table 21 Physical dimensions and weight 120GB 100GB 80GB models 60GB 40GB models Height mm 9 5 0 2 9 5 0 2 Width mm 69 85 0 25 69 85 0 25 Length mm 100 2 0 25 100 2 0 25 Weight grams maximum 99 95 ...

Page 46: ...tor specifications are included in Section 7 2 Interface connector on page 39 6 4 4 Mounting orientation The drive will operate in all axes six directions and will stay within the specified error rates when tilted 5degrees from these positions Performance and error rate will stay within specification limits if the drive is operated in the other permissible ori entations from which it was formatted...

Page 47: ...unting hardware to mount the drive securely enough to prevent excessive motion or vibration of the drive at seek operation or spindle rotation 6 4 5 Load unload mechanism The head load unload mechanism is provided to protect the disk data during shipping movement or storage Upon power down a head unload mechanism secures the heads at the unload position See Section 6 5 4 Nonoperating shock on page...

Page 48: ...ing subjected to the following vibration levels 6 5 1 1 Random vibration The test consists of 30 minutes of random vibration using the power spectral density PSD levels below The vibration test level is 6 57 m sec2 RMS Root Mean Square 0 67 G RMS 6 5 1 2 Swept sine vibration Table 22 Random vibration PSD profile breakpoints operating Random vibration PSD profile breakpoint Hz m x 10n m2 sec4 Hz 5 ...

Page 49: ... criteria in the table below while operating under these conditions The shock test consists of 10 shock inputs in each axis and direction for a total of 60 There must be a minimum delay of 3 seconds between shock pulses The disk drive will operate without a hard error while subjected to the following half sine shock pulse The input level shall be applied to the normal disk drive subsystem mounting...

Page 50: ...ported by spacers so that the lower surface of the drive be located 25 3 mm above from the chamber floor No sound absorbing material shall be used The acoustical characteristics of the disk drive are measured under the following conditions Mode definitions Idle mode Power on disks spinning track following unit ready to receive and respond to control line com mands Operating mode Continuous random ...

Page 51: ...ing provided by the user Labels containing the vendor s name disk drive model number serial number place of manufacture and UL CSA logos Labels containing jumper information if required by the customer 6 8 Electromagnetic compatibility When installed in a suitable enclosure and exercised with a random accessing routine at the maximum data rate the drive meets the worldwide EMC requirements listed ...

Page 52: ...on mark or the CSA monogram for CSA certification appears on the drive 6 9 2 IEC compliance All models of the Travelstar 4K120 comply with IEC 60950 1999 6 9 3 German safety mark All models of the Travelstar 4K120 are approved by TUV on Test Requirement EN60950 2000 but the GS mark has not been obtained 6 9 4 Flammability The printed circuit boards used in this drive are made of material with a UL...

Page 53: ...he signal connector for AT attachment is designed to mate with Dupont part number 69764 044 or equivalent The figure below and on page 32 show the connector and pin location Figure 1 Interface connector pin assignments Figure 1 Interface connector pin assignments Pin position 20 is left blank for correct connector insertion Pin positions A B C and D are used for the drive address setting Refer to ...

Page 54: ...TL 02 GND 03 DD07 I O 3 state 04 DD08 I O 3 state 05 DD06 I O 3 state 06 DD09 I O 3 state 07 DD05 I O 3 state 08 DD10 I O 3 state 09 DD04 I O 3 state 10 DD11 I O 3 state 11 DD03 I O 3 state 12 DD12 I O 3 state 13 DD02 I O 3 state 14 DD13 I O 3 state 15 DD01 I O 3 state 16 DD14 I O 3 state 17 DD00 I O 3 state 18 DD15 I O 3 state 19 GND 20 Key 21 DMARQ O 3 state 22 GND 23 DIOW I TTL 24 GND 25 DIOR I...

Page 55: ...ected RESET This line is used to reset the drive It shall be kept at a Low logic state during power up and kept High thereafter DIOW The rising edge of this signal holds data from the data bus to a register or data register of the drive DIOR When this signal is low it enables data from a register or data register of the drive onto the data bus The data on the bus shall be latched on the rising edg...

Page 56: ...IAG within 30 seconds to indicate that it is no longer busy and is able to provide status Following the receipt of a valid Execute Drive Diagnostics command device 1 shall negate PDIAG within 1 ms to indicate to device 0 that it is busy and has not yet passed its drive diagnostics If device 1 is present then device 0 shall wait up to 6 seconds from the receipt of a valid Execute Drive Diagnostics ...

Page 57: ...ra DMA data in transfers The host may negate HDMARDY to pause an Ultra DMA data in transfer HSTROBE Ultra DMA This signal is used only for Ultra DMA data transfers between host and drive The signal HSTROBE is the data out strobe signal from the host for an Ultra DMA data out transfer Both the rising and falling edge of HSTROBE latch the data from DD 15 0 into the device The host may stop toggling ...

Page 58: ...s Inputs Voltage Input high ViH Voltage input low ViL 2 0 V min 5 5 V max 0 5 V min 0 8 V max Outputs Voltage output high at IoH min VoH Voltage output low at IoL min VoL 2 4 V min 0 5 V max Current Driver Sink Current IoL Driver Source Current IoH 16mA min 400 µA min PARAMETER DESCRIPTION Min µs Max µs t1 RESET high to Not BUSY 9 5 t10 RESET low width 25 t10 t1 RESET BUSY ...

Page 59: ...p 25 t2 DIOR DIOW pulse width 70 t2i DIOR DIOW recovery time 25 t3 DIOW data setup 20 t4 DIOW data hold 10 t5 DIOR data setup 20 t6 DIOR data hold 5 t6z DIOR data tristate 30 t9 DIOR DIOW to address valid hold 10 tRD Read data valid to IORDY active 0 tA IORDY setup width 35 tB IORDY pulse width 1 250 IOCS16 t9 t0 t2 t2i t3 t4 t5 t8 t7 t1 tB Read data DD 15 0 DIOR DIOW CS 1 0 DA 2 0 W rite data DD ...

Page 60: ...time 120 tD DIOR DIOW asserted pulse width 70 tE DIOR data access 50 tF DIOR data hold 5 tG DIOR DIOW data setup 20 tH DIOW data hold 10 tI DMACK to DIOR DIOW setup 0 tJ DIOR DIOW to DMACK hold 5 tKR tKW DIOR negated pulse width DIOW negated pulse width 25 tLR tLW DIOR to DMARQ delay DIOW to DMARQ delay 35 tZ DMACK to read data released 25 WRITEDD 15 0 READDD 15 0 DMACK DMARQ DIOR DIOW t0 tLR tLW ...

Page 61: ...20 20 tENV Envelope time 20 70 20 70 20 70 20 55 20 55 20 50 tZIORDY Minimum time before driv ing IORDY 0 0 0 0 0 0 tFS First DSTROBE time 0 230 0 200 0 170 0 130 0 120 0 90 tCYC Cycle time 112 73 54 39 25 16 8 t2CYC Two cycle time 230 154 115 86 57 38 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 tZAD Drivers to assert 0 0 0 0 0 0 tDS Data setup time at host 15 10 7 7 5...

Page 62: ...ore data words after HDMARDY is negated Table 33 Ultra DMA cycle timings Host Pausing Read PARAMETER DESCRIPTION MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns tSR DSTROBE to HDMARDY time 50 30 20 tRFS HDMARDY to final DSTROBE time 75 70 60 60 60 50 DSTROBE HDMARDY DMACK DMARQ tSR STOP tRFS ...

Page 63: ...e 0 150 0 150 0 150 0 100 0 100 0 75 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 tZAH Minimum delay time required for output 20 20 20 20 20 20 tMLI Interlock time with mini mum 20 20 20 20 20 20 tDS CRC word setup time at device 15 10 7 7 5 4 tDH CRC word hold time at device 5 5 5 5 5 4 6 tACK Hold time for DMACK negation 20 20 20 20 20 20 tIORDYZ Maximum time before r...

Page 64: ...0 150 0 150 0 100 0 100 0 75 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 tZAH Maximum delay time required for output 20 20 20 20 20 20 tMLI Interlock time with mini mum 20 20 20 20 20 20 tDS CRC word setup time at device 15 10 7 7 5 4 tDH CRC word hold time at device 5 5 5 5 5 4 6 tACK Hold time for DMACK negation 20 20 20 20 20 tIORDYZ Maximum time before releasing IO...

Page 65: ...ACK 20 20 20 20 20 20 tENV Envelope time 20 70 20 70 20 70 20 55 20 55 20 55 tZIORDY Minimum time before driv ing IORDY 0 0 0 0 0 0 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tCYC Cycle time 112 73 54 39 25 16 8 t2CYC Two cycle time 230 154 115 86 57 38 tDS Data setup time at device 15 10 7 7 5 4 tDH Data Hold time at device 5 5 5 5 5 4 6 HSTROBE DDMARDY DMACK DMARQ STOP tUI tAC...

Page 66: ...re data words after DDMARDY is negated Table 37 Ultra DMA cycle timing Device Pausing Write PARAMETER DESCRIPTION MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns MIN ns MAX ns tSR HSTROBE to DDMARDY time 50 30 20 tRFS DDMARDY to final HSTROBE time 75 70 60 60 60 50 HSTROBE DDMARDY DMACK DMARQ tSR STOP tRFS ...

Page 67: ...0 60 50 tRP Ready to pause time 160 125 100 100 100 85 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tMLI Interlocking time with mini mum 20 20 20 20 20 20 tDS CRC word setup time at device 15 10 7 7 5 4 tDH CRC word hold time at device 5 5 5 5 5 4 6 tACK Hold time for DMACK negation 20 20 20 20 20 20 tIORDYZ Maximum time before releasing IORDY 20 20 20 20 20 20 HSTROBE DDMARDY DMA...

Page 68: ...dge to assertion of STOP 50 50 50 50 50 50 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tMLI Interlock time with mini mum 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 4 tCH CRC word hold time at device 5 5 5 5 5 4 6 tACK Hold time for DMACK 20 20 20 20 20 20 tIORDYZ Maximum time before releasing IORDY 20 20 20 20 20 20 HSTROBE DDMARDY DMACK DMARQ STOP tMLI DD 15...

Page 69: ... used Setting 2 Device 1 Slave Setting 3 Cable Select Setting 4 Do not attach a jumper here Setting 5 Do not attach a jumper here The default setting at shipment is Setting 1 no jumper When pin C is grounded the drive does not spin up at POR When the drive address is Cable Select the address depends on the condition of pin 28 of the AT interface cable If pin 28 is ground or low the drive is a Mast...

Page 70: ... CS0 is used to address the Command Block registers while the CS1 is used to address Con trol Block registers The following table shows the I O address map CS0 CS1 DA02 DA01 DA00 DIOR 0 Read DIOW 0 Write Command Block Registers 0 1 0 0 0 Data Reg Data Reg 0 1 0 0 1 Error Reg Features Reg 0 1 0 1 0 Sector count Reg Sector count Reg 0 1 0 1 1 LBA low Reg LBA low Reg 0 1 1 0 0 LBA mid Reg LBA mid Reg...

Page 71: ...Travelstar 4K120 Hard Disk Drive Specification 57 Part 2 Interface specification ...

Page 72: ...Travelstar 4K120 Hard Disk Drive Specification 58 ...

Page 73: ...2004 with certain limitations described in Section 9 0 Deviations from standard on page 61 The drive supports the following functions as Vendor Specific Functions Address Offset Feature Format Unit Function SENSE CONDITION command 8 2 Terminology Device The Travelstar 4K120 drive Host Host indicates the system that the device is attached to First Command The first command which is executed after t...

Page 74: ...Travelstar 4K120 Hard Disk Drive Specification 60 ...

Page 75: ... Attachment with Packet Interface Extension ATA ATAPI 7 Revision 4b dated 21 April 2004 with the following deviation S M A R T Return Status S M A R T RETURN STATUS subcommand does not check advisory attributes This means that the device will not report a threshold exceeded condition unless the prefailure attributes exceed their corresponding thresholds For example a Power On Hours Attribute never...

Page 76: ...Travelstar 4K120 Hard Disk Drive Specification 62 ...

Page 77: ...lternate status Addresses Functions CS0 CS1 DA2 DA1 DA0 READ DIOR WRITE DIOW N N x x x Data bus high impedence Not used Control block registers N A 0 x x Data bus high impedance Not used N A 1 0 x Data bus high impedance Not used N A 1 1 0 Alternate Status Device Control N A 1 1 1 Device Address Not used Command block registers A N 0 0 0 Data Data A N 0 0 1 Error Features A N 0 1 0 Sector Count Se...

Page 78: ...immediately after this register is written The command set is shown in Table 60 Command Set 1 of 2 on page 97 and Table 61 Command Set 2 of 2 on page 99 All other registers required for the command must be set up before writ ing to the Command Register 10 3 Data Register This register is used to transfer data blocks between the device data buffer and the host It is also the register through which ...

Page 79: ...st 5 ms before setting RST 0 IEN Interrupt Enable When IEN 0 and the device is selected the device interrupts to the host will be enabled When IEN 1 or the device is not selected the device interrupts to the host will be disabled 7 6 5 4 3 2 1 0 HIZ WTG H3 H2 H1 H0 DS1 DS0 Bit Definitions HIZ High Impedance This bit is not a device and will always be in a high impedance state WTG Write Gate This b...

Page 80: ...nd 7 6 5 4 3 2 1 0 1 L 1 DRV HS3 HS2 HS1 HS0 L Binary encoded address mode select When L 0 addressing is by CHS mode When L 1 addressing is by LBA mode DRV Device When DRV 0 device 0 Master is selected When DRV 1 device 1 Slave is selected HS3 HS2 HS1 HS0 These contain bits 24 27 of the LBA At command completion these bits are updated to reflect the current LBA bits 24 27 7 6 5 4 3 2 1 0 CRC UNC 0...

Page 81: ...ts 8 15 and the previous content contains Bits 32 39 10 12 Sector Count Register This register contains the number of sectors of data requested to be transferred on a read or write operation between the host and the device If the value in the register is set to 0 a count of 256 sectors in 28 bit addressing or 65 536 sectors in 48 bit addressing is specified If the register is zero at command compl...

Page 82: ...When an error occurs this bit is not changed until the Status Register is read by the host and at that time the bit again indicates the current Seek complete status When the device enters into or is in Standby mode or Sleep mode this bit is set by device in spite of the drive not spinning up DRQ Data Request Bit DRQ 1 indicates that the device is ready to transfer a word or byte of data between th...

Page 83: ...ft reset Aborting Host interface o o Aborting Device operation 1 1 Initialization of hardware o x x Internal diagnostic o x x Starting spindle motor 5 x x Initialization of registers 2 o o o DASP handshake o o x PDIAG handshake o o o Reverting programmed parameters to default Number of CHS set by Initialize Device Parameters Multiple mode Write Cache Read look ahead ECC bytes Volatile max address ...

Page 84: ...power on hard reset or the Execute Device Diagnostic command are shown in the following table Table 48 Default Register Values Register Default Value Error Diagnostic Code Sector Count 01h LBA Low 01h LBA Mid 00h LBA High 00h Device A0h Status 50h Alternate Status 50h Table 49 Diagnostic codes Code Description 01h No error detected 02h Format device error 03h Sector buffer error 04h ECC circuitry ...

Page 85: ...bit whenever it is ready to accept commands Device 0 may assert DASP to indicate device activity If Device 1 is not present Device 0 does not Assert DASP at POR Soft Reset If Device 1 is present Device 0 shall read PDIAG to determine when it is valid to clear the BSY bit and whether Device 1 has reset without any errors otherwise Device 0 shall simply reset and clear the BSY bit DASP is asserted b...

Page 86: ...nload is intended to be invoked in rare situations Because this operation is inherently uncontrolled it is more mechanically stressful than a normal unload A single emergency unload operation is more stressful than 100 normal unloads Use of emergency unload reduces the start stop life of the drive at a rate at least 100 times faster than that of normal unload and may damage the drive 11 4 3 Requir...

Page 87: ...numbered from 1 to the maximum value allowed by the current CHS translation mode but cannot exceed 255 0FFh Heads are numbered from 0 to the maximum value allowed by the current CHS translation mode but cannot exceed 15 0Fh Cylinders are numbered from 0 to the maximum value allowed by the current CHS translation mode but cannot exceed 65535 0FFFFh When the host selects a CHS translation mode using...

Page 88: ...ed to move a device out of sleep mode When a device exits sleep mode it will enter standby mode The Standby and Standby Immediate commands move a device to standby mode immediately from the active or idle modes The standby command also sets the standby timer count 11 6 3 Standby Sleep command completion time 1 Confirm the completion of writing cached data in the buffer to media 2 Unload the heads ...

Page 89: ...ce registers may be invalid the host should NOT check the Status register nor the Alternate Status register prior to issuing a soft reset to wake up a device 11 6 7 Initial Power Mode at Power On After power on or hard reset the device goes to IDLE mode or STANDBY mode depending on the option Refer to section 4 4 3 Operating modes on page 19 for the initial power mode selection 11 7 Advanced Power...

Page 90: ...mp but the spindle is still rotated at the full speed Recovery time to Active mode is about 300 ms 11 7 4 Transition time The transition time is dynamically managed by the user s recent access pattern instead of fixed times The ABLE 3 algorithm monitors the interval between commands instead of the command frequency of ABLE 2 The algorithm supposes that the next command will come with the same comm...

Page 91: ...condition existing Accordingly lower attribute values indicate that the analysis algo rithms being used by the device are predicting a higher probability of a degrading or fault condition existing There is no implied linear reliability relationship corresponding to the numerical relationship between different attribute values for any particular attribute 11 8 3 Attribute thresholds Each attribute ...

Page 92: ...media access commands after power on Media access commands are enabled by either a Security Unlock command or a Security Erase Unit command Device Unlocked Mode The device enables all commands If a password is not set this mode is entered after power on otherwise it is entered by a Security Unlock or a Security Erase Unit command Device Frozen Mode The device enables all commands except those whic...

Page 93: ...default value of Master Password Revision Code is FFFEh Values 0000h and FFFFh are reserved 11 9 4 1 Master Password setting The system manufacturer or dealer can set an initial Master Password using the Security Set Password command without enabling the Device Lock Function 11 9 4 2 User Password setting When a User Password is set the device will automatically enter lock mode the next time the d...

Page 94: ...rs to the commands in Table 55 Command table for device lock operation on page 82 POR Device Locked mode Unlock CMD Command 1 Command 1 Password Erase Unit Password Match Reject Complete Complete Erase Unit Lock function Disable Normal operation All commands are available Freeze Lock command Enter Device Frozen mode Normal Operation expect Set Password Disable Password Erase Unit Unlock commands E...

Page 95: ...ITY UNLOCK command has an attempt limit the purpose of which is to prevent someone from attempting to unlock the drive with various passwords numerous times The device counts the password mismatch If the password does not match the device counts it without distinguishing the Master password and the User password If the count reaches 5 EXPIRE bit bit 4 of Word 128 in Identify Device information is ...

Page 96: ...able automatic off line o o o Initialize Device Parameters o o o S M A R T Enable Disable Attribute Autosave o o o Read Buffer o o o S M A R T Enable Operations o o o Read DMA x o o S M A R T Execute Off line Immediate o o o Read DMA EXT x o o S M A R T Read Attribute Values o o o Read Long x o o S M A R T Read Attribute Thresholds o o o Read Multiple x o o S M A R T Read log sector o o o Read Mul...

Page 97: ...the device has been tested to have a capacity of 536 MB flagging the media defects not visible by the system 2 Preparing drives at system manufacturer Special utility software is required to define the size of the protected area and to store the data in it The sequence is Issue Read Native Max ADDRESS command to get the real device max of LBA CYL Returned value shows that native device Max LBA is ...

Page 98: ...his command requests a transfer of a single sector of data from the host The following figure defines the content of this sector of information The password is retained by the device until the next power cycle When the device accepts this command the device is in Set Max Unlocked mode The Set Max LOCK command allows the host to disable the Set Max commands except Set Max UNLOCK and Set Max FREEZE ...

Page 99: ...an be removed by a Set Max Address command to move the Set Max pointer to the end of the drive But any commands which access sectors across the original native maximum LBA are rejected with error even if this protection is removed by a Set Max Address command 11 11 1 Enable Disable Address Offset Mode Subcommand code 09h Enable Address Offset Mode offsets address Cylinder 0 Head 0 Sector 1 LBA 0 t...

Page 100: ...e Data Identify Device data word 83 bit 7 indicates the device supports the Address Offset Feature Identify Device data word 86 bit 7 indicates the device is in Address Offset mode 11 11 3 Exceptions in Address Offset Mode Any commands which access sectors across the original native maximum LBA are rejected with error even if the access protection is removed by a Set Max Address command Read Look ...

Page 101: ...er of seeks is large this overhead can be ignored Table 59 Seek overlap 11 13 Write Cache function Write cache is a performance enhancement whereby the device reports completion of the write command Write Sector s and Write Multiple to the host as soon as the device has received all of the data in its buffer The device assumes responsibility to write the data subsequently onto the disk Writing dat...

Page 102: ...nder 0 The conditions for auto reallocation are described below Nonrecovered write errors When a write operation can not be completed after the Error Recovery Procedure ERP is fully carried out the sector s are reallocated to the spare location An error is reported to the host system only when the write cache is disabled and the auto reallocation fails If the number of available spare sectors reac...

Page 103: ...ved to previous content location The host may read the previous content of the Features the Sector Count the LBA Low Mid High registers by first setting the High Order Bit HOB bit 7 of the Device control register to one and then reading the desired register If HOB in the Device Control register is cleared to zero the host reads the most recently written content when the register is read A write to...

Page 104: ...Travelstar 4K120 Hard Disk Drive Specification 90 ...

Page 105: ...terrupts are cleared when the host reads the Status Register issues a reset or writes to the Command Register See Section 14 0 Timings on page 211 for the device time out values 12 1 Data In commands The following are Data In commands Device Configuration Identify Identify Device Read Buffer Read Long Read Multiple Read Multiple EXT Read Sector s Read Sector s EXT S M A R T Read Attribute Values S...

Page 106: ... BSY 0 ERR 1 ABT 1 and inter rupting the host If an error occurs the device sets BSY 0 ERR 1 and DRQ 1 The device then stores the error status in the Error Register and interrupt the host The registers will contain the location of the sector in error The error location will be reported using CHS mode or LBA mode The mode is decided by the mode select bit bit 6 of the Device Head register upon issu...

Page 107: ...ector of data including ECC bytes via the Data Register c The device sets BSY 1 after it has received the sector d After processing the sector of data the device sets BSY 0 and interrupts the host e In response to the interrupt the host reads the Status Register f The device clears the interrupt in response to the Status Register being read The Write Multiple command transfers one block of data fo...

Page 108: ...o save S M A R T Enable Disable Automatic Off line S M A R T Enable Operations S M A R T Execute Off line Immediate S M A R T Return Status S M A R T Save Attribute Values Standby Standby Immediate Execution of these commands involves no data transfer a The host writes any required parameters to the Features Sector Count LBA High LBA Mid LBA Low and Device Registers b The host writes the command c...

Page 109: ...ultisector commands The host resets the DMA channel prior to reading status from the device The DMA protocol allows high performance multitasking operating systems to eliminate processor overhead asso ciated with PIO transfers 1 The host initializes the Slave DMA channel 2 The host writes any required parameters to the Features Sector Count LBA High LBA Mid LBA Low and Device registers 3 The host ...

Page 110: ...Travelstar 4K120 Hard Disk Drive Specification 96 ...

Page 111: ...0 1 1 3 Idle 97 1 0 0 1 0 1 1 1 3 Idle Immediate E1 1 1 1 0 0 0 0 1 3 Idle Immediate 95 1 0 0 1 0 1 0 1 3 Initialize Device Parameters 91 1 0 0 1 0 0 0 1 1 Read Buffer E4 1 1 1 0 0 1 0 0 4 Read DMA C8 1 1 0 0 1 0 0 0 4 Read DMA C9 1 1 0 0 1 0 0 1 4 Read DMA EXT 25 0 0 1 0 0 1 0 1 1 Read Log EXT 2F 0 0 1 0 1 1 1 1 1 Read Long 22 0 0 1 0 0 0 1 0 1 Read Long 23 0 0 1 0 0 0 1 1 1 Read Multiple C4 1 1 ...

Page 112: ...Travelstar 4K120 Hard Disk Drive Specification 98 3 Seek 7x 0 1 1 1 3 Sense Condition F0 1 1 1 1 0 0 0 0 ...

Page 113: ... 0 3 S M A R T Execute Off line Immediate B0 1 0 1 1 0 0 0 0 1 S M A R T Read Attribute Values B0 1 0 1 1 0 0 0 0 1 S M A R T Read Attribute Thresholds B0 1 0 1 1 0 0 0 0 1 S M A R T Read Log Sector B0 1 0 1 1 0 0 0 0 3 S M A R T Return Status B0 1 0 1 1 0 0 0 0 3 S M A R T Save Attribute Values B0 1 0 1 1 0 0 0 0 2 S M A R T Write Log Sector B0 1 0 1 1 0 0 0 0 3 Standby E2 1 1 1 0 0 0 1 0 3 Stand...

Page 114: ...Travelstar 4K120 Hard Disk Drive Specification 100 Protocol 1 PIO data IN command 3 Non data command Vendor specific command 2 PIO data OUT command 4 DMA command ...

Page 115: ...F 05 Enable Power Up in Standby feature EF 06 Power Up in Standby feature device Spin Up EF 07 Enable Address Offset mode EF 09 Enable Automatic Acoustic management AAM EF 42 52 bytes of ECC apply on Read Write Long EF 44 Disable read look ahead feature EF 55 Disable reverting to power on defaults EF 66 Disable write cache EF 82 Disable Advanced Power Management feature EF 85 Disable Power Up in S...

Page 116: ...the condition of the device is not recommended for start up This indicates that the bit is not part of an input parameter Out put registers 0 This indicates that the bit must be set to 0 1 This indicates that the bit must be set to 1 D The device number bit This indicates that the device number bit of the Device Register should be specified Zero selects the master device and one selects the slave ...

Page 117: ...ster if the spindle motor is at speed and the device is not in Standby or Sleep mode Other wise the Sector Count Register is set to 0 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count V V V V V V V V LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device D Device Command 1 1 1...

Page 118: ...ice Con figuration Overlay settings After successful execution of a DEVICE CONFIGURATION FREEZE LOCK com mand all DEVICE CONFIGURATION SET DEVICE CONFIGURATION FREEZE LOCK DEVICE CONFIGURATION IDENTIFY and DEVICE CONFIGURATION RESTORE commands are aborted by the device The DEVICE CONFIGURATION FREEZE LOCK condition shall be cleared by a power down The DEVICE CONFIGURATION FREEZE LOCK condition sha...

Page 119: ...et If a bit is set in the overlay transmitted by the device that is not set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command no action is taken for that bit The format of the overlay transmitted by the device is described in the table in Table 66 Device Configuration Overlay Data structure on page 106 The restrictions on changing these bits is described in the text following th...

Page 120: ...e 3 and below are supported 2 1 Ultra DMA mode 2 and below are supported 1 1 Ultra DMA mode 1 and below are supported 0 1 Ultra DMA mode 0 is supported 3 6 Maximum LBA address 7 Command set feature set supported 15 9 Reserved 8 1 48 bit Addressing feature set supported 7 1 Host Protected Area feature set supported 6 1 Automatic acoustic management supported 5 Reserved 4 1 Power Up in Standby featu...

Page 121: ... to this command Instead the register contains a diagnostic code See Table 49 Diagnostic codes on page 70 for the definition Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device Device Command 1 0 0 1 0 0 0 0 Status see below...

Page 122: ... is written to the disk media Return a successful completion Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device D Device Command 1 1 1 0 0 1 1 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 ...

Page 123: ...ster 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current Sector Count HOB 0 Previous HOB 1 LBA Low Current LBA Low HOB 0 Previous HOB 1 LBA Mid Current LBA Mid HOB 0 Previous HOB 1 LBA High Current LBA High HOB 0 Previous HOB 1 Device Head D Device Head Command 1 1 1 0 1 0 1 0 Status See below Error Register S...

Page 124: ... LBA mode this reg ister specifies that LBA address bits 24 27 are to be formatted L 1 Input parameters from the device LBA Low In LBA mode this register specifies the current LBA address bits as 0 7 L 1 LBA High Mid In LBA mode this register specifies the current LBA address bits as 8 15 Mid and bits 16 23 High H In LBA mode this register specifies the current LBA address bits as 24 27 L 1 In LBA...

Page 125: ...t Unit command If the device receives a Format Unit command without a prior Security Erase Prepare command the device aborts the Format Unit command If the Feature register is NOT 11h the device returns an Abort error to the host This command does not request a data transfer Output parameters to the device Feature This indicates the Destination code for this command 11H The merge reassigned locati...

Page 126: ... information in Table 74 beginning on page 113 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device D Device Command 1 1 1 0 1 1 0 0 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 ID...

Page 127: ...omplete 1 1 1 hard sectored 0 0 Reserved 01 Note 1 Number of cylinders in default translate mode 02 xxxxH Specific configuration C837h SET FEATURES subcommand is not required to spin up and IDENTIFY DEVICE response is complete 37C8h SET FEATURES subcommand is required to spin up and IDENTIFY DEVICE response is complete 03 Note 1 Number of heads in default translate mode 04 05 0 Reserved 06 003FH N...

Page 128: ...ag of the word 15 3 0 Reserved 2 1 1 Word 88 is Valid 1 1 1 Word 64 70 are Valid 0 1 1 Word 54 58 are Valid 54 XXXXH Number of current cylinders 55 XXXXH Number of current heads 56 XXXXH Number of current sectors per track 57 58 XXXXH Current capacity in sectors Word 57 specifies the low word of the capacity 59 0XXXH Current Multiple setting Bit assignments 15 9 0 Reserved 8 1 Multiple Sector Sett...

Page 129: ...H Minimum PIO Transfer Cycle Time Without Flow Control 15 0 F0h Cycle time in nanoseconds 240 ns 8 3 MB s 68 0078H Minimum PIO Transfer Cycle Time With IORDY Flow Control 15 0 78h Cycle time in nanoseconds 120 ns 16 6 MB s 69 79 0000H Reserved 80 00FCH Major version number ATA 1 2 3 and ATA ATAPI 4 5 6 7 81 001AH Minor version number ATA ATAPI 7 T13 1532D Revision 1 82 746BH Command set supported ...

Page 130: ...e Media Status Notification Feature Set supported 3 1 1 Advanced Power Management Feature Set supported 2 0 1 CFA Feature Set supported 1 0 1 READ WRITE DMA QUEUED supported 0 1 1 DOWNLOAD MICROCODE command supported 84 4163H Command set feature supported extension 15 0 Always 14 1 Always 13 0 1 Idle Immediate with unload Feature supported 12 11 0 Reserved 10 0 1 URG bit supported for Write Stream...

Page 131: ... 13 1 1 READ BUFFER command supported 12 1 1 WRITE BUFFER command supported 11 0 Reserved 10 1 1 Host Protected Area Feature Set supported 9 0 1 DEVICE RESET command supported 8 0 1 SERVICE interrupt enabled 7 0 1 release interrupt enabled 6 X 1 look ahead enabled 5 X 1 write cache enabled 4 0 1 supports PACKET Command Feature Set 3 1 1 supports Power Management Feature Set 2 0 1 supports Removabl...

Page 132: ...command 4 0 1 Removable Media Status Notification Feature Set enabled 3 X 1 Advanced Power management Feature Set enabled 2 0 1 CFA Feature Set supported 1 0 1 READ WRITE DMA QUEUED command supported 0 1 1 DOWNLOAD MICROCODE command supported 87 4163H Command set feature enabled 15 0 Always 14 1 Always 13 0 1 Idle Immediate with unload feature supported 12 11 0 Reserved 10 0 1 URG bit supported fo...

Page 133: ...selected 11 X 1 UltraDMA mode 3 is selected 10 X 1 UltraDMA mode 2 is selected 9 X 1 UltraDMA mode 1 is selected 8 X 1 UltraDMA mode 0 is selected 7 0 Reserved 6 0 1 UltraDMA mode 6 is supported 5 1 1 UltraDMA mode 5 is supported 4 1 1 UltraDMA mode 4 is supported 3 1 1 UltraDMA mode 3 is supported 2 1 1 UltraDMA mode 2 is supported 1 1 1 UltraDMA mode 1 is supported 0 1 1 UltraDMA mode 0 is suppo...

Page 134: ...tic 10 9 X How Device 1 determined the device number 00 Reserved 01 a jumper was used 10 the CSEL signal was used 11 some other method used or method unknown 8 1 Always 7 0 Device 0 hardware reset result Device 1 clears these bits to 0 7 0 Reserved 6 X 1 Semi duplex mode is enabled 5 X 1 Device 0 detected Device 1 4 X 1 Device 1 passed diagnostic 3 X 1 Device 0 passed diagnostic 2 1 X how Device 0...

Page 135: ...us Bit assignments Ultra DMA Transfer mode mode 5 supported 15 9 0 Reserved 8 X Security Level 1 Maximum 0 High 7 6 0 Reserved 5 0 1 Enhanced secturity erase supported 4 X 1 Security count expried 3 X 1 Security Frozen 2 X 1 Security locked 1 X 1 Security enabled 0 1 1 Security supported 129 000xH Current Set Feature Option Bit assignments 15 4 0 Reserved 3 x 1 Auto reassign enabled 2 x 1 Revertin...

Page 136: ...er addressable sectors DF94BB0h HTS421210H9AT00 Number of cylinders 3FFFh Number of heads 10h Buffer size 3AD1h Total number of user addressable sectors BA52230h HTS421280H9AT00 Number of cylinders 3FFFh Number of heads 10h Buffer size 3AD1h Total number of user addressable sectors 950F8B0h HTS421260H9AT00 Number of cylinders 3FFFh Number of heads 10h Buffer size C45h Total number of user addressa...

Page 137: ... Input parameters to the device Sector Count This indicates the Time out Parameter If it is zero the time out interval Standby Timer is disabled If it is other than zero the time out interval is set for Time out Parameter 5 seconds The device will enter Standby mode automatically if the time out interval expires with no device access from the host The time out interval will be reinitialized if the...

Page 138: ...dy to respond to the host commands immediately The Idle Immediate command will not affect the auto power down time out parameter Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device D Device Command 1 1 1 0 0 0 0 1 Status see...

Page 139: ...tion of CCh is set Output parameters to the device Sector Count This indicates the number of sectors per track Zero 0 indicates 0 sectors per track instead of 256 sectors per track It means that there are no sectors per track H This indicates the number of heads minus 1 per cylinder The minimum is 0 and the maxi mum is 15 Command Block Output Registers Command Block Input Registers Register 7 6 5 ...

Page 140: ...Buffer command The contents of the sector may be different if any reads or writes have occurred since the Write Buffer command was issued Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device D Device Command 1 1 1 0 0 1 0 0 S...

Page 141: ...rst sector to be transferred L 0 In LBA mode this register specifies that LBA address bits 0 7 are to be transferred L 1 LBA High Mid This indicates the cylinder number of the first sector to be transferred L 0 In LBA mode this register specifies LBA address bits 8 15 Mid and 16 23 High to be transferred L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode thi...

Page 142: ...ndicates the sector number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 0 7 L 1 LBA High Mid This indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Mid and bits16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains...

Page 143: ...bits 15 8 If 0000h in the Sector Count register is specified 65 536 sectors will be transferred LBA Low Current LBA 7 0 LBA Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 LBA High Current LBA 23 16 LBA High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data Hi...

Page 144: ...A Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 145: ...the to be read low order bits 7 0 LBA Mid Previous The first sector of the log to be read high order bit 15 8 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V V HOB 1 LBA Low Curre...

Page 146: ...eneral purpose log Directory The value of the General Purpose Logging Version word shall be 0001h A value of 0000h indicates that there is no General Purpose Log Directory The Logs at log addresses 80h 9Fh are defined as 16 sectors long Description Bytes Offset General Purpose Logging Version 2 00h Number of sectors in the log at log address 01h 7 0 1 02h Number of sectors in the log at log addres...

Page 147: ...h of the last four errors reported by the device These error log data structure entries are viewed as a circular buffer The fifth error shall create an error log structure that replaces the first error log data structure The next error after that shall create an error log data structure that replaces the second error log structure etc Unused error log data structures shall be filled with zeros Dat...

Page 148: ...ite to the register Description Bytes Offset Device Control register 1 00h Features register 7 0 see Note 1 01h Features register 15 8 1 02h Sector count register 7 0 1 03h Sector count register 15 8 1 04h Sector number register 7 0 1 05h Sector number register 15 8 1 06h Cylinder Low register 7 0 1 07h Cylinder Low register 15 8 1 08h Cylinder High register 7 0 1 09h Cylinder High register 15 8 1...

Page 149: ...alue indicating the state of the device when the command was issued to the device or the reset occurred as described below Value State Note The value of x is vendor specific Value State x0h Unknown x1h Sleep x2h Standby x3h Active Idle x4h SMART Off line or Self test x5h xAh Reserved xBh xFh Vendor specific ...

Page 150: ...nded Self test log data structure These descriptor entries are viewed as a circular buffer The nineteenth self test shall create a descriptor entry that replaces descriptor entry 1 The next self test after that shall create a descriptor entry that replaces descriptor entry 2 etc All unused self test descriptors shall be filled with zeros 13 15 4 1 Self test log data structure revision number The v...

Page 151: ...n Bytes Offset Self test number 1 00h Self test execution status 1 01h Power on life timestamp in hours 2 02h Self test failure check point 1 04h Failing LBA 7 0 1 05h Failing LBA 15 8 1 06h Failing LBA 23 16 1 07h Failing LBA 31 24 1 08h Failing LBA 39 32 1 09h Failing LBA 47 40 1 0Ah Vendor specific 15 0Bh 26 ...

Page 152: ...e LBA Low This indicates the sector number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 0 7 L 1 LBA High Mid This indicates the cylinder number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 24 2...

Page 153: ...de this register contains current LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 The device internally uses 51 bytes of ECC data on all data written or read from the disk The 4 byte mode of oper ation is provided by means of an emulation Use of the 51 byte ECC mode is recommended for test...

Page 154: ...ed L 0 In LBA mode this register contains LBA bits 8 15 Mid 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains LBA bits 24 27 L 1 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred This number is zero unless an unrecoverable error occurs LBA Low This indicates the sec...

Page 155: ...indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Mid 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 ...

Page 156: ...ess of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error Table 97 Read Multiple EXT 29h Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previ...

Page 157: ...register contains the native max LBA bits 0 7 L 1 In CHS mode this register contains the native max LBA Low L 0 LBA High Mid In LBA mode this register contains the native max LBA bits 8 15 Mid and bits 16 23 High L 1 In CHS mode this register contains the native max cylinder number L 0 H In LBA mode this register contains the native max LBA bits 24 27 L 1 In CHS mode this register contains the nat...

Page 158: ...ive max areas LBA High HOB 1 LBA 47 40 of the address of the Native max areas Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current Sector Count HOB 0 Previous HOB 1 LBA Low Current LBA Low HOB 0 V V V V V V V V Previous HOB 1 V V V V V V V V ...

Page 159: ...is the retry bit this bit is ignored Input parameters from the device Sector Count This is the number of requested sectors not transferred This will be zero unless an unre coverable error occurs LBA Low This is the sector number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 0 7 L 1 LBA High Mid This is the cylinder number of the last transferred sector ...

Page 160: ...BA Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 LBA High Current LBA 23 16 LBA High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V ...

Page 161: ...A Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 162: ...In LBA mode this register contains the LBA bits 8 15 Mid and bits 16 23 High L 1 H This is the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This is the retry bit this bit is ignored Input parameters from the device Sector Count This is the number of requested sectors not transferred This number will be zero unless an unrecoverabl...

Page 163: ...s the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Mid and bits 16 23 High L 1 H This is the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 164: ...be transferred LBA Low Current LBA 7 0 LBA Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 LBA High Current LBA 23 16 LBA High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V ...

Page 165: ...A Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 166: ...ill be set in the Error Register Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device D Device Command 0 0 0 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RD...

Page 167: ...d Information for Security Disable Password command The device will compare the password sent from this host with that specified in the control word Identifier Zero indicates that the device should check the supplied password against the user pass word stored internally One indicates that the device should check the given password against the master password stored internally Command Block Output ...

Page 168: ... Unit Command This com mand is to prevent accidental erasure of the device This command does not request to transfer data Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device D Device Command 1 1 1 1 0 0 1 1 Status see below ...

Page 169: ...d disables the security mode feature device lock func tion After completing of this command all the user data will be initialized to zero with a write operation At this time the data write is not verified with a read operation to determine if the data sector is initialized correctly At this time the defective sector information and the reassigned sector information for the device are not updated T...

Page 170: ...n a new user password is set If you execute this command on disabling the security mode feature device lock function the password sent by the host is NOT compared with the Master Password and the User Password The device only erases all user data The execution time of this command for each model is shown below HTS421212H9AT00 88 min HTS421210H9AT00 76 min HTS421280H9AT00 62 min HTS421260H9AT00 46 ...

Page 171: ...evice is in frozen mode Refer to Table 55 Command table for device lock operation on page 82 Security Set Password Security Unlock Security Disable Password Security Erase Unit Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High De...

Page 172: ... function of this command Table 112 Security Set Password information Identifier Zero indicates that the device should check the supplied password against the user password stored internally One indicates that the device should check the given password against the master password stored internally Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 ...

Page 173: ...served The setting of the Identifier and Security level bits interact as follows Identifier User Security level High The password supplied with the command will be saved as the new user password The security mode feature lock function will be enabled from the next power on The drive may then be unlocked by either the user password or the previously set master password Identifier Master Security le...

Page 174: ...and is decremented for each password mismatch When this counter reaches zero all password protected commands are rejected until there is a hard reset or a power off Identifier A zero indicates that the device regards Password as the User Password A one indicates that the device regards Password as the Master Password The user can detect if the attempt to unlock the device has failed due to a misma...

Page 175: ... for seek L 1 Input parameters from the device LBA Low In LBA mode this register contains the current LBA bits 0 7 L 1 LBA High Mid In LBA mode this register contains the current LBA bits 8 15 Mid and bits16 23 High L 1 H In LBA mode this register contains the current LBA bits 24 27 L 1 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 D...

Page 176: ... Input parameters from the device Sector Count The Sector Count register contains result value Value Description 00h Temperature is equal to or lower than 20 C 01h FEh Temperature is Value 2 20 C FFh Temperature is higher than 107 C N Not recommendable condition for start up If over stressed condition is detected this bit will be set to one Command Block Output Registers Command Block Input Regist...

Page 177: ...A High Device D Device Command 1 1 1 0 1 1 1 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 V Write cache Enable ECC bytes 4 bytes Read look ahead Enable Reverting to power on defaults Disable Address Offset mode Disable Feature Destination code for this command 02H Enable write ca...

Page 178: ...Power Saving mode becomes Active Idle Note 4 When Feature register is 42h Enable Automatic Acoustic Management the Sector Count Register spec ifies the Automatic Acoustic Management level 80h BFh The seek mode is set to Quiet seek mode C0h FEh The seek mode is set to Normal seek mode 00h 7Fh FFh Invalid setting The command is aborted When Feature register is C2h Disable Automatic Acoustic Manage m...

Page 179: ...ICE and LBA Low are ignored The default value see default CHS in Identify device information is used for that In LBA mode the Head number of Device LBA High LBA Mid and LBA Low specify the max LBA This com mand sets this LBA as the max LBA of the device After a successful command completion Identify Device response words 61 60 shall reflect the maximum address set with this command If the 48 bit A...

Page 180: ... register is ignored L 0 LBA High Mid In LBA mode this register contains LBA bits 8 15 Mid 16 23 High which is to be set L 1 In CHS mode this register contains max cylinder number which is to be set L 0 H In LBA mode this register contains LBA bits 24 27 which are to be input L 1 In CHS mode this register is ignored L 0 L This indicates the LBA addressing mode L 0 specifies the CHS mode and L 1 sp...

Page 181: ... Address Ext command or the device is in the Set Max Locked or Set Max Frozen state the device shall return command aborted If the device in Address Offset mode receives this command with the nonvolatile option the device returns aborted error to the host The device returns the command aborted for a second non volatile Set Max Address Ext command until next power on or hardware reset Command Block...

Page 182: ...mmand will be lost by POR B 1 is not valid when the device is in Address Offset mode LBA Low Current Set Max LBA 7 0 LBA Low Previous Set Max LBA 31 24 LBA Mid Current Set Max LBA 15 8 LBA Mid Previous Set Max LBA 39 32 LBA High Current Set Max LBA 23 16 LBA High Previous Set Max LBA 47 40 Input parameters from the device LBA Low HOB 0 Set Max LBA 7 0 LBA Low HOB 1 Set Max LBA 31 24 LBA Mid HOB 0 ...

Page 183: ...l tiple commands will be disabled Output parameters to the device Sector Count This indicates the block size to be used for the Read Multiple and the Write Multiple com mands Valid block sizes can be selected from 0 2 4 8 or 16 If 0 is specified then the Read Multiple and the Write Multiple commands are disabled Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 ...

Page 184: ...reset The use of hardware reset to recover from Sleep Mode may be incompatible with continued operation of the host system If the device is already spun down the spin down sequence is not executed Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid ...

Page 185: ...mand returns the device s Attribute Thresholds to the host Upon receipt of the S M A R T Read Attribute Thresholds subcommand from the host the device asserts BSY reads the Attribute Thresholds from the Attribute Threshold sectors asserts DRQ clears BSY asserts INTRQ and then waits for the host to transfer the 512 bytes of Attribute Thresholds information from the device via the Data Register 13 3...

Page 186: ... clears BSY and asserts INTRQ 13 39 1 5 S M A R T Execute Off line Immediate subcommand D4h This subcommand causes the device to immediately initiate the set of activities that collect Attribute data in an off line mode off line routine or execute a self test routine in either captive or off line mode The LBA Low register shall be set to specify the operation to be executed Off line mode The devic...

Page 187: ...ors Table 118 shows an example of a Selective self test definition with three test spans defined In this example the test terminates when all three test spans have been scanned Table 122 Selective self test span example After the scan of the selected spans described above a user may wish to have the rest of media read scanned as an off line scan In this case the user shall set the flag to enable o...

Page 188: ...t is in progress the selective self test is aborted and the newly requested self test is executed 13 39 1 6 S M A R T Read Log Sector subcommand D5h This command returns the specified log sector contents to the host The 512 bytes of data are returned at a command and the Sector Count value shall be set to one The LBA Low shall be set to specify the log sector address 13 39 1 7 S M A R T Write Log ...

Page 189: ... High register clears BSY and asserts INTRQ If the device detects a Threshold Exceeded Condition for prefailure attributes the device loads F4h into the LBA Mid register 2Ch into the LBA High register clears BSY and asserts INTRQ Advisory attributes never result in a negative reliability condition 13 39 1 11 S M A R T Enable Disable Automatic Off line subcommand DBh This subcommand enables and dis...

Page 190: ...evice s Sector Count register before issuing this subcommand shall cause the off line read scanning feature to be enabled The Device perform the off line read scanning at the off line data collection activities which is initiated by the S M A R T Execute Off line Immediate Subcommand D4h even if the automatic off line feature is disabled Any other non zero value written by the host into this regis...

Page 191: ...ich version of this data structure is implemented by the device This revision number will be set to 0005h This revision number identifies both the Attribute Value and Attribute Threshold Data structures Description Byte Offset Format Value Data Structure Revision Number 2 00h binary 0010h 1st Device Attribute 12 02h 1 2 30th Device Attribute 12 15Eh 1 2 Off line data collection status 1 16Ah 1 2 S...

Page 192: ...alue valid values from 01h to FEh 1 03h binary 00h invalid for attribute value not to be used 01h minimum value 64h initial value for all attributes prior to any data collection FDh maximum value FEh value is not valid FFh invalid for attribute value not to be used Reserved may not be 0 1 04h binary Reserved may not be 0 6 05h binary Reserved 00h 1 0Bh binary Total Bytes 12 ID Attribute Name 0 Ind...

Page 193: ...c Off line Data Collection Status Bit 7 Automatic Off line Data Collection Status 0 Automatic Off line Data Collection is disabled 1 Automatic Off line Data Collection is enabled Bits 0 6 represent a hexadecimal status value reported by the device Value Definition 0 Off line data collection never started 2 All segments completed without errors In this case the current segment pointer is equal to t...

Page 194: ...s implemented 2 Abort restart off line by host bit 0 The device will suspend off line data collection activity after an interrupting command and resume it after a vendor specific event 1 The device will abort off line data collection activity upon receipt of a new command Bit Definition 0 3 Percent Self test remaining An approximation of the percent of the self test routine remaining until complet...

Page 195: ...power mode attribute saving capability If bit 1 the device will save its Attribute Values prior to going into a power saving mode Standby or Sleep mode 1 Attribute auto save capability If bit 1 the device supports the S M A R T ENABLE DISABLE ATTRIBUTE AUTOSAVE command 2 15 Reserved 0 13 39 2 9 Error logging capability Bit Definition 7 1 Reserved 0 0 The Error Logging support bit If bit 1 the devi...

Page 196: ...that is that the least significant byte occupies the lowest numbered byte address location in the field The sequence of active Attribute Thresholds will appear in the same order as their corresponding Attribute Values Table 125 Device Attribute Thresholds Data Structure 1 See the following definitions 2 Value varies by actual operating condition 3 Filled with 00h Description Byte Offset Format Val...

Page 197: ...shown in these data structures follow the ATA ATAPI 7 specifications for byte ordering 13 39 5 1 S M A R T error log version This value is set to 01h 13 39 5 2 Error log pointer This points to the most recent error log data structure Only values 1 through 5 are valid Description Bytes Offset S M A R T Logging Version 2 00h Number of sectors in the log at log address 1 1 02h Reserved 1 03H Number o...

Page 198: ...re 12 18h 4th command data structure 12 24h 5th command data structure 12 30h Error data structure 30 3Ch 90 Description Byte Offset Device Control register 1 00h Features register 1 01h Sector count register 1 02h LBA Low register 1 03h LBA Mid register 1 04h LBA High register 1 05h Device register 1 06h Command register 1 07h Time stamp milliseconds from Power On 4 08h 12 Description Byte Offset...

Page 199: ... 0 When there are descriptor s the value is 1 through 21 13 39 7 Selective self test log data structure The Selective self test log is a log that may be both written and read by the host This log allows the host to select the parameters for the self test and to monitor the progress of the self test The following table defines the contents of the Selective self test log which is 512 bytes long All ...

Page 200: ...Travelstar 4K120 Hard Disk Drive Specification 186 Table 131 Selective self test log ...

Page 201: ... loaded into the LBA High and LBA Mid registers 51h 04h A S M A R T FUNCTION SET command was received by the device with a subcommand value in the Features Regis ter that is either invalid or not supported by this device 51h 04h A S M A R T FUNCTION SET command subcommand other than S M A R T ENABLE OPERATIONS was received by the device while the device was in a S M A R T Disabled state 51h 04h Th...

Page 202: ...arameters to the device Sector Count The Time out Parameter If it is zero the time out interval Standby Timer is disabled If it is other than zero the time out interval is set for Time out Parameter 5 seconds When the automatic power down sequence is enabled the device will enter the Standby mode automatically if the time out interval expires with no device access from the host The time out interv...

Page 203: ... executed During the Standby mode the device will respond to commands however there will be a delay while waiting for the spindle to reach operating speed The Standby Immediate command will not affect the auto power down time out parameter Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Se...

Page 204: ...ronized such that sequential Write Buffer and Read Buffer commands access the same 512 byte within the buffer Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count LBA Low LBA Low LBA Mid LBA Mid LBA High LBA High Device D Device Command 1 1 1 0 1 0 0 0 Status see below Error Regist...

Page 205: ...his register contains the LBA bits 0 7 L 1 LBA High Mid This indicates number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 8 15 Mid and bits 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This indicates the retry bit but this bit is ignored Input param...

Page 206: ...gister contains the current LBA bits 0 7 L 1 LBA High Mid This indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Mid and bits 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 207: ...o be transferred high order bits 15 8 If zero is speci fied in the Sector Count register then 65 536 sectors will be transferred LBA Low Current LBA 7 0 LBA Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Err...

Page 208: ...irst unrecoverable error LBA Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 209: ...ous sectors to be transferred low order bits 7 0 Sector Count Previous The number of continuous sectors to be transferred high order bits 15 8 If zero is speci fied in the Sector Count register then 65 536 sectors will be transferred LBA Low Current LBA 7 0 LBA Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 Command Block Output Registers Command Block Input Registers Re...

Page 210: ...irst unrecoverable error LBA Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 211: ...st sector of the log to be written low order bits 7 0 Cylinder Low Previous The first sector of the log to be written high order bits 15 8 If the feature set associated with the log specified in the Sector Number register is not supported or enabled or if the values in the Sector Count Sector Number or Cylinder Low registers are invalid the device shall return com mand aborted If the host attempts...

Page 212: ...Travelstar 4K120 Hard Disk Drive Specification 198 ...

Page 213: ... L 1 LBA High Mid This indicates the cylinder number of the sector to be transferred L 0 In LBA mode this register contains the LBA bits 8 15 Mid and bits 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R The retry bit but this bit is ignored Input parameters from the device Sector Count This indicates th...

Page 214: ...e sector to be transferred L 0 In LBA mode this register contains current the LBA bits 24 27 L 1 The drive internally uses 51 bytes of ECC on all data read or writes The 4 byte mode of operation is provided via an emulation technique As a consequence of this emulation it is recommended that 51 byte ECC mode is used for all tests to confirm the operation of the ECC hardware of the drive Unexpected ...

Page 215: ... In LBA mode this register contains the LBA bits 24 27 L 1 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred The Sector Count will be zero unless an unrecoverable error occurs LBA Low This indicates the sector number of the last transferred sector L 0 In LBA mode this register contains current the LBA bits 0 7 L 1 LBA High Mid This indicat...

Page 216: ...ll be transferred LBA Low Current LBA 7 0 LBA Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 LBA High Current LBA 23 16 LBA High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V...

Page 217: ...A Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 218: ...ransferred LBA Low Current LBA 7 0 LBA Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 LBA High Current LBA 23 16 LBA High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sect...

Page 219: ...A Low HOB 1 LBA 31 24 of the address of the first unrecoverable error LBA Mid HOB 0 LBA 15 8 of the address of the first unrecoverable error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 220: ... 8 15 Mid and bits 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This indicates the retry bit this bit is ignored Input parameters from the device Sector Count This indicates the number of requested sectors not transferred The Sector Count will be zero unless an unrecoverable error occurs LBA Lo...

Page 221: ...s the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Mid and bits 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 222: ... Low Previous LBA 31 24 LBA Mid Current LBA 15 8 LBA Mid Previous LBA 39 32 LBA High Current LBA 23 16 LBA High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V ...

Page 223: ...ble error LBA Mid HOB 1 LBA 39 32 of the address of the first unrecoverable error LBA High HOB 0 LBA 23 16 of the address of the first unrecoverable error LBA High HOB 1 LBA 47 40 of the address of the first unrecoverable error 13 53 Write Verify 3Ch vendor specific In the implementation of the drive the Write Verify command is exactly the same as the Write Sectors command 30h Read verification is...

Page 224: ...Travelstar 4K120 Hard Disk Drive Specification 210 ...

Page 225: ...ESET Signal Asserted Status Register BSY 1 400 ns Device Ready After Hard Reset Bus RESET Signal Asserted Status Register BSY 0 and RDY 1 31 sec Data In Com mand Device Busy After Com mand Code Out OUT To Command Register Status Register BSY 1 400 ns Interrupt DRQ For Data Transfer In Status Register BSY 1 Status Register BSY 0 and DRQ 1 Interrupt 30 sec Device Busy After Data Transfer In 256th Re...

Page 226: ...ication 212 Note 1 For SECURITY ERASE UNIT command the execution time is referred to 13 28 Security Erase Unit F4h on page 155 Note 2 For FORMAT UNIT command the execution time is referred to 13 7 Format Unit F7h vendor specific on page 111 ...

Page 227: ...bsoleted 30h WRITE SECTOR S Yes Mandatory 31h WRITE SECTOR S Yes Obsoleted 32h WRITE LONG Yes Obsoleted 33h WRITE LONG Yes Obsoleted 38h CFA TRANSLATE SECTORS W O ERASE No Optional Note 7 3Ch WRITE VERIFY 2 Vendor specific Obsoleted 3Dh WRITE DMA FUA EXT Yes Optional 40h READ VERIFY SECTOR S Yes Mandatory 41h READ VERIFY SECTOR S Yes Obsoleted 50h FORMAT TRACK Yes Obsoleted 7xh SEEK Yes Mandatory ...

Page 228: ... Yes Optional E5h CHECK POWER MODE Yes Mandatory E6h SLEEP Yes Mandatory E7h FLUSH CACHE Yes Mandatory E8h WRITE BUFFER Yes Optional ECh IDENTIFY DEVICE Yes Mandatory EDh MEDIA EJECT No Optional Note 7 EEh IDENTIFY DEVICE DMA No Obsoleted EFh SET FEATURES Yes Mandatory F0h SENSE CONDITION Vendor specific Vendor specific F1h SECURITY SET PASSWORD Yes Optional Note 6 F2h SECURITY UNLOCK Yes Optional...

Page 229: ...led operation refer to section 13 34 Set Features EFh on page 163 Reserved all remaining codes Reserved Reserved Table 148 SET FEATURES command coverage Features Register Features Name Implementation for Travelstar 4K120 02h Enable write cache Yes 03h Set transfer mode Yes 05h Enable Advanced Power Management Yes 06h Enable Power Up in Standby feature set Yes 07h Power Up in Standby device spin up...

Page 230: ...ture Yes BBh Set 4 bytes ECC Yes C2h Disable Automatic Acoustic Management Yes CCh Enable reverting to power on defaults Yes DDh Disable release interrupt No DEh Disable SERVICE interrupt No others Reserved Reserved Table 148 SET FEATURES command coverage Features Register Features Name Implementation for Travelstar 4K120 ...

Page 231: ...avelstar 4K120 Hard Disk Drive Specification 217 15 3 Changes from the Travelstar 5K100 The changes between the Travelstar 5K100 and the Travelstar 4K120 are listed below Identify device information data ...

Page 232: ...Travelstar 4K120 Hard Disk Drive Specification 218 ...

Page 233: ...atted 11 CE mark 37 Check Power Mode 103 Command descriptions 97 Command overhead 17 Command protocol 91 Command table 82 Commands Support Coverage 213 Conductive noise 27 Control electronics 9 Corrosion test 27 CSA approval 38 C TICK mark 37 Cylinder allocation 12 Cylinders heads sectors by model 122 D Data 11 Data In commands 91 Data Out Commands 92 Data Reliability 28 Data sheet 11 ...

Page 234: ... Drive ready time 19 E Electrical interface specification 39 Electromagnetic compatibility 37 Emergency unload 30 Environment 25 Execute Device Diagnostic 107 F Failure prediction S M A R T 28 Features Register 66 Fixed disk subsystem 9 Fixed disk subsystem description 9 Flammability 38 Flush Cache 108 Format Track 110 Format Unit 111 H Head disk assembly data 9 Humidity 25 I Identify Device 112 I...

Page 235: ... Mode transition time 20 Mounting hole locations 32 Mounting orientation 32 N Non data commands 93 O Operating modes description 19 P Packaging 38 Performance characteristics 17 PIO timings 45 Power consumption effiency 28 Power management commands 74 Power management features 74 Power off considerations 72 Power Off Sequence 30 Preventive maintenance 29 Protected Area Function 83 ...

Page 236: ...M A R T Function 76 Safety 38 Secondary circuit protection 38 Sector Addressing Mode 73 Sector Count Register 67 Security Disable Password 153 Security Erase Unit 155 Security Set Password 158 Security Unlock 160 Seek 161 Seek Overlap 87 Seek time average 17 full stroke 18 single track 18 Sense Condition 162 Service life 29 Set Features 163 Set Max ADDRESS 165 Set Max ADDRESS EXT 167 Set Multiple ...

Page 237: ...evels 36 Specification 25 Standby 188 Standby timer 75 Status 75 Status Register 67 T Temperature 25 Time out values 211 Transition time 76 U UL approval 38 V Vibration 34 W Write Buffer 190 Write Cache function 87 ...

Page 238: ......

Page 239: ...istered trade marks of their respective companies References in this publication to Hitachi Global Storage Technologies products programs or services do not imply that Hitachi Global Storage Technologies intends to make these available in all countries in which Hitachi Global Storage Technologies operates Product information is provided for information pur poses only and does not constitute a warr...

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