Hitachi HTC426020G7CE10 Specifications Download Page 10

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K6610170
Rev.2
Dec 22, 2004

- 10 -

8.2. Ultra DMA Data Transfer Timing........................................................................................................133

8.3. Power On and Hardware Reset Timing .............................................................................................143

Summary of Contents for HTC426020G7CE10

Page 1: ...4K60 30 20 REV 2 Models HTC426030G7CE00 HTC426020G7CE10 Caution for Safety Read Safety descriptions carefully Read and recommend drive usage cautions to your end user Keep this manual with care Total 144 pages H I T A C H I 2004 Hitachi Global Storage Technologies All rights reserved ...

Page 2: ...K6610170 Rev 2 Dec 22 2004 2 Rev 1 Nov 19 2004 Rev 2 Dec 22 2004 ...

Page 3: ...rive usage in this manual Protect yourself The safety instructions in this manual were thoroughly considered but unexpected situations can occur Not only follow the instructions on this manual but also be careful for the safety of yourself Headline of safety caution Safety instructions and cautions are indicated as the following headline which consists a word of Caution The indication and meaning ...

Page 4: ...ons This product meets the following safety regulations but the system side should consider the safety of the system with this product Regulations UL1950 Third Edition dated July 28 1995 CSA C22 2 N0 950 M95 IEC60950 A4 1996 EN60950 A11 1992 Warranty and Limited Liability This product is sold with a limited warranty and specific remedies are available to the original purchaser in the event the pro...

Page 5: ...uired over current protection for possible combustion due to circuit or component failure Secondary over current protection shall be prepared by the system The requirement of the current limitation is max 10 A for the protection 11 Improper insertion of connector or wrong jumper setting may cause catastrophic failures Referring to this manual prior to the connector insertion or jumper setting can ...

Page 6: ...ery 21 Data may be lost due to unexpected or accidental power loss during write operation NOTE TO USERS While every effort has been made to ensure that the information provided herein is correct please feel free to notify us in the event of an error or inconsistency Hitachi makes no representations or warranties with respect to the contents hereof and specifically disclaims any implied warranties ...

Page 7: ... Test Condition 21 4 2 3 Attention for HDD Installation 22 4 3 Dimensions 23 5 0 Packing and Handling 24 5 1 Packing 24 5 2 Handling 25 6 0 Physical Interface 26 6 1 Power Interface 26 6 2 Physical Interface 27 6 2 1 Connector 27 6 2 2 Connector Specification 28 6 2 3 Connector Pin Assignment 28 6 2 4 Description of the Interface Signals 29 7 0 Logical Interface 31 7 1 I O Registers 31 7 1 1 Data ...

Page 8: ... Power Mode 98h E5h 55 7 5 2 Device Configuration Identify B1h Sub 02h 55 7 5 3 Device Configuration Freeze Lock B1h Sub 01h 57 7 5 4 Device Configuration Restore B1h Sub 00h 57 7 5 5 Device Configuration Set B1h Sub 03h 58 7 5 6 Execute Device Diagnostic 90h 62 7 5 7 Flush Cache E7h 63 7 5 8 Flush Cache EXT EAh 63 7 5 9 Format Track 50h Vendor Specific 64 7 5 10 Identify Device ECh 64 7 5 11 Idle...

Page 9: ...4 SMART Disable Operations B0h Sub D9h 105 7 5 45 SMART Enable Disable Automatic Off line B0h Sub DBh 106 7 5 46 SMART Enable Disable Attribute AUTOSAVE B0h Sub D2h 107 7 5 47 SMART Enable Operations B0h Sub D8h 108 7 5 48 SMART Execute Off line Immediate B0h Sub D4h 109 7 5 49 SMART Read Log Sector B0h Sub D5h 112 7 5 50 SMART Return Status B0h Sub DAh 119 7 5 51 SMART Save Attribute Values B0h S...

Page 10: ...K6610170 Rev 2 Dec 22 2004 10 8 2 Ultra DMA Data Transfer Timing 133 8 3 Power On and Hardware Reset Timing 143 ...

Page 11: ...er 2MB Read ahead Cache Write Cache Auto Read Reassign Auto Write Reassign SMART Average Access Time 15 ms Embedded Sector Servo FDB Fluid Dynamics Bearing Motor Rotary Actuator Load Unload Mechanism 46 grams Low Power Consumption 0 25W at Idle mode 0 08W at Standby mode Advanced Power Management APM Non operating Shock 11 760m S 2 1200G 1ms half sine wave Operating Shock 4 900m S 2 500G 2ms half ...

Page 12: ...y HDA seal label is broken b Hot swapping Power on damages the drive The drive should be swapped during Power Off only c Shock can result in permanent damage to the drive and or loss of data Prevent shocks often incurred by dropping knocking over or hitting the drive Dropping Knocking over Hitting Hitting Figure 1 1 Caution PREVENT SHOCKS Caution ...

Page 13: ...K6610170 Rev 2 Dec 22 2004 13 2 0 Components Travelstar C4K60 30 20 Disk Drive Figure 2 1 Overview of Travelstar C4K60 30 20 7 0mm height ...

Page 14: ...ecording density Max 32 8 832 28 1 713 Mbpm kBPI Track density 4 65 118 0 4 13 105 0 Mtpm kTPI Recording method ME2 PRML ID Less format 5 Interface ATA 6 IDE Data transfer rate Disk Buffer 18 4 34 0 15 9 29 7 MB sec Data transfer rate Host Buffer Max 16 6 MB sec PIO mode 4 Multiword DMA mode 2 Max 100 Ultra DMA mode 5 MB sec Buffer size 2 048 kB 6 Power on Ready 2 5 Typical 3 sec Sleep Standby Rea...

Page 15: ...A of this drive and in the nominal condition in which the power voltage and the temperature are 3 3V and 25 C respectively The DC power input has to be burst free common mode The average current may have some tolerance after power on The current measurement is recommended at 5 minutes later after power on Voltage rise time 5 100 ms at power on is required for power supply The power supply voltage ...

Page 16: ...sive vapors salt or organic metal compound ex organic silicon organic tin Idle Typical 1 6 Bels 6 Acoustic noise 3 seek Typical 2 2 Bels 7 Height Operational 3 000m or less Altitude Non operational 12 000m or less Height gradient Max 300m min 3 1kpa min 8 4 Data reliability with retries and ECC Less than 1 non recoverable error in 10 E 13 bits read 9 External magnetic field 1 500 micro Tesla DC or...

Page 17: ...des The heads are unloaded during Power off Standby Sleep or Low Power Idle modes The spindle motor is stopped during Standby and Sleep modes This drive is not designed or intended to be used for 24 7 applications Continuous motor spinning should be limited to 48 hours period In case of continuous POH condition the transition to Standby mode or Sleep mode must occur at least once every 48 hours pe...

Page 18: ...nload can not be performed by the software control after power off the heads are unloaded by a hardware control The maximum number of emergency unload is defined separately 3 4 3 Required Power Off Sequence To operate the load unload normally the following BIOS sequence is required by Host system before power off Sequence 1 Execute one of following commands Standby Standby Immediate Sleep Note Suc...

Page 19: ...K6610170 Rev 2 Dec 22 2004 19 4 0 Installation 4 1 Installation Direction The Travelstar C4K60 30 20 can be installed in the 6 directions as shown below Figure 4 1 Installation ...

Page 20: ...ngagement of 2 3mm max ii The torque for fixing the screws is 2 5 0 5kgcm 2 2 0 4 lb inch c Consider an appropriate cooling to keep the temperature of center of HDD top cover less than 65 C d The inertia of the chassis around the Z axis of the gravity center of the device must be more than 3 X 10 4 kg m2 Note In case of general Sub Notebook PC Weight 1 7kg the inertia of the chassis around the Z a...

Page 21: ...ft sponge sheet or slippery hard desk surface the HDD has unstable conditions such as HDD self vibration at seek operations or spindle motor rotation It may cause performance reduction or some errors Also HDD floating by tension of I F cabling may cause the similar symptom The HDD should be placed without any floating Don t test the HDD under these unstable conditions 3 If the HDD cannot be fixed ...

Page 22: ...kept for the steel plate it may affect Load Unload mechanism 2 The PCBA side of the drive should be covered with insulation sheet if the active metal of host system may contact to the PCBA of the drive If the insulation sheet is not provided for the possible contact of the live metal failures may occur 3 Do not push the bottom PCBA It may cause catastrophic failures Caution Steel Plate PCBA Insula...

Page 23: ...K6610170 Rev 2 Dec 22 2004 23 4 3 Dimensions Figure 4 4 Dimensions Unit mm ...

Page 24: ...er cushion material separating them 4 Indicate which side is upside or downside on the exterior of the package box and attach notes requesting careful treatment and preventing the box from being turned upside down 5 Prevent excessive pressure from being applied on the top and bottom of the drive top cover and PCBA side when packing unpacking and transporting 6 Remember mishandling of a drive can v...

Page 25: ... vibration shock and static electricity to the drive because it will damage the precision parts In particular prevent vibration or shock generated by dropping knocking over or hitting the drive Also avoid touching the electrical components directly which can discharge electrostatic energy and damage the drive Dropping Knocking over Hitting Hitting Figure 5 1 Caution ...

Page 26: ...10170 Rev 2 Dec 22 2004 26 6 0 Physical Interface 6 1 Power Interface Figures 6 1 shows typical power current transitions after turning on the power Figure 6 1 Power Current Transition 0 2sec div 0 1A div ...

Page 27: ...K6610170 Rev 2 Dec 22 2004 27 6 2 Physical Interface 6 2 1 Connector Figure 6 2 Connector Location 0 5mm pitch 40 pin ZIF type connector pin 1 ...

Page 28: ...rity 5 Durability is 20 times with the same connector and FPC 6 FPC holding force is min 8 0N Please secure appropriate margin in the FPC length not to apply excessive force on shock 6 2 3 Connector Pin Assignment Table 6 1 Connector pin assignment pin signal name pin signal name pin signal name pin signal name 1 factory use 11 DD4 21 GROUND 31 DA1 2 factory use 12 DD11 22 DMARQ 32 PDIAG 3 RESET 1...

Page 29: ...mination of the Ultra DMA burst DIOR 25 I Activating this Read Strobe signal enables data from a register on the device to be clocked onto the host data bus The rising edge of this signal latches data at the host HDMARDY 1 This signal is a flow control signal for Ultra DMA Read Host asserts this signal and indicates that the host is ready to receive Ultra DMA Read data HSTROBE 1 This signal is Wri...

Page 30: ...The device shall assert this signal used for DMA data transfers between host and device when it is ready to transfer data DMACK 29 I The host in response to DMARQ to either acknowledge that data has been accepted or that data is available shall use this signal DEVADR 40 I The device is configured as either Device 0 Master or Device 1 Slave depending upon the signal level of 40 pin DEVADR signal Wh...

Page 31: ...ta 0 1 0 0 1 Error Features 0 1 0 1 0 Sector Count Sector Count 0 1 0 1 1 LBA Low Sector Number LBA Low Sector Number 0 1 1 0 0 LBA Mid Cylinder Low LBA Mid Cylinder Low 0 1 1 0 1 LBA High Cylinder High LBA High Cylinder High 0 1 1 1 0 Device Head Device Head 0 1 1 1 1 Status Command Control Block Registers 1 0 1 1 0 Alt Status Device Control Invalid or Not Used 0 0 Invalid address 0 1 Data bus hi...

Page 32: ...r is not found UNC Uncorrectable Data Error This bit indicates that an uncorrectable error or an data address mark not found has occurred ICRC Interface CRC Error This bit indicates that an interface CRC error was occurred This bit is not applied for Multiword DMA transfers 7 1 3 Features Register By combining with the Set Features command this register is used for enabling or disabling each featu...

Page 33: ...e defined otherwise on some commands These definitions are given in the command descriptions 7 1 7 LBA High Register Cylinder High Register This register in CHS mode contains the higher 8 bits of the starting cylinder address for any disk access In LBA mode and 28 bit addressing the register contains bits 23 16 of the LBA address When 48 bit addressing commands are used the most recently written c...

Page 34: ...ady to transfer data between the host and the device DSC Device Seek Complete This bit indicates that the device head is located on the specified track If an error has occurred the value of this bit is not changed until the host reads the Status register DFW Device Write Fault This bit indicates that an error has occurred during a Write operation If an error has occurred the value of this bit is n...

Page 35: ...ad the previous content of the Features Sector Count LBA Low LBA Mid and LBA High Registers HOB 0 The host can read the most recently written content of the above registers The device clears HOB bit to zero by a write to any command block register nIEN Interrupt Enable If the device is selected when nIEN is 0 the INTRQ signal is enabled When nIEN is 1 or when the device is not selected the INTRQ s...

Page 36: ... of the register is moved to previous content location The host may read the previous content of the Sector Count LBA Low LBA Mid and LBA High Registers by first setting the High Order Bit HOB bit 7 of the Device Control register to one and then reading the desired register If HOB bit 7 in the Device Control register is cleared to zero the host reads the most recently written content when the regi...

Page 37: ...eady to receive commands but the spindle motor is stopped If the device receive a command with seek operation the spindle motor is rotated and the command is executed Sleep mode This mode is the lowest power mode The spindle motor is stopped The device can not receive the command except Hardware Reset and Software Reset Standby Standby Immediate and Sleep commands are executed with the following p...

Page 38: ...eature command Enable Advanced Power Management sub command Command Code EFh Features 05h Set Feature command Disable Advanced Power Management sub command Command Code EFh Features 85h The Enable Advanced Power Management sub command enables the APM operation set by the Sector Count Register The Disable Advanced Power Management sub command disables the APM operation If the APM operation is disab...

Page 39: ...he status of the device Attributes are selected by the device manufacturer based on that attribute s ability to contribute to the prediction of degrading or fault conditions for that particular device The specific set of attributes being used and the identity of these attributes is vendor specific and proprietary Attribute values are used to represent the relative reliability of individual perform...

Page 40: ...deliver the error information using the SMART READ LOG SECTOR command If SMART is disabled by the host the device does not disable SMART device error log Disabling SMART will only disable the delivering of error log information via the SMART READ LOG SECTOR command If a device receives a firmware modification all error log data will be discarded and the device error count for the life of the devic...

Page 41: ...evice When the security level is set to High the device requires the SECURITY UNLOCK command and the Master password to unlock When the security level is set to Maximum the device requires a SECURITY ERASE PREPARE command and a SECURITY ERASE UNIT command with the master password to unlock The SECURITY FREEZE LOCK command prevents changes to passwords until a following power cycle The purpose of t...

Page 42: ...m Power on or Hardware Reset When lock is enabled the device reject media access commands until a SECURITY UNLOCK command is successfully completed Power on Locked mode UNLOCK ERASE Media access Non media PREPARE access No Password ERASE Reject match UNIT Command Execute Command Yes Unit erased Unlock mode Lock function disabled Normal operation all commands are available FREEZE LOCK Normal operat...

Page 43: ...aster password If the user password is lost and Maximum security level is set data access is impossible However the device is unlocked using the SECURITY ERASE UNIT command with the master password to unlock the device and erase all user data User password lost High Level UNLOCK with master password Maximum ERASE PREPARE Normal operation ERASE UNIT with master password Normal operation but data lo...

Page 44: ...LE OPERATIONS SMART ENABLE DISABLE AUTOSAVE SMART ENABLE OPERATIONS SMART RETURN STATUS SMART SAVE ATTRIBUTE VALUES SMART READ LOG SECTOR SMART WRITE LOG SECTOR Executable Executable Executable RECALIBRATE SEEK READ BUFFER WRITE BUFFER INITIAL DEVICE PARAMETERS IDENTIFY DEVICE EXECUTE DEVICE DIAGNOSTICS SET MULTIPLE MODE SET FEATURE IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP READ DMA READ...

Page 45: ...r SET MAX ADDRESS EXT command is immediately preceded by a READ NATIVE MAX ADDRESS or READ NATIVE MAX ADDRESS EXT command After the SET MAX ADDRESS or SET MAX ADDRESS EXT command has been issued the device reports only the reduced user address space in response to an IDENTIFY DEVICE command in words 60 61 100 101 102 and 103 Any read or write command to an address above the maximum address specifi...

Page 46: ... SET MAX commands including Set Max Unlock until the next power cycle When this command is accepted the device is in the Set Max Frozen mode 7 2 6 Address Offset Feature Vendor Specific Computer systems perform initial code booting by reading from a predefined address on a disk drive To allow an alternate bootable operating system to exist in a reserved area on disk drive Address Offset Feature pr...

Page 47: ...Mode A reserved area has been created using a non volatile SET MAX ADDRESS command or SET MAX ADDRESS EXT command User Accessible Area Reserved Area LBA 0 LBA R LBA M After Enable Address Offset Mode The former reserved area is now the user accessible area The former user accessible area is now the reserved area User Accessible Area former Reserved Area Reserved Area former User Accessible Area LB...

Page 48: ...gs made by a DEVICE CONFIGURATION SET command are maintained over power down and power up A DEVICE CONFIGURATION IDENTIFY command indicates the selectable commands modes capacity and feature sets that the device is capable of supporting After the execution of DEVICE CONFIGURATION SET command this information is no longer available from an IDENTIFY DEVICE command A DEVICE CONFIGURATION RESTORE comm...

Page 49: ...If the device cannot recover the data by this auto write reallocation the device reports the error as follows a The error occurred when the command execution is on going the error is reported for the current command b The error occurred when the command execution is not on going the error is reported for by the next command In case of non write cache mode the device reports the write command compl...

Page 50: ... another sector block is required the device also sets BSY and the above sequence is repeated from 4 7 3 2 PIO Data Out Command Execution includes the transfer of one or more 512 byte sectors of data from the host to the device 1 The host writes any required parameters to the Features Sector Count LBA Low Sector Number LBA Mid Cylinder Low LBA High Cylinder High and Device Head Registers 2 The hos...

Page 51: ...erates the interrupt to the host when the data transfer has completed 7 The host resets the slave DMA channel 8 The host reads the Status Register In response to the Status Register being read the device negates INTRQ 7 3 4 Non Data Command Execution of these commands does not involve any data transfer 1 The host writes any required parameters to the registers 2 The host writes the command code to...

Page 52: ...MA DM 1 C8h C9h V V V V V Read Verify ND 1 40h 41h V V V V V Read Sectors EXT PI 1 V 24h V V V V LD Read Multiple EXT PI 1 V 29h V V V V LD Read DMA EXT DM 1 V 25h V V V V LD Read Verify Sectors EXT ND 1 V 42h V V V V LD Write Commands Write Buffer PO 2 E8h D Write Sectors PO 2 30h 31h V V V V V Write Long PO 2 32h 33h V V V V V Write Multiple PO 2 C5h V V V V V Write DMA DM 2 CAh CBh V V V V V Fo...

Page 53: ...E1h D Sleep ND 1 99h E6h D Standby ND 1 96h E2h V D Standby Immediate ND 1 94h E0h D Unload Immediate ND 1 E1h 44h 00h 4Ch 4Eh 55h D SMART Commands SMART Enable Disable Auto Save ND 1 B0h D2h V V D SMART Save Attribute Values ND 1 B0h D3h V D SMART Enable Operations ND 1 B0h D8h V D SMART Disable Operations ND 1 B0h D9h V D SMART Return Status ND 1 B0h DAh V D SMART Enable Disable Automatic Off li...

Page 54: ... F9h 01h D Set Max Lock ND 1 F9h 02h D Set Max Unlock PO 2 F9h 03h D Set Max Freeze Lock ND 1 F9h 04h D Device Configuration Overlay Device Configuration Restore ND 1 B1h C0h D Device Configuration Freeze Lock ND 1 B1h C1h D Device Configuration Identify PI 1 B1h C2h D Device Configuration Set PO 2 B1h C3h D PI PIO Data In PO PIO Data Out ND Non Data DM DMA Data In Out 48 bit LBA 48 bit Addressing...

Page 55: ...nterrupt 7 5 2 Device Configuration Identify B1h Sub 02h Task File Register 7 6 5 4 3 2 1 0 Command B1h LBA High XX LBA Mid XX LBA Low XX Device Head X X X DRV X X X X Sector Count XX Features 02h The DEVICE CONFIGURATION IDENTIFY command returns a 512 byte data structure via PIO data in transfer The content of this data structure indicates the selectable commands modes and feature sets that the d...

Page 56: ...he factory default condition If no DEVICE CONFIGURATION SET command has been executed modifying the factory default condition 30GB 037E 3E3Fh 20GB 0254 297Fh 7 Command Set Feature Set Supported bit 15 9 0 Reserved bit 14 0 Reserved bit 13 0 Reserved bit 12 1 SMART selective self test supported bit 11 1 Forced Unit Access feature set supported bit 10 0 Reserved bit 9 0 Reserved bit 8 1 48 bit Addre...

Page 57: ...RATION FREEZE LOCK condition is not cleared by hardware or software reset If the device has executed a previous DEVICE CONFIGURATION FREEZE LOCK command since power up the device returns command aborted 7 5 4 Device Configuration Restore B1h Sub 00h Task File Register 7 6 5 4 3 2 1 0 Command B1h LBA High XX LBA Mid XX LBA Low XX Device Head X X X DRV X X X X Sector Count XX Features 00h The DEVICE...

Page 58: ...is set in the overlay transmitted by the device that is not set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command no action is taken for that bit The format of the overlay transmitted by the device is described in following table Table 7 6 DEVICE CONFIGURATION SET command Data Structure Word Description 0 Data Structure Revision Word 0 contains the value 0002h 1 Multiword DMA mo...

Page 59: ...port for Ultra DMA mode 2 This bit shall not be cleared if Ultra DMA mode 5 4 or 3 is supported or if Ultra DMA mode 5 4 3 or 2 is selected bit 1 1 Ultra DMA mode 1 and below are supported Bit 1 is cleared to select no support for Ultra DMA mode 1 This bit shall not be cleared if Ultra DMA mode 5 4 3 or 2 is supported or if Ultra DMA mode 5 4 3 2 or 1 is selected bit 0 1 Ultra DMA mode 0 is suppor...

Page 60: ... Reserved bit 3 1 Security feature set supported Bit 3 is cleared to select no support for the Security feature set This These bits shall not be cleared if the Security feature set has been enabled bit 2 1 SMART error log supported Bit 2 is cleared to select no support for the SMART error logging bit 1 1 SMART self test supported Bit 1 is cleared to select no support for the SMART self test bit 0 ...

Page 61: ...A Low Register Sector Number Register If the command was aborted because an attempt was made to modify a mode or feature that cannot be modified with the device in its current state these registers contain bits 15 0 set in the bit positions that correspond to the bits in the device configuration overlay data structure words 1 2 or 7 for each mode or feature that cannot be changed If not the value ...

Page 62: ...lf diagnostics When Device 0 and Device 1 are connected in the daisy chain mode this command is executed for both of the devices When the device receives this command it sets BSY 1 and executes the self diagnostic operation Then the device registers the diagnostic result in the Error Register clears BSY and generates an interrupt Table 7 7 Diagnostic Codes Code Contents 01 No Error 02 Controller e...

Page 63: ...s which had the first error during write cache is reported on Task File Register 7 5 8 Flush Cache EXT EAh Task File Register 7 6 5 4 3 2 1 0 Command EAh Feature Previous setting XX Current setting XX LBA High Previous setting XX Current setting XX LBA Mid Previous setting XX Current setting XX LBA Low Previous setting XX Current setting XX Sector Count Previous setting XX Current setting XX Devic...

Page 64: ... filled with 512 bytes of data the device clears DRQ sets BSY and begins the command execution Transferred single sector data is ignored This command is used only in the physical mode but the physical mode is not released If the device is not in the physical mode the device executes a vendor specific operation 7 5 10 Identify Device ECh Task File Registers 7 6 5 4 3 2 1 0 Command ECh LBA High XX L...

Page 65: ...Number of logical sectors per logical track See Table 7 9 7 9 Vendor Specific 10 19 Serial Number 20 ASCII characters 20 Retired 0000h 21 Retired 0000h 22 Number of ECC bytes passed on READ WRITE LONG commands 0004h 23 26 Firmware Revision 8 ASCII Characters 27 46 Model number 40 ASCII Characters 47 Number of sectors on multiple commands bit 15 8 80h Fixed bit 7 0 Number of sectors on multiple com...

Page 66: ...ultiple sector setting bit 15 9 0 Reserved bit 8 1 Multiple sector setting is valid bit 7 0 Current setting for number of sectors that can be transferred per interrupt on R W MULTIPLE command 60 61 Total addressable LBA See Table 7 9 62 Obsolete 0000h 63 Multi word DMA transfer bit 15 8 Multi word DMA transfer mode active bit 7 0 Multi word DMA transfer mode supported 64 Flow control PIO transfer ...

Page 67: ...ite cache supported bit 4 1 PACKET command feature set supported bit 3 1 Power management feature set supported bit 2 1 Removable feature set supported bit 1 1 Security feature set supported bit 0 1 SMART feature set supported 746Bh 83 Command set supported bit 15 0 Fixed bit 14 1 Fixed bit 13 1 Flush cache EXT command supported bit 12 1 Flush cache command supported bit 11 1 Device configuration ...

Page 68: ...Card Path Though Command feature set supported bit 2 1 Media Serial Number supported bit 1 1 SMART self test supported bit 0 1 SMART error logging supported 60E3h 85 Command set feature enabled bit 15 0 Reserved bit 14 1 NOP command supported bit 13 1 READ BUFFER command supported bit 12 1 WRITE BUFFER command supported bit 11 0 Reserved bit 10 1 Host Protected Area feature set supported bit 9 1 D...

Page 69: ...AD FEATURE supported bit 12 11 0 Reserved bit 10 1 WRITE STREM URG bit supported bit 9 1 READ STREAM URG bit supported bit 8 1 64 bit World wide name supported bit 7 1 WRITE DMA QUEUED FUA EXT command supported bit 6 1 WRITE DMA MULTIPLE FUA EXT commands supported bit 5 1 General Purpose Logging feature set supported bit 4 1 Valid CONFIGURE STREAM command has been executed bit 3 1 Media Card Pass ...

Page 70: ...value of the Master password revision code set when the Master Password was last changed XXXXh 93 Hardware reset result bit 15 0 fixed bit 14 1 fixed bit 13 1 Device detected CBLID above ViH 0 Device detected CBLID below ViL bit 12 8 Device 1 hardware reset result Device 1 clears these bits to zero Device 1 sets these bits as follows bit 12 0 Reserved bit 11 1 Device 1 asserted PDIAG bit 10 9 Thes...

Page 71: ...ity frozen bit 2 1 Security locked bit 1 1 Security enabled bit 0 1 Security supported 0XXXh 129 159 Vendor Specific 160 254 Reserved 0000h 255 Integrity Word Bit 15 8 Checksum The checksum is the two s complement of the sum of all bytes in word 0 through 254 and the byte consisting of bit 7 0 in word 255 Each byte is added with unsigned arithmetic and overflow is ignored Bit 7 0 Signature Code A5...

Page 72: ...es XX The IDLE command causes the device to enter to the Active Idle Mode The Sector Count Register sets the standby timer value By the power on default the Standby timer is disabled Table 7 10 Standby Timer Sector Count Value Standby Timer Value SC 0 Disabled Power on default 0 SC 240 SC X 5 sec 5 sec to 20 minutes 241 SC 251 253 30 minutes 252 21 minutes 254 255 21 minutes 15 sec Default Power o...

Page 73: ...and latched The time to complete the unload operation is typically within 500 milliseconds of receiving the command The unload controlling method by the Unload Feature of the Idle Immediate command is the same as that by power mode transition and does not effect the specification of normal load unload times per device life The device stops read look ahead operation if it is in process If the devic...

Page 74: ...er that specifies the number of sectors per track and the Device Head Register that specifies the number of heads minus 1 The sector count and head values are not checked for validity by this command If they are invalid no error will be posted until an illegal access is made by some other command 7 5 14 Read Buffer E4h Task File Registers 7 6 5 4 3 2 1 0 Command E4h LBA High XX LBA Mid XX LBA Low ...

Page 75: ...unt Sector count Features XX This command executes in a similar manner to the READ SECTORS command except for the following The host initializes a slave DMA channel prior to issuing the command Data transfers are qualified by DMARQ and are performed by the slave DMA channel The device issues only one interrupt per command indicating that data transfer has terminated and status is valid If an error...

Page 76: ...nt bit 15 8 Current setting Sector Count bit 7 0 Device X 1 X DEV X X X X This command executes in a similar manner to the READ SECTORS EXT command except for the following The host initializes a slave DMA channel prior to issuing the command Data transfers are qualified by DMARQ and are performed by the slave DMA channel The device issues only one interrupt per command indicating that data transf...

Page 77: ...X X X X The READ LOG EXT command returns the specified log to the host If the feature set associated with the log specified in the LBA Low register is not supported or enabled or if the values in the Features Sector Count LBA Mid or LBA High registers are invalid the device returns command aborted Sector Count Register Specifies the number of sectors to be read from the specified log The log trans...

Page 78: ...s reported size of each log sector address The following table defines 512 bytes that make up the General Purpose Log Directory Table 7 12 General Purpose Log Directory Byte Description 0 1 SMART Logging Version 0001h 2 3 Number of sectors in the log at log sector address 01h 4 5 Number of sectors in the log at log sector address 02h 510 511 Number of sectors in the log at log sector address FFh 7...

Page 79: ...o s complement of the sum of the first 511 bytes in the first sector Subsequent 0 3 Reserved Sector 4 127 4n 1 Extended Error log data structure N 128 251 4n 2 Extended Error log data structure 252 375 4n 3 Extended Error log data structure 1 N 63 376 499 4n 4 Extended Error log data structure 500 510 Reserved 511 Data structure checksum Two s complement of the sum of the first 511 bytes in the su...

Page 80: ...d register was written n 9 n 10 Content of the LBA High Register when the Command register was written n 11 Content of the Device Head register when the Command register was written n 12 Content of the Command Register when Command Register was written n 13 Reserved n 14 n 17 Timestamp Time since power on in milliseconds when command acceptance occurred 3 Error data structure The error data struct...

Page 81: ...499 Vendor Specific 500 510 Reserved 511 Data structure checksum 1 Extended Self test log descriptor entry Table 7 18 Self test log descriptor entry Byte Description n Content of the LBA Low Sector Number Register This contains the content of the LBA Low Sector Number Register when the Nth self test subcommand was issued n 1 Content of the self test execution status byte This contains the result o...

Page 82: ...ved across power cycles and hardware reset Table 7 19 Delayed LBA Log Sector Byte Decription First 0 Delayed LBA Log Version 01h Sector 1 Reserved 2 3 Number of Delayed LBA entries Contain the total count of Delayed LBA entries 4 9 1st Entry LBA address of 1st re assigned sector 10 11 Power on lifetime of the device in hours when the 1st sector was reallocated 500 505 LBA address of 63rd re assign...

Page 83: ...28 bit LBA address bit 27 24 Sector Count 01h Features XX The READ LONG command performs similarly to the READ SECTORS command except that it returns the data and the ECC bytes contained in the data field of the desired sector During a READ LONG command the device does not check the ECC bytes to determine if there has been a data error Only single sector read long operations are supported The numb...

Page 84: ...ULTIPLE MODE command which must be executed prior to the READ MULTIPLE command sets the block count of sectors to be transferred When the READ MULTIPLE command is issued the Sector Count Register contains the number of sectors not the number of blocks or the block count requested If the number of requested sectors is not evenly divisible by the block count as many full blocks as possible are trans...

Page 85: ...k not on each sector The SET MULTIPLE MODE command which must be executed prior to the READ MULTIPLE EXT command sets the block count of sectors to be transferred When the READ MULTIPLE EXT command is issued the Sector Count Register contains the number of sectors not the number of blocks or the block count requested If the number of requested sectors is not evenly divisible by the block count as ...

Page 86: ...ock registers is the maximum device size as shown in the following tables Task File Registers 7 6 5 4 3 2 1 0 LBA High L 0 Native Maximum Cylinder bit 15 8 L 1 Native Maximum LBA bit 23 16 LBA Mid L 0 Native Maximum Cylinder bit 7 0 L 1 Native Maximum LBA bit 15 8 LBA Low L 0 Native Maximum Sector Number L 1 Native Maximum LBA bit 7 0 Device Head L DRV L 0 Native Max Head L 1 Native Max LBA bit 27...

Page 87: ...urrent setting XX Device X 1 X DEV X X X X The READ NATIVE MAX EXT command returns the native maximum 48 bit LBA of the device which is not affect by SET MAX ADDRESS EXT command or SET MAX ADDRESS EXT command The data returned in the command block registers is the maximum device size as shown in the following tables Task File Register 7 6 5 4 3 2 1 0 LBA High HOB 1 Maximum LBA bit 47 40 HOB 0 Maxi...

Page 88: ...Command Block Registers contain the 28 bit LBA address or the cylinder head sector numbers where the error occurred 7 5 24 Read Sectors EXT 24h Task File Register 7 6 5 4 3 2 1 0 Command 24h Feature Previous setting XX Current setting XX LBA High Previous setting LBA bit 47 40 Current setting LBA bit 23 16 LBA Mid Previous setting LBA bit 39 32 Current setting LBA bit 15 8 LBA Low Previous setting...

Page 89: ...Y command is same as the READ SECTORS command except that DRQ is never set and no data is transferred to the host When the requested sectors have been verified the device clears BSY and generates an interrupt Upon command completion the Command Block Registers contain the 28 bit LBA address or cylinder head sector numbers of the last sector verified If an error occurs the verify terminates at the ...

Page 90: ... Count bit 7 0 Device X 1 X DEV X X X X The READ VERIFY SECTORS EXT command is same as the READ SECTORS EXT command except that DRQ is never set and no data is transferred to the host When the requested sectors have been verified the device clears BSY and generates an interrupt Upon command completion the Command Block Registers contain the 48 bit LBA address of the last sector verified If an erro...

Page 91: ...The SECURITY DISABLE PASSWORD command requests a transfer of a single sector of data from the host The following table defines the content of this sector of information Then the device checks the transferred password If the User password or the Master password match the device disables the lock function This command does not change the Master password that may be reactivated later by setting a Use...

Page 92: ...or if the device is in Frozen mode 7 5 30 Security Erase Unit F4h Task File Registers 7 6 5 4 3 2 1 0 Command F4h LBA High XX LBA Mid XX LBA Low XX Device Head X X X DRV X X X X Sector Count XX Features XX The SECURITY ERASE UNIT command requests a transfer of a single sector of data from the host The following table defines the content of this sector of information If the password does not match ...

Page 93: ...f this command is shown below HTC426030G7CE00 27 minutes HTC426020G7CE10 20 minutes 7 5 31 Security Freeze Lock F5h Task File Registers 7 6 5 4 3 2 1 0 Command F5h LBA High XX LBA Mid XX LBA Low XX Device Head X X X DRV X X X X Sector Count XX Features XX The SECURITY FREEZE LOCK command sets the device to frozen mode After this command is completed any other commands which update the device lock ...

Page 94: ...d 0 bit 0 1 18 255 Reserved The following table defines the interaction of the identifier and security level bits Table 7 23 Security Level and Identifier Identifier Security Level Command Result User High The password supplied with the command is saved as the new user password The lock function will be enabled from the next power on or hardware reset The device will then be unlocked by either the...

Page 95: ... password supplied is compared with the stored master password If the device is in maximum security level then the SECURITY UNLOCK command is rejected If the Identifier bit is set to user then the device compares the supplied password with the stored user password If the password compare fails then the device returns an abort error to the host and decrements the unlock counter This counter is init...

Page 96: ...bit LBA address bit 7 0 Device Head X L X DRV L 0 Head Number L 1 28 bit LBA address bit 27 24 Sector Count XX Features XX The SEEK command initiates a seek operation to the track specified in the Command Block Registers The device returns the interrupt before completion of a seek operation If another command is issued to the device while a seek operation is being executed the device sets BSY wait...

Page 97: ...feature 66h Disable reverting to power on defaults 77h Disable ECC 85h Disable Advanced Power management 2 88h Enable ECC 89h Disable Address Offset Mode 3 99h Enable retries AAh Enable read look ahead feature BBh Enable 4 bytes ECC transfer CCh Enable reverting to power on defaults 02h Enable write cache 82h Disable write cache 1 If the code is not supported the device returns Aborted Command Err...

Page 98: ... command is preserved over power on hardware reset software reset When B 0 Maximum LBA or maximum cylinder which is set by SET MAX ADDRESS command will be lost by power on or hardware reset B set to one is not valid when the device is in Address Offset Mode ABRT is set if B set to one when the device is in Address Offset mode READ NAX ADDRESS command should be issued and completed immediately prio...

Page 99: ... shown in the following tables Output Parameters to the device Task File Registers 7 6 5 4 3 2 1 0 LBA High L 0 Maximum Cylinder bit 15 8 L 1 Maximum LBA bit 23 16 LBA Mid L 0 Maximum Cylinder bit 7 0 L 1 Maximum LBA bit 15 8 LBA Low L 0 Maximum Sector Number 1 L 1 Maximum LBA bit 7 0 Device Head X L X DRV L 0 Maximum head number 1 L 1 Maximum LBA bit 27 24 1 Maximum sector number and maximum head...

Page 100: ...ADDRESS EXT command is preserved over power on hardware reset software reset When B 0 Maximum LBA which is set by SET MAX ADDRESS EXT command will be lost by power on or hardware reset B set to one is not valid when the device is in Address Offset Mode ABRT is set if B set to one when the device is in Address Offset mode READ NAX ADDRESS EXT command should be issued and completed immediately prior...

Page 101: ...Registers 7 6 5 4 3 2 1 0 Command F9h LBA High XX LBA Mid XX LBA Low XX Device Head X X X DRV X X X X Sector Count XX Features 04h The SET MAX FREEZE LOCK command sets the device to Set Max Frozen state After command completion any subsequent SET MAX commands are rejected Commands disabled by Set Max Freeze Lock are SET MAX ADDRESS command SET MAX ADDRESS EXT command SET MAX SET PASSWORD command S...

Page 102: ... If this command is immediately preceded by a READ MAX ADDRESS command it is interpreted as a SET MAX ADDRESS command If the device is not in the Set Max Locked state the device reports command aborted 7 5 40 Set Max Set Password Command F9h Sub 01h Task File Registers 7 6 5 4 3 2 1 0 Command F9h LBA High XX LBA Mid XX LBA Low XX Device Head X X X DRV X X X X Sector Count XX Features 01h The SET M...

Page 103: ...f data transferred is compared with the stored Set Max password If the password compare fails then the device returns command aborted and decrements the unlock counter On the acceptance of the SET MAX LOCK command this counter is set to a value of five and is decrement for each password mismatch when SET MAX UNLOCK command is issued and the device is locked When this counter reaches zero then the ...

Page 104: ...or Count Register contains a valid value then the value is loaded for all subsequent Multiple commands and execution of those commands is enabled If an invalid value is specified an Aborted Command error is posted and execution of the Multiple commands is disabled The Multiple commands cannot be executed in the default mode at power on or after a hardware reset 7 5 43 Sleep 99h E6h Task File Regis...

Page 105: ...onitored or saved by the device The device will preserve the state of SMART either enabled or disabled across power cycles If SMART is not enabled or if the values in the Features LBA Mid Cylinder Low or LBA High Cylinder High registers are invalid an Aborted command error is posted Upon receipt of the SMART DISABLE OPERATIONS command from the host the device sets BSY disables SMART capabilities a...

Page 106: ...d for the Automatic off line feature a Raw Read Error Rate Measurement Partial read scanning and Raw Read Error Rate measurement is performed This event is occurred every 24 POH s and 2 minutes of host inactivity b Automatic sector reallocation in off line read scanning for entire LBA This event occurs every 168 POH s and 2 minutes of host inactivity Enable state is preserved until receiving a dis...

Page 107: ...nto the Sector Count register before issuing this command will cause this feature to be disabled Disabling this feature does not preclude the device from saving attribute values to non volatile memory during some other normal operation A value of F1h written by the host into the Sector Count register before issuing this command will cause this feature to be enabled Upon receipt of the command from...

Page 108: ...mand attribute values are neither monitored nor saved by the device The device will preserve the state of SMART either enabled or disabled across power cycles Once enabled the receipt of subsequent SMART Enable Operations commands does not affect any of the attribute values If the values in the Features LBA Mid Cylinder Low or LBA High Cylinder High registers are invalid an Aborted command error i...

Page 109: ...led during execution The device sets 4Fh to LBA Mid Register and sets C2h to LBA High Register when the subcommand specified a captive self test routine and some error other than a self test routine failure occurred Table 7 28 11 SMART EXECUTE OFF LINE IMMEDIATE LBA Low Register Values Value Description of subcommand to be executed 0 Execute SMART off line routine immediately in off line mode 1 Ex...

Page 110: ...vice is in the process of performing the subcommand routine and is interrupted by a SMART DISABLE OPERATIONS command from the host the device aborts the subcommand routine and services the host within two seconds after receipt of the command f If the device is in the process of performing the subcommand routine and is interrupted by a SMART EXECUTE OFF LINE IMMEDIATE command from the host the devi...

Page 111: ...d settling accuracy Load and Unload function is tested Servo data on the outer track of each zone for each head is verified d Partial read scan test for the first 500MB and the last 300MB 0f the device e Random read test Average seek time and throughput performance are measured in this test f RAM test Diagnoses buffer RAM and SDRAM g SMART parameter verify Detects a threshold exceed condition h SM...

Page 112: ...Features D5h The SMART READ LOG SECTOR command returns the indicated log to the host LBA Low Sector number Register indicates the log to be returned as described in Table 7 11 The host vendor specific logs may be used by the host to store any data desired If a host vendor specific log has never been written by the host when read the content of the log is zeros Device vendor specific logs are used ...

Page 113: ...nvalid addresses Table 7 30 Summary SMART Error Log Byte Description 0 SMART error log version The value of the SMART error log version is 01h 1 Error log index The error log index indicates the error log data structure representing the most recent error Only values 1 through 5 are valid 2 91 First error log data structure 92 181 Second error log data structure 182 271 Third error log data structu...

Page 114: ...ded the command or reset for which the error is being reported the third command data structure contains the command or reset preceding the one in the fourth command data structure etc If fewer than four commands and resets preceded the command or reset for which the error is being reported the unused command data structures are zero filled If the command data structure represents a command or sof...

Page 115: ... Register after command completion occurred n 5 Content of the LBA High Cylinder High Register after command completion occurred n 6 Content of the Device Head register after command completion occurred n 7 Content written to the Status register after command completion occurred n 8 n 25 Extended error information Vendor Specific n 27 State This contains a value indicating the state of the device ...

Page 116: ...on Unused error log data structures are filled with zeros The content of the error log data structure entries is defined in Table 7 31 Table 7 34 Comprehensive SMART Error Log Sector Byte Description First Sector 0 SMART error log version The value of the SMART error log version is 01h 1 Error log index The error log index indicates the error log data structure representing the most recent error O...

Page 117: ...nd entry that replaces the first entry Then the twenty third entry replaces the second entry and so on If fewer than 21 self tests have been performed by the device the unused descriptor entries are filled with zeros The content of the self test descriptor entry is shown in following table Table 7 36 Self test log descriptor entry Byte Description n Content of the LBA Low Sector Number Register Th...

Page 118: ...ld This field shall be written with a value of zero by the host 500 501 Current span under test read As the self test progresses the device modifies this value to contain the test span number of the current span being tested If an off line scan between test spans is selected a value greater then five is placed in this field during the off line scan When the self test including the off line scan be...

Page 119: ...e sets the LBA Mid Cylinder Low Register to F4h and the LBA High Cylinder High Register to 2Ch If SMART is disabled or if the values in the Features LBA Mid Cylinder Low or LBA High Cylinder High registers are invalid an Aborted command error is posted 7 5 51 SMART Save Attribute Values B0h Sub D3h Task File Registers 7 6 5 4 3 2 1 0 Command B0h LBA High C2h LBA Mid 4Fh LBA Low XX Device Head X X ...

Page 120: ...re any data desired using the SMART Write LOG SECTOR command LBA Low Sector Number Register indicated the log to be written as described in Table 7 11 If the host attempts to write to a read only log address the device returns command aborted 7 5 53 Standby 96h E2h Task File Registers 7 6 5 4 3 2 1 0 Command 96h or E2h LBA High XX LBA Mid XX LBA Low XX Device Head X X X DRV X X X X Sector Count St...

Page 121: ... 2 1 0 Command 94h or E0h LBA High XX LBA Mid XX LBA Low XX Device Head X X X DRV X X X X Sector Count XX Features XX The STANDBY IMMEDIATE command causes the device to be spun down and enter the Standby Mode The device returns an interrupt before it has complete transition to the Standby Mode ...

Page 122: ... number bit 7 0 L 1 28 bit LBA address bit 15 8 LBA Low L 0 Sector number L 1 28 bit LBA address bit 7 0 Device Head X L X DRV L 0 Head Number L 1 28 bit LBA address bit 27 24 Sector Count Sector count Features XX This command executes in a similar manner to the WRITE SECTORS command except for the followings The host initializes a slave DMA channel prior to issuing the command Data transfers are ...

Page 123: ...e interrupt per command to indicate that data transfer has terminated and status is valid If an error occurs the write terminates at the sector where the error occurred The command Block Registers contain the 48 bit LBA address where the error occurred 7 5 58 Write DMA FUA EXT 3Dh Task File Register 7 6 5 4 3 2 1 0 Command 3Dh Feature Previous setting XX Current setting XX LBA High Previous settin...

Page 124: ... register is not supported or enabled or if the values in the Features Sector Count LBA Mid or LBA High registers are invalid the device returns command aborted If the host attempts to write to a read only RO log address the device returns command aborted Sector Count Register Specifies the number of sectors that shall be written to the specified log If the number is greater than the number indica...

Page 125: ...es directly from the host the device does not generate the ECC bytes itself Only single sector Write Long operations are supported The transfer of the ECC bytes shall be 8 bits wide The number of ECC bytes transferred will be 4 bytes Default If the ECC transfer length is changed by Features Register 44h 68 bytes of ECC will be transferred 7 5 61 Write Multiple C5h Task File Registers 7 6 5 4 3 2 1...

Page 126: ...dless of the position in the block Subsequent blocks are not transferred in the event of an error Interrupts are generated when DRQ is set at the beginning of transfer of each block except first block 7 5 62 Write Multiple EXT 39h Task File Register 7 6 5 4 3 2 1 0 Command 39h Feature Previous setting XX Current setting XX LBA High Previous setting LBA bit 47 40 Current setting LBA bit 23 16 LBA M...

Page 127: ...hen DRQ is set at the beginning of transfer of each block except first block 7 5 63 Write Multiple FUA EXT CEh Task File Register 7 6 5 4 3 2 1 0 Command CEh Feature Previous setting XX Current setting XX LBA High Previous setting LBA bit 47 40 Current setting LBA bit 23 16 LBA Mid Previous setting LBA bit 39 32 Current setting LBA bit 15 8 LBA Low Previous setting LBA bit 31 24 Current setting LB...

Page 128: ... XX The WRITE SECTORS command transfers one or more sectors from the host to the device The data is then written to the media beginning at the specified in the LBA High Cylinder High LBA Mid Cylinder Low and LBA Low Sector Number Registers At command completion the Command Block Registers contain the cylinder head and sector numbers or LBA address of the last sector written If an error occurs duri...

Page 129: ...ctor Count bit 15 8 Current setting Sector Count bit 7 0 Device X 1 X DEV X X X X The WRITE SECTORS EXT command transfers one or more sectors from the host to the device The data is then written to the media beginning at the specified in the LBA High LBA Mid and LBA Low Registers At command completion the Command Block Registers contain 48 bit LBA address of the last sector written If an error occ...

Page 130: ...s of signals CS0 CS1 and DA2 0 2 Data consists of DD0 15 16 bit or DD0 7 8 bit SYMBOL Description MIN ns MAX ns t0 Cycle Time 120 t1 Address Valid to DIOR DIOW Setup 25 t2 DIOR DIOW Pulse Width 70 t2i DIOR DIOW Recovery 25 t3 DIOW Data Setup 20 t4 DIOW Data Hold 10 t5 DIOR Data Setup 20 t6 DIOR Data Hold 5 t6Z DIOR Data tristate 30 t7 DIOR DIOW to Address Valid Hold 10 t1 t7 t2 t3 t5 t4 t6 Addr Va...

Page 131: ...4 131 Figure 8 2 IORDY Timing SYMBOL Description MIN ns MAX ns tA IORDY Setup Time 35 tB IORDY Pulse Width 1250 tRD Read Data Valid to IORDY active 0 tc IORDY assertion to release 5 tA tB DIOR DIOW IORDY tRD Read Data Valid tC ...

Page 132: ...cess 50 tF DIOR Data Hold 5 tGr DIOR Data Setup 20 tGw DIOW Data Setup 20 tH DIOW Data Hold 10 tI DMACK to DIOR DIOW Setup 0 tJ DIOR DIOW to DMACK Hold 5 tK DIOR DIOW Negated Pulse Width 25 tL DIOR DIOW to DMARQ Delay 35 tM CS 1 0 valid to DIOR DIOW 25 tN CS 1 0 hold 10 tZ DMACK to tristate 25 tM t0 tL tI tD tK tJ tGw tGr tH tF DMARQ DMACK DIOR DIOW Write Data Valid 3 Read Data Valid 3 CS0 CS1 tN ...

Page 133: ... 6 7 4 8 Data valid setup time at sender tDVH 6 2 6 2 6 2 6 2 6 2 4 8 Data valid hold time at sender tFS 230 200 170 130 120 90 First strobe tUI 0 0 0 0 0 0 Unlimited interlock tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to release tZAD 0 0 0 0 0 0 Maximum delay time for output drivers turning on tENV 20 70 20 70 20 70 20 55 20 55 20 50 Envelope time tZIORDY 0 0 0 0 0 0 Minimum t...

Page 134: ...evice Mode 0 ns Mode 1 ns Mode 2 ns Mode3 ns Mode4 ns Mode5 ns Description SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tCYC 112 73 54 39 25 16 8 Cycle time allowing for asymmetry and clock variation t2CYC 230 153 115 86 57 38 Two cycle time allowing for clock variation tDS 15 10 7 7 5 4 Data setup time at recipient tDH 5 5 5 5 5 4 6 Data hold time at recipient tDVS 70 48 31 20 6 7 4 8 D...

Page 135: ...ce tRFS tRP Note The host asserts STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY is negated Mode 0 ns Mode 1 ns Mode 2 ns Mode3 ns Mode4 ns Mode5 ns Description SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tRFS 75 70 60 60 60 50 Ready to final STROBE time tRP 160 125 100 100 100 85 Ready to pause time ...

Page 136: ... MAX MIN MAX MIN MAX MIN MAX MIN MAX tCVS 70 48 31 20 6 7 10 CRC word valid setup time at sender tCVH 6 2 6 2 6 2 6 2 6 2 10 CRC word valid hold time at sender tLI 0 150 0 150 0 150 0 100 0 100 0 75 Limited interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to release tZAH 20 20 20 20 20 20 Minimum delay time for output d...

Page 137: ...AX MIN MAX MIN MAX MIN MAX MIN MAX tCVS 70 48 31 20 6 7 10 CRC word valid setup time at sender tCVH 6 2 6 2 6 2 6 2 6 2 10 CRC word valid hold time at sender tLI 0 150 0 150 0 150 0 100 0 100 0 75 Limited interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to release tZAH 20 20 20 20 20 20 Minimum delay time for output dri...

Page 138: ...de5 ns Description SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tDVS 70 48 31 20 6 7 4 8 Data valid setup time at sender tDVH 6 2 6 2 6 2 6 2 6 2 4 8 Data valid hold time at sender tLI 0 150 0 150 0 150 0 100 0 100 0 75 Limited interlock time tUI 0 0 0 0 0 0 Unlimited interlock tENV 20 70 20 70 20 70 20 55 20 55 20 50 Envelope time tZIORDY 0 0 0 0 0 0 Minimum time before driving IORDY tA...

Page 139: ...by the host Mode 0 ns Mode 1 ns Mode 2 ns Mode 3 ns Mode 4 ns Mode5 ns Description SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tCYC 112 73 54 39 25 16 8 Cycle time allowing for asymmetry and clock variation t2CYC 230 153 115 86 57 38 Two cycle time allowing for clock variation tDS 15 10 7 7 5 4 Data setup time at recipient tDH 5 5 5 5 5 4 6 Data hold time at recipient tDVS 70 48 31 20 6...

Page 140: ...t tRFS tRP Note The device negates DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY is negated Mode 0 ns Mode 1 ns Mode 2 ns Mode 3 ns Mode 4 ns Mde5 ns Description SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tRFS 75 70 60 60 60 50 Ready to final STROBE time tRP 160 125 100 100 100 85 Ready to pause time ...

Page 141: ... Mode 4 ns Mode5 ns Description SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tCVS 70 48 31 20 6 7 10 CRC word valid setup time at sender tCVH 6 2 6 2 6 2 6 2 6 2 10 CRC word valid hold time at sender tLI 0 150 0 150 0 150 0 100 0 100 0 75 Limited interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to release tIOR...

Page 142: ... 0 ns Mode 1 ns Mode 2 ns Mode 3 ns Mode 4 ns Mode5 ns Description SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tCVS 70 48 31 20 6 7 10 CRC word valid setup time at sender tCVH 6 2 6 2 6 2 6 2 6 2 10 CRC word valid hold time at sender tLI 0 150 0 150 0 150 0 100 0 100 0 75 Limited interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tRFS 75 70 60 60 60 50 Ready to final STRO...

Page 143: ... bit tR1 tS DASP PDIAG DRDY tN1 DASP out in out out out Master Slave SYMBOL Description MIN MAX Units TM RESET Pulse Width 25 µs tN0 DRV 0 RESET negation to BSY bit set to one release PDIAD_ 400 ns tP0 DRV 0 release DASP 1 ms tR0 DRV 0 sample of DASP 1 450 ms TS DRV 0 sample of PDIAG 1ms 31s tR1 DRV 1 assert DASP 400 ms tN1 DRV 1 negate PDIAG if asserted 1 ms TQ DRV 1 assert PDIAG 30 sec ...

Page 144: ...ECC Error Checking and Correction ERR Error GND Ground GB 1000 000 000 bytes HD Head HDA Head Disk Assembly HDD Hard Disk Drive I O Input Output ICRC Interface CRC Error IDE Intelligent Device Electronics IDNF ID Not Found IDX Index MB 1000 000 bytes ME2 PRML Modified Extended Extended Partial Response Maximum Likelihood PCBA Printed Circuit Board Assembly PIO Programmed Input output p p peak to p...

Page 145: ...ty 1 Package box Card box 1 2 HDD Cushion Card Board 1 3 Upper Cushion Card Board 1 4 Side Cushion Card Board 4 5 Desiccant Silica gel 50 6 Vinyl Package ESD protective bags 50 2 Standard Identification Label The label is indicated on the exterior of the package The following items will be based on user request a HDD type b HDD serial number c Package serial number d Quantity ...

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