K6610007
Rev.5
02.14.’03
- 37 -
6.3.2.2 Command BSY Timing
The manner in which a command is accepted varies by the three classes of command acceptance all
predicated on the fact that to receive a command, BSY=0. The following describes by the conditions
under which busy is set after receipt of a command.
Class1 - The device sets busy within 400 ns.
Class2 - The device will set BSY within 400 ns, then sets up the sector buffer for a write operation,
then sets DRQ, and clears BSY within 400 ns of setting DRQ.
Note
: DRQ may be set so quickly on classes 2 that the BSY transition is too short for BSY=1 to
be recognized.
6.3.2.3 PIO Data In Commands
Execution includes the transfer of one or more 512 byte sectors of data from the device to the host.
1) The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder
Low, Cylinder High, and Device/Head registers.
2) The host writes the command code to the Command Register.
3) The device sets BSY and prepares for data transfer.
4) When a sector(block) of data is available, the device sets DRQ and clears BSY prior to asserting
INTRQ.
5) After detecting INTRQ, the host reads the Status Register, then reads one sector (block) of data via
the Data Register. In response to the Status Register being read, the device negates INTRQ.
6) The device clears DRQ. If transfer of another sector (block) is required, the device also sets BSY
and the above sequence is repeated from 4).
