Hitachi CL43WP910TAN, Service Manual

Page: 19 / 77

Horizontal and Vertical Synchronisation Connections
Pin 48 is the vertical synchronisation input from the deflection stage. This input is used to ensure that the OSD is displayed
in a stable vertical position. When the TV is in the standby state, this input is normally low. The vertical input is triggered on
the rising edge (positive polarity).
Pin 49 is the horizontal synchronisation input from the deflection stage. This input ensures that the OSD is displayed in
stable horizontal position. When the TV is in the standby state, this input is normally low. This input is rising edge triggered
(positive polarity).
General Input Connections
Headphone Input
Pin 19 is used to detect if the headphone has been inserted into its socket. This input is normally HIGH (+5V) unless the
headphone has been inserted, in which case it is near 0V. When the headphone is inserted, the headphone mode option
is then available in the "Sound Mode" Menu and the loudspeakers (and internal sub-woofer if available) in the television
are muted.
Front Panel Buttons and SAV4 Socket Inputs
Pins 36 and 38 are 2 of the 4 ADC inputs of the microcontroller.
Pin 36 is connected to the /- buttons and the SAV4 (Hi-8) socket on the front panel of the TV. When the voltage
on this pin is changed to a value in a certain window, the microcontroller will interpret it as either a , volume -,
/- command and/or an SVHS Hi-8 connector was inserted into the Hi-8 socket.
Pin 38 is connected to the Pro/- and Menu buttons on the front panel of the TV. When the voltage on this pin is
changed to a value in a certain window, the microcontroller will interpret it as either a programme change or the menu
button was pressed.
General Output Connections
74HC595 Shift Register Outputs
Storage-Register Clock Output (RCLK)
Pin 20 of the microcontroller is connected to the rising edge (positive triggered) input (pin 12) of I006. This line is normally
low when not communicating with the device or when shifting data into it. Once the full 8-bits have been shifted in, the
RCLK line rises in order to latch the data to the device’s outputs.
Shift-Register Clock Output (SCLK)
Pin 17 of the microcontroller (MMU4) is used to transfer the data into to the 8-stage shift-register on the rising edge of the
SCLK. 8 clock pulses are needed to transfer 8 bits of data into the shift register.
Shift-Register Data Output (SI)
Pin 21 of the microcontroller is used as the data line input to pin 14 of the shift register. When this line is HIGH, and the
SCLK changes from low to high, the first bit of data (logical 1) is shifted into the register. When this input is low, the first bit
of data is ‘0’, on the rising edge of the SCLK.