Hitachi 3.5-INCH HDS725050KLA360 Specifications Download Page 56

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Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification

6.8.8 Host Terminating Write DMA

Table 39: Ultra DMA cycle timing chart (Host Terminating Write)

Table 40: Ultra DMA cycle timings (Host Terminating Write)

PARAMETER

DESCRIPTION

(all values in ns)

MODE 0

MODE 1

MODE 2

MODE 3

MODE 4

MODE 5

MODE 6

MIN MAX

MIN

MAX

tSS

Time from HSTROBE edge to asser-
tion of STOP

–

tLI

Limited interlock time

150

100

tMLI

Interlock time with minimum

–

tCS

CRC word setup time at device

–

tCH

CRC word hold time at device

–

tACK

Hold time for DMACK-

–

tIORDYZ

Maximum time before releasing
IORDY

–

HSTROBE

DDMARDY-

DMACK-

DMARQ

STOP

tMLI

DD(15:0)

Host drives DD

tCH

tCS

CRC

tSS

tACK

tLI

tIORDYZ

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

xxxxxxxxxx

tLI

Summary of Contents for 3.5-INCH HDS725050KLA360

Page 1: ...ard Disk Drive Specification Deskstar 7K500 Deskstar E7K500 3 5 inch Ultra ATA 133 hard disk drive 3 5 inch Serial ATA hard disk drive Models HDS725050KLAT80 HDS725050KLA360 Version 1 5 12 September 2006 ...

Page 2: ......

Page 3: ... Disk Drive Specification Deskstar 7K500 Deskstar E7K500 3 5 inch Ultra ATA 133 hard disk drive 3 5 inch Ultra Serial ATA hard disk drive Models HDS725050KLAT80 HDS725050KLA360 Version 1 5 12 September 2006 ...

Page 4: ...porated in new editions of the publication Hitachi may make improvements or changes in any products or programs described in this publication at any time It is possible that this publication may contain reference to or information about Hitachi products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean ...

Page 5: ...itioning 15 4 4 3 Drive ready time 16 4 4 4 Data transfer speed 17 4 4 5 Throughput 18 4 4 6 Operating modes 19 5 0 Defect flagging strategy 21 6 0 Specification 23 6 1 Electrical Interface 23 6 1 1 Connector location 23 6 1 2 4pin DC Power connector 24 6 1 3 AT signal connector 24 6 2 Signal definitions PATA model 25 6 3 Signal descriptions 26 6 4 Interface logic signal levels PATA model 29 6 4 1...

Page 6: ...pical 51 7 3 3 Power supply generated ripple at drive power connector 52 7 4 Reliability 53 7 4 1 Data integrity 53 7 4 2 Cable noise interference 53 7 4 3 Start stop cycles 53 7 4 4 Preventive maintenance 53 7 4 5 Data reliability 53 7 4 6 Required power off sequence 53 7 5 Mechanical specifications 54 7 5 1 Physical dimensions and weight 54 7 5 2 Mounting hole locations 55 7 5 3 Connector locati...

Page 7: ...egister 70 9 10 Error Register 71 9 11 Features Register 71 9 12 Sector Count Register 71 9 13 Sector Number Register 72 9 14 Status Register 72 10 0 General operation 75 10 1 Reset response 75 10 2 Register initialization 76 10 3 Diagnostic and Reset considerations 77 10 4 Sector Addressing Mode 78 10 4 1 Logical CHS addressing mode 78 10 4 2 LBA addressing mode 78 10 5 Power management features ...

Page 8: ... 10 15 3 Exceptions in Address Offset Mode 96 10 16 48 bit Address Feature Set 97 10 17 Streaming Feature Set 97 10 17 1 Streaming commands 98 10 17 2 Urgent bit 98 10 17 3 Flush to Disk bit 98 10 17 4 Not Sequential bit 98 10 17 5 Read Continuous bit 99 10 17 6 Write Continuous bit 99 10 17 7 Handle Streaming Error bit 99 10 17 8 Streaming Logs 99 11 0 Command protocol 101 11 1 PIO Data In comman...

Page 9: ...iple C4h 155 12 20 Read Multiple Ext 29h 157 12 21 Read Native Max ADDRESS F8h 159 12 22 Read Native Max Address Ext 27h 160 12 23 Read Sectors 20h 21h 161 12 24 Read Sector s Ext 24h 163 12 25 Read Stream DMA 2Ah 165 12 26 Read Stream PIO 2Bh 168 12 27 Read Verify Sectors 40h 41h 171 12 28 Read Verify Sector s 42h 173 12 29 Recalibrate 1xh 175 12 30 Security Disable Password F6h 176 12 31 Securit...

Page 10: ...T Log Directory 208 12 42 5 S M A R T summary error log sector 208 12 42 6 Self test log data structure 210 12 42 7 Selective self test log data structure 211 12 42 8 Error reporting 212 12 43 Standby E2h 96h 213 12 44 Standby Immediate E0h 94h 214 12 45 Write Buffer E8h 215 12 46 Write DMA CAh CBh 216 12 47 Write DMA Ext 35h 218 12 48 Write Log Ext 3Fh 220 12 49 Write Long 32h 33h 221 12 50 Write...

Page 11: ...rd DMA cycle timings 34 Table 25 Ultra DMA cycle timing chart Initiating Read 35 Table 26 Ultra DMA cycle timings Initiating Read 35 Table 27 Ultra DMA cycle timing chart Host pausing Read 36 Table 28 Ultra DMA cycle timings Host pausing Read 36 Table 29 Ultra DMA cycle timing chart Host terminating Read 37 Table 30 Ultra DMA cycle timings Host terminating Read 37 Table 31 Ultra DMA cycle timing c...

Page 12: ...ister Values 76 Table 66 Diagnostic codes 76 Table 67 Reset error register values 77 Table 68 Power conditions 80 Table 69 Command table for device lock operation 87 Table 70 Seek overlap 90 Table 71 Enable Disable Address Offset Mode 96 Table 72 Command Set 1 of 2 107 Table 73 Command Set 2 of 2 108 Table 74 Command Set subcommand 109 Table 75 Check Power Mode command E5h 98h 111 Table 76 Configu...

Page 13: ...le 111 Write Stream Error Log 151 Table 112 Streaming Performance Parameters log 151 Table 113 Sector Time Array Entry Linearly Interpolated 152 Table 114 Position Array Entry Linearly Interpolated 152 Table 115 Access Time Array Entry Linearly Interpolated 152 Table 116 Read Long 22h 23h 153 Table 117 Read Multiple C4h 155 Table 118 Read DMA Ext Command 25h 157 Table 119 Read Native Max ADDRESS F...

Page 14: ...ure 207 Table 152 Individual Threshold Data Structure 207 Table 153 S M A R T Log Directory 208 Table 154 S M A R T summary error log sector 208 Table 155 Error log data structure 209 Table 156 Command data structure 209 Table 157 Error data structure 209 Table 158 Self test log data structure 210 Table 159 Selective self test log data structure 211 Table 160 S M A R T Error Codes 212 Table 161 St...

Page 15: ...tion Technology AT Attachment with Packet Interface 7 Serial ATA II Extensions to Serial ATA 1 0 1 3 Abbreviations Abbreviation Meaning A Ampere AC alternating current AT Advanced Technology ATA Advanced Technology Attachment BIOS Basic Input Output System C Celsius CSA Canadian Standards Association C UL Canadian Underwriters Laboratory Cyl cylinder DC Direct Current DFT Drive Fitness Test DMA Di...

Page 16: ...gram force centimeter KHz kilohertz LBA logical block addressing Lw unit of A weighted sound power m meter max maximum MB 1 000 000 bytes Mbps 1 000 000 bits per second MHz megahertz MLC Machine Level Control mm millimeter ms millisecond us ms microsecond O Output OD Open Drain Programmed Input Output POH power on hours Pop population P N part number p p peak to peak PSD power spectral density RES...

Page 17: ...y V volt VDE Verband Deutscher Electrotechniker W watt 3 state transistor transistor tristate logic 1 4 Caution Do not apply force to the top cover Do not cover the breathing hole on the top cover Do not touch the interface connector pins or the surface of the printed circuit board This drive can be damaged by electrostatic discharge ESD Any damages incurred to the drive after its removal from the...

Page 18: ...Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification 4 ...

Page 19: ... KB is used for firmware Ring buffer implementation Write Cache Native command queuing support SATA Advanced ECC On The Fly EOF Automatic Error Recovery procedures for read and write commands Self Diagnostics on Power on and resident diagnostics PIO Register Data Transfer Mode 4 16 6 MB s DMA Data Transfer Multiword mode Mode 2 16 6 MB s Ultra DMA Mode 6 133 MB s Serial ATA Data Transfer3Gbps CHS ...

Page 20: ...Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification 6 ...

Page 21: ...Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive specification 7 Part 1 Functional specification ...

Page 22: ...Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification 8 ...

Page 23: ...error conditions of the servo and takes corresponding action if an error occurs Monitors various timers such as head settle and servo failure Performs self checkout diagnostics 3 2 Head disk assembly The head disk assembly HDA is assembled in a clean room environment and contains the disks and actuator assembly Air is constantly circulated and filtered when the drive is operational Venting of the ...

Page 24: ...Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification 10 ...

Page 25: ...the drive from the system interface The logical layout to Physical layout that is the actual Head and Sectors translation is done automatically in the drive The default setting can be obtained by issuing an IDENTIFY DEVICE command Table 1 Formatted capacity HDS725050KLXXXX Physical Layout Label capacity GB 500 Bytes per sector 512 Sectors per track 594 1242 Number of heads 10 Number of disks 5 Dat...

Page 26: ... users Table 2 Mechanical positioning performance Data transfer rates Mbps 817 Interface transfer rates Mb s 133 PATA 300 SATA Data buffer size1 KB 8192 PATA 16384 SATA Rotational speed RPM 7200 Number of buffer segments read up to 128 Number of buffer segments write up to 63 Recording density max Kbpi 720 Track density TPI 105 Areal density max Gbits in2 76 Number of data bands 30 Table 3 World W...

Page 27: ... are not allocated Data cylinder This cylinder contains the user data which can be sent and retrieved via read write commands and a spare area for reassigned data Spare cylinder The spare cylinder is used by Hitachi Global Storage Technologies manufacturing and includes data sent from a defect loca tion 4 4 Performance characteristics Drive performance is characterized by the following parameters ...

Page 28: ...mand overhead is defined as the time required from the time the command is written into the command register by a host to the assertion of DRQ for the first data byte of a READ command when the requested data is not in the buffer excluding Physical seek time and Latency The table below gives average command overhead Table 4 Command overhead Command type Drive is in quiescent state Time typical ms ...

Page 29: ...rrival problems The average seek time is mea sured as the weighted average of all possible seek combinations max Σ m10 n Tnin Tnout n 1 Weighted Average max 1 max where max Maximum seek length n Seek length 1 to max Tnin Inward measured seek time for an n track seek Tnout Outward measured seek time for an n track seek 4 4 2 2 Full stroke seek time without command overhead including settling Full s...

Page 30: ...ck seek is measured as the average of one 1 single track seek from every track in both directions inward and out ward 4 4 2 6 Average latency 4 4 3 Drive ready time Ready The condition in which the drive is able to perform a media access command for example read write immediately Power onThis includes the time required for the internal self diagnostics Note Max Power On to ready time is the maximu...

Page 31: ...ollowing formula Sustained Transfer Rate A B C D where A 512 number of data sectors per cylinder B number of Surfaces per cylinder 1 head switch time C cylinder change time D number of surfaces time for one revolution Instantaneous buffer host transfer rate Mbyte s defines the maximum data transfer rate on the AT Bus It also depends on the speed of the host The method of measurement is given in 4 ...

Page 32: ...d that a host system responds instantaneously and host data transfer is faster than sustained data rate 4 4 5 2 Random access The following table illustrates simple sequential access for three disk enclosure Table 12 Random Access performance The above table gives the time required to execute a total of 1000h read commands which access a single random LBA Typi cal and Max values are given by 105 a...

Page 33: ...ek Seek operation mode Write Write operation mode Read Read operation mode Unload Idle Spindle rotation at 7200 RPM with heads unloaded Idle Spindle motor and servo system are working normally Commands can be received and pro cessed immediately Standby Actuator is unloaded and spindle motor is stopped Commands can be received immediately Sleep Actuator is unloaded and spindle motor is stopped Only...

Page 34: ...Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification 20 ...

Page 35: ...BA to the physical locations is calculated by an internally maintained table Shipped format Data areas are optimally used No extra sector is wasted as a spare throughout user data areas All pushes generated by defects are absorbed by the spare tracks of the inner zone Table 15 Plist physical format Defects are skipped without any constraint such as track or cylinder boundary N N 1 N 2 N 3 defect d...

Page 36: ...Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification 22 ...

Page 37: ...and Deskstar E7K500 Hard Disk Drive Specification 23 6 0 Specification 6 1 Electrical Interface 6 1 1 Connector location Refer to the following illustration to see the location of the connectors PATA Model SATA Model ...

Page 38: ...4 0 using AMP pins part num ber 350078 4 strip part number 61173 4 loose piece or their equivalents Pin assignments are shown in the fig ure below 6 1 3 AT signal connector The PATA signal connector is a 40 pin connector PATA model The SATA signal connector is a 8 pin connector The power connector is a 15 pin connector SATA model 4 3 2 1 Pin Voltage 1 12 V 2 GND 3 GND 4 5V ...

Page 39: ...ion of the DMA burst Table 16 Signal definitions PIN SIGNAL I O Type PIN SIGNAL I O Type 01 RESET I TTL 02 GND 03 DD7 I O 3 state 04 DD08 I O 3 state 05 DD6 I O 3 state 06 DD09 I O 3 state 07 DD5 I O 3 state 08 DD10 I O 3 state 09 DD4 I O 3 state 10 DD11 I O 3 state 11 DD3 I O 3 state 12 DD12 I O 3 state 13 DD2 I O 3 state 14 DD13 I O 3 state 15 DD1 I O 3 state 16 DD14 I O 3 state 17 DD0 I O 3 sta...

Page 40: ... can be selected See Table 41 I O address map on page 43 RESET This line is used to reset the drive It shall be kept at a Low logic state during power up and kept High thereafter DIOW The rising edge of this signal holds data from the data bus to a register or data register of the drive DIOR When this signal is low it enables data from a register or data register of the drive onto the data bus The...

Page 41: ...conds to indicate that it is no longer busy and is able to provide status Following the receipt of a valid Execute Drive Diagnostics command device 1 shall negate PDIAG within 1 ms to indicate to device 0 that it is busy and has not yet passed its drive diagnostics If device 1 is present then device 0 shall wait up to 6 seconds from the receipt of a valid Execute Drive Diagnostics command for driv...

Page 42: ...Both the rising and falling edge of HSTROBE latch the data from DD 15 0 into the device The host may stop toggling HSTROBE to pause an Ultra DMA data out transfer STOP Ultra DMA This signal is used only for Ultra DMA data transfers between host and drive The STOP signal shall be asserted by the host prior to initiation of an Ultra DMA burst A STOP shall be negated by the host before data is transf...

Page 43: ... mate Gnd S2 A Differential signal A from Phy RX Input S3 A RX Input Signal S4 Gnd 2nd mate Gnd S5 B Differential signal B from Phy TX Output S6 B TX Output S7 Gnd 2nd mate Gnd Key and spacing separate signal and power segments P1 V33 3 3V power 3 3V P2 V33 3 3V power 3 3V P3 V33 3 3V power pre charge 2nd Mate 3 3V P4 Gnd 1st mate Gnd P5 Gnd 2nd mate Gnd P6 Gnd 2nd mate Gnd P7 V5 5V power pre char...

Page 44: ...ferential signals that are connected to the serial ATA cable The following standard shall be referenced about signal specifications Serial ATA High Speed Serialized AT Attachment Revision 1 0a 7 January 2003 6 4 2 Out of band signaling SATA model Table 19 The timing of COMRESET COMINT and COMWAKE Table 20 Parameter descriptions PARAMETER DESCRIPTION Nominal ns t1 ALINE primitives 106 7 t2 Spacing ...

Page 45: ...7K500 Hard Disk Drive Specification 31 6 5 Signal timings PATA model 6 5 1 Reset timings Table 21 System reset timing chart PARAMETER DESCRIPTION Min µs Max µs t10 RESET low width 25 t14 RESET high to not BUSY 31 t10 t14 RESET BUSY ...

Page 46: ...DRQ bit until set ting of the next DRQ bit PARAMETER DESCRIPTION MIN ns MAX ns t0 Cycle time 120 t1 Address valid to DIOR DIOW setup 25 t2 DIOR DIOW pulse width 70 t2i DIOR DIOW recovery time 25 t3 DIOW data setup 20 t4 DIOW data hold 10 t5 DIOR data setup 20 t6 DIOR data hold 5 t9 DIOR DIOW to address valid hold 10 tA IORDY setup width 35 tB IORDY pulse width 1250 IOCS16 t9 t0 t2 t2i t3 t4 t5 t8 ...

Page 47: ... from the end of negation of the DRQ bit until setting of the next DRQ bit is as follows In the event that a host reads the status register only before the sector or block transfer DRQ interval the DRQ interval 4 2 µs In the event that a host reads the status register after or both before and after the sector or block transfer the DRQ interval is 11 5 µs ...

Page 48: ... MAX ns t0 Cycle time 120 tD DIOR DIOW asserted pulse width 70 tE DIOR data access 50 tF DIOR data hold 5 tG DIOR DIOW data setup 20 tH DIOW data hold 10 tI DMACK to DIOR DIOW setup 0 tJ DIOR DIOW to DMACK hold 5 tKR tKW DIOR DIOW negated pulse width 25 tLR tLW DIOR DIOW to DMARQ delay 35 tM CS 1 0 valid to DIOR DIOW 25 tN CS 1 0 10 tZ DMACK to read data released 25 WRITE DATA READ DATA DMACK DMAR...

Page 49: ...20 70 20 55 20 55 20 50 20 50 tZIORDY Minimum time before driving IORDY 0 0 0 0 0 0 0 tFS First DSTROBE time 0 230 0 200 0 170 0 130 0 120 90 0 80 tCYC Cycle time 112 73 54 39 25 17 13 t2CYC Two cycle time 230 154 115 86 57 38 29 tAZ Maximum time allowed for out put drivers to release 10 10 10 10 10 10 10 tZAD Drivers to assert 0 0 0 0 0 0 0 tDS Data setup time at host 15 10 7 7 5 4 8 2 6 tDH Data...

Page 50: ...should be ready to receive two more data words after HDMARDY is negated Table 28 Ultra DMA cycle timings Host pausing Read PARAMETER DESCRIPTION all values in ns MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tSR DSTROBE to HDMARDY time 50 30 20 tRFS HDMARDY to final DSTROBE time 75 70 60 60 50 50 50 DSTROBE HDMARDY DMACK DMARQ tSR STOP tRF...

Page 51: ... 85 85 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 0 60 tAZ Maximum time allowed for output driv ers to release 10 10 10 10 10 10 10 tZAH Minimum delay time required for out put 20 20 20 20 20 20 20 tMLI Interlock time with minimum 20 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 5 tACK Hold time for DMACK 20 20 2...

Page 52: ...I Limited interlock time 0 150 0 150 0 150 0 100 0 75 0 60 0 60 tAZ Maximum time allowed for output driv ers to release 10 10 10 10 10 10 10 tZAH Maximum delay time required for out put 20 20 20 20 20 20 20 tMLI Interlock time with minimum 20 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 5 tACK Hold time for DMACK 20 20 20 20 20 20...

Page 53: ...ACK Setup time for DMACK 20 20 20 20 20 20 20 tENV Envelope time 20 70 20 70 20 70 20 55 20 50 20 50 20 50 tZIORDY Minimum time before driving IORDY 0 0 0 0 0 0 0 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 60 0 60 tCYC Cycle time 112 73 54 39 25 16 8 13 0 t2CYC Two cycle time 230 154 115 86 57 38 29 tDS Data setup time at device 15 10 7 7 5 4 2 6 tDH Data Hold time at device 5 5 5 ...

Page 54: ... it shall be ready to receive two more strobes after DDMARDY is negated Table 36 Ultra DMA cycle timing chart Device Pausing Write PARAMETER DESCRIPTION all values in ns MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tSR HSTROBE to DDMARDY time 50 30 20 tRFS DDMARDY to final HSTROBE time 75 70 60 60 60 50 50 HSTROBE DDMARDY DMACK DMARQ tSR ...

Page 55: ...inal HSTROBE time 75 70 60 60 60 50 50 tRP Ready to pause time 160 125 100 100 100 85 85 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 0 60 tMLI Interlocking time with minimum 20 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 5 tACK Hold time for DMACK negation 20 20 20 20 20 20 20 tIORDYZ Maximum time before releasi...

Page 56: ... MAX tSS Time from HSTROBE edge to asser tion of STOP 50 50 50 50 50 50 50 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 0 60 tMLI Interlock time with minimum 20 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 5 tACK Hold time for DMACK 20 20 20 20 20 20 20 tIORDYZ Maximum time before releasing IORDY 20 20 20 20 20 20...

Page 57: ...ample the host is not supposed to read status register contents before interrupt the value is invalid 6 9 1 Cabling The maximum cable length from the host system to the drive plus circuit pattern length in the host system shall not exceed 18 inches For higher data transfer application 8 3 MB s a modification in the system design is recommended to reduce cable noise and cross talk such as a shorter...

Page 58: ...Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification 44 ...

Page 59: ...Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification 45 7 0 Jumper Settings PATA model 7 1 Connector location 7 1 1 Jumper pin identification Jumper pins Pin A Pin B Pin I DERA001 prz ...

Page 60: ...n standby Within each of these four jumper settings the pin assignment selects Device 0 Device 1 Cable Selection or Device 1 Slave Present as shown in the following figures The Device 0 setting automatically recognizes device 1 if it is present The Device 1 Slave Present setting is for a slave device that does not comply with the ATA specification Note In conventional terminology Device 0 designat...

Page 61: ...ow shows the jumper positions used to select Device 0 Device 1 Cable Selection or Device1 Slave Present GND DS I G E C A H D B F RSV GND GND RSV CS SP GND RSV G I E C A H F D B DEVICE 0 Master G I E C A H F D B DEVICE 1 Slave G I E C A H F D B CABLE SEL G I E C A H F D B DEVICE 1 Slave Present G I E C A H F D B Shipping Default Condition CABLE SEL ...

Page 62: ...logical head default The figure below shows the jumper positions used to select Device 0 Device 1 Cable Selection or Device1 Slave Present setting 15 logical heads instead of default 16 logical head models Notes 1 To enable the CSEL mode Cable Selection mode the jumper block must be installed at E F In the CSEL mode the drive address is determined by AT interface signal 28 CSEL as follows When CSE...

Page 63: ... clip which clips the LBA to 66055248 The CHS is unchanged from the factory default of 16383 16 63 7 1 3 4 Power up in Standby The figure below shows the jumper positions used to select Device 0 Device 1 Cable Selection or Device 1 Slave Present to enable Power up in Standby Table 43 Jumper settings for Disabling Auto Spin G I E C A H F D B DEVICE 0 Master G I E C A H F D B DEVICE 1 Slave G I E C ...

Page 64: ...pin up is SET FEATURES subcommand 07h Refer to 12 28 Set Features 3 To enable the CSEL mode Cable Selection mode the jumper block must be installed at E F In the CSEL mode the drive address is determined by AT interface signal 28 CSEL as follows When CSEL is grounded or at a low level the drive address is 0 Device 0 When CSEL is open or at a high level the drive address is 1 Device 1 ...

Page 65: ...rature and humidity Operating conditions Temperature 5C to 55ºC See note below Relative humidity 8 to 90 non condensing Maximum wet bulb temperature 29 4ºC non condensing Maximum temperature gradient 15ºC hour Altitude 300 to 3 048 m Non operating conditions Temperature 40C to 65ºC Relative humidity 5 to 95 non condensing Maximum wet bulb temperature 35ºC non condensing Altitude 300 to 12 000 m 0 ...

Page 66: ...wer supply current typical Except for a peak of less than 100 ms duration 1 Random seeks at 40 duty cycle 2 Seek duty 30 W R duty 45 Idle duty 25 Table 46 Input voltage Input voltage supply During run and spin up Absolute max spike voltage1 Supply rise time 5 V 5 V 5 0 3 to 7 V 0 to 5 sec 12 V 12 V 10 8 0 3 to 15 V 0 to 5 sec Table 47 Power supply current of PATA model Power supply current of PATA...

Page 67: ...o electrical level difference at the four screws position and has less than 300 millivolts peak to peak level difference to the ground of the drive power connector Table 48 Power supply current of SATA model Power supply current of SATA model 5 Volts mA 12 Volts mA Total W values in milliamps RMS Pop Mean Std Dev Pop Mean Std Dev Idle average 500 12 590 12 9 6 Idle ripple peak to peak 330 40 630 2...

Page 68: ...d in the power requirement section 7 4 3 Start stop cycles The drive withstands a minimum of 50 000 start stop cycles in a 40 C environment and a minimum of 10 000 start stop cycles in extreme temperature or humidity within the operating range 7 4 4 Preventive maintenance None 7 4 5 Data reliability Probability of not recovering data is 1 in 1014 bits read ECC On The Fly correction 1 Symbol 8 bits...

Page 69: ...t uncovered in order to keep the air pressure inside of the disk enclosure equal to external air pressure The following table lists the dimensions of the drive Table 50 Physical dimensions and weight Height mm 25 4 0 4 Width mm 101 6 0 4 Length mm 146 0 0 6 Weight grams maximum 700 BR EAT HER HO LE D ia 2 0 0 1 19 7 0 4 38 9 0 4 101 6 0 4 146 0 6 25 4 0 4 LEFT FR O N T D O N O T B LO C K T H E B R...

Page 70: ...g hole locations and size of the drive are shown below All dimensions are in mm Figure 1 Mounting hole locations Thread 1 2 3 4 5 6 7 6 32 UNC 41 28 0 5 44 45 0 2 95 25 0 2 6 35 0 2 28 5 0 5 60 0 0 2 41 6 0 2 Side View 5 6 7 Bottom View 1 2 3 4 I F Connector 4X Max penetration 4 0 mm 6X Max penetration 4 5 mm ...

Page 71: ...Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification 57 7 5 3 Connector locations 3X 5 08 0 1 4 6 0 5 42 73 REF 13 43 REF 33 39 4 REF SATA model ...

Page 72: ...n using appropriate screws or equivalent mounting hardware The recommended mounting screw torque is 0 6 1 0 Nm 6 10 Kgf cm The recommended mounting screw depth is 4 mm maximum for bottom and 4 5 mm maximum for horizontal mounting Drive level vibration test and shock test are to be conducted with the drive mounted to the table using the bottom four screws 7 5 5 Heads unload and actuator lock The he...

Page 73: ...an square level is 0 67 G for horizontal vibration and 0 56 G for vertical Table 51 Random vibration PSD The overall RMS root mean square level is 0 67 G for horizontal vibration and 0 56 G for vertical 7 6 1 2 Swept sine vibration The drive will meet the criteria shown below while operating in the specified conditions No errors occur with 0 5 G 0 to peak 5 to 300 to 5 Hz sine wave 0 5 oct min swe...

Page 74: ...nd direction for total of 60 There must be a delay between shock pulses long enough to allow the drive to complete all necessary error recovery procedures No error occurs with a 10 G half sine shock pulse of 11 ms duration in all models No data loss occurs with a 30 G half sine shock pulse of 4 ms duration in all models No data loss occurs with a 55 G half sine shock pulse of 2 ms duration in all ...

Page 75: ...alf sine pulse The figure below shows the maximum acceleration level and duration 7 6 5 Nonoperating rotational shock All shock inputs shall be applied around the actuator pivot axis Table 55 Rotational shock Table 54 Sinusoidal shock wave Acceleration level G Duration ms 225 2 150 11 Duration Rad sec2 1 ms 30 000 2 ms 20 000 ...

Page 76: ...ith the following formula Dwell time 0 5 x 60 RPM Seek rate 0 4 average seek time dwell time 7 8 Identification labels The following labels are affixed to every drive A label containing the Hitachi logo the Hitachi Global Storage Technologies part number and the statement Made by Hitachi Global Storage Technologies Inc or Hitachi Global Storage Technol ogies approved equivalent A label containing ...

Page 77: ...g of V 2 7 9 4 Safe handling The product is conditioned for safe handling in regards to sharp edges and corners 7 9 5 Environment The product does not contain any known or suspected carcinogens Environmental controls meet or exceed all applicable government regulations in the country of origin Safe chemi cal usage and manufacturing control are used to protect the environment An environmental impac...

Page 78: ...k Marking for Hitachi Global Storage Technologies 7 10 1 CE mark The product is declared to be in conformity with requirements of the following EC directives under the sole responsibility of Hitachi Global Storage Technologies Japan Ltd Council Directive 89 336 EEC on the approximation of laws of the Member States relating to electromagnetic compatibility 7 10 2 C TICK mark The product complies wi...

Page 79: ... 23 December 2003 with certain limitations described in 2 0 Deviations From Standard 8 2 Terminology 8 3 Deviations from standard The device conforms to the referenced specifications with the following deviations Check Power Mode Check Power Mode command returns FFh to Sector Count Register when the device is in Idle mode This command does not support 80h as the return value Hard Reset Hard reset ...

Page 80: ...Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification 66 ...

Page 81: ...l and to post alternate status Addresses Functions CS0 CS1 DA2 DA1 DA0 READ DIOR WRITE DIOW N N x x x Data bus high impedance Not used Control block registers N A 0 x x Data bus high impedance Not used N A 1 0 x Data bus high impedance Not used N A 1 1 0 Alternate Status Device Control N A 1 1 1 Device Address Not used Command block registers A N 0 0 0 Data Data A N 0 0 1 Error Register Features A...

Page 82: ... access At the end of the com mand this register is updated to reflect the current cylinder number In LBA Mode this register contains Bits 16 23 At the end of the command this register is updated to reflect the current LBA Bits 16 23 The cylinder number may be from zero to the number of cylinders minus one When 48 bit addressing commands are used the most recently written content contains LBA Bits...

Page 83: ... only when DRQ 1 is in the Status Register 9 7 Device Control Register Table 60 Device Control Register 7 6 5 4 3 2 1 0 HOB 1 SRST IEN 0 Bit Definitions HOB HOB high order byte is defined by the 48 bit Address feature set A write to any Command Register shall clear the HOB bit to zero SRST Software Reset The device is held at reset when RST 1 Setting RST 0 again enables the device To ensure that t...

Page 84: ...is the least significant DS1 Drive Select 1 The Drive Select bit for device 1 is active low DS1 0 when device 1 slave is selected and active DS0 Drive Select 0 The Drive Select bit for device 0 is active low DS0 0 when device 0 master is selected and active 7 6 5 4 3 2 1 0 1 L 1 DRV HS3 HS2 HS1 HS0 L Binary encoded address mode select When L 0 addressing is by CHS mode When L 1 addressing is by LB...

Page 85: ...g or 65 536 sectors in 48 bit addressing is specified If the register is zero at command completion the command was successful If it is not successfully completed the register contains the number of sectors which need to be transferred in order to complete the request The contents of the register are defined otherwise on some commands These definitions are given in the command descriptions 7 6 5 4...

Page 86: ... the registers The host should not read or write any registers when BSY 1 If the host reads any register when BSY 1 the contents of the Status Register will be returned DRDY RDY Device Ready RDY 1 indicates that the device is capable of responding to a command RDY will be set to zero during power on until the device is ready to accept a command If the device detects an error while processing a com...

Page 87: ...may not see it set to 1 even if the host is continuously reading the Status Register Therefore the host should not attempt to use IDX for timing purposes ERR Error ERR 1 indicates that an error occurred during execution of the previous command The Error Register should be read to determine the error type The device sets bit ERR 0 when the next command is received from the host ...

Page 88: ...Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification 74 ...

Page 89: ...5 Reset response table POR hard reset soft reset Aborting Host interface O O Aborting Device operation 1 1 Initialization of hardware O X X Internal diagnostic O X X Spinning spindle O X X Initialization of registers 2 O O O DASP handshake O O X PDIAG handshake O O O Reverting programmed parameters to default Number of CHS set by Initialize Device Parameters Multiple mode Write Cache Read look ahe...

Page 90: ...ower on hard reset or the Execute Device Diagnostic command is shown in the figure below Table 66 Default Register Values Register Default Value Error Diagnostic Code Sector Count 01h Sector Number 01h Cylinder Low 00h Cylinder High 00h Device Head A0h Status 50h Alternate Status 50h Table 67 Diagnostic codes Code Description 01h No error detected 02h Formatter device error 03h Sector buffer error...

Page 91: ...ands Device 0 may assert DASP to indicate device activity Hard Reset Soft Reset If Device 1 is present Device 0 shall read PDIAG to determine when it is valid to clear the BSY bit and whether Device 1 has reset without any errors otherwise Device 0 shall simply reset and clear the BSY bit DASP is asserted by Device 0 and Device 1 if it is present in order to indicate device active Execute Device D...

Page 92: ...rs are numbered from 0 to the maximum value allowed by the current CHS translation mode but cannot exceed 65535 0FFFFh When the host selects a CHS translation mode using the INITIALIZE DEVICE PARAMETERS command the host requests the number of sectors per logical track and the number of heads per logical cylinder The device then computes the number of logical cylinders available in requested mode T...

Page 93: ... is disabled Sleep Mode The lowest power consumption when the device is powered on occurs in Sleep Mode When in Sleep Mode the device requires a reset to be activated Standby Mode The device interface is capable of accepting commands but since the media may not be immediately accessible there is a delay while waiting for the spindle to reach operating speed Idle Mode In Idle Mode the device is cap...

Page 94: ...ects the physical interface as defined in the following table Ready RDY is not a power condition A device may post ready at the interface even though the media may not be accessible Table 69 Power conditions Mode BSY RDY Interface active Media Active x x Yes Active Idle o 1 Yes Active Standby o 1 Yes Inactive Sleep x x No Inactive ...

Page 95: ...ndition existing Accordingly lower attribute values indicate that the analysis algorithms being used by the device are predicting a higher probability of a degrading or faulty condition 10 6 3 Attribute thresholds Each attribute value has a corresponding attribute threshold limit which is used for direct comparison to the attribute value to indicate the existence of a degrading or faulty condition...

Page 96: ...s a firmware modification all error log data is discarded and the device error count for the life of the device is reset to zero 10 6 8 Self test The device provides the self test features which are initiated by SMART Execute Off line Immediate command The self test checks the fault of the device reports the test status in Device Attributes Data and stores the test result in the SMART self test lo...

Page 97: ...er power on Media access commands are enabled by either a Security Unlock command or a Security Erase Unit command Device Unlocked Mode The device enables all commands If a password is not set this mode is entered after power on otherwise it is entered by a Security Unlock or a Security Erase Unit command Device Frozen Mode The device enables all commands except those which can update the device l...

Page 98: ...er Password is set the device will automatically enter lock mode the next time the device is powered on Master Password When the Master Password is set the device does NOT enable the Device Lock Function and the device CANNOT be locked with the Master Password but the Master Password can be used for unlocking the locked device Identify Device Information word 92 contains the value of the Master Pa...

Page 99: ...efer to the commands in Figure 10 8 5 Command table on page 90 POR Device Locked mode Unlock CMD Command 1 Command 1 Password Erase Unit Password Match Reject Complete Complete Erase Unit Lock function Disable Normal operation All commands are available Freeze Lock command Enter Device Frozen mode Normal Operation expect Set Password Disable Password Erase Unit Unlock commands Enter Device Unlock ...

Page 100: ...SECURITY UNLOCK command has an attempt limit the purpose of which is to prevent attempts to unlock the drive with various passwords numerous times The device counts the password mismatch If the password does not match the device counts it without distinguishing the Master password and the User password If the count reaches 5 EXPIRE bit bit 4 of Word 128 in Identify Device information is set and th...

Page 101: ...T Enable Operations o o o Initialize Device Parameters o o o S M A R T Execute Off line Immediate o o o NOP S M A R T Read Attribute Values o o o Read Buffer o o o S M A R T Read Attribute Thresholds o o o Read DMA x o o S M A R T Return Status o o o Read DMA Ext x o o S M A R T Save Attribute Values o o o Read DMA Queued x o o S M A R T Read Log Sector o o o Read DMA Queued Ext x o o S M A R T Wr...

Page 102: ...he sequence is as follows i Issue a Read Native Max ADDRESS command to get the real device maximum LBA Returned value shows that native device maximum LBA is 12 692 735 C1ACFFh regardless of the current setting ii Make the entire device accessible including the protected area by setting the device maximum LBA to 12 692 735 C1ACFFh via Set Max ADDRESS command The option may be either nonvolatile or...

Page 103: ...assword Set Max Lock Set Max Freeze Lock Set Max Unlock The Set Max Set Password command allows the host to define the password to be used during the current power on cycle The password does not persist over a power cycle but does persist over a hardware or software reset This password is not related to the password used for the Security Mode Feature set When the password is set the device is in t...

Page 104: ... command from the host however the actual seek operation for the next seek command starts immediately after the actual seek operation for the first seek command is completed In other words the execution of two seek commands overlaps excluding the time required for the actual seek operation With this overlap the total elapsed time for a number of seek commands results in the total accumulated time ...

Page 105: ...writing the data onto the disk While writing data after completed acknowledgment of a write command soft reset or hard reset does not affect its operation However power off terminates the writing operation immediately and unwritten data is lost The Soft reset Standby Immediate command and Flush Cache commands during the writing of the cached data are executed after the completion of writing to med...

Page 106: ...bed below Nonrecovered write errors When a write operation cannot be completed after the Error Recovery Procedure ERP is fully carried out the sector s are reallocated to the spare location An error is reported to the host system only when the write cache is disabled and the auto reallocation has failed If the Write Cache function is ENABLED when the number of available spare sectors reaches 0 sec...

Page 107: ...re set is enabled or disabled the device needs the Set Features command to spin up into active state 10 13 Advanced Power Management feature set APM This feature allows the host to select an advanced power management level The advanced power management level is a scale from the lowest power consumption setting of 01h to the maximum performance level of FEh Device performance may increase with incr...

Page 108: ...Acoustic Management and the Standby timer setting are independent functions The device shall enter Standby mode if any of the following are true 1 The Standby timer has been set and times out 2 Automatic Power Management is enabled and the associated algorithm indicates that the Standby mode should be entered to save power 3 Automatic Acoustic Management is enabled and the associated algorithm ind...

Page 109: ...ering offset mode the capacity of the drive returned in the Identify Device data is the size of the former protected area A subsequent Set Max Address command with the address returned by Read Max Address command allows access to the entire drive Addresses wrap so the entire drive remains addressable If a non volatile protected area has not been established before the device receives a Set Feature...

Page 110: ...e Address Offset Feature Identify Device data word 86 bit 7 indicates the device is in Address Offset mode 10 15 3 Exceptions in Address Offset Mode Any commands which access sectors across the original native maximum LBA are rejected with error even if the access protection is removed by a Set Max Address command Read Look Ahead operation is not carried out even if it is enabled by the Set Featur...

Page 111: ...ntrol register to one and then reading the desired register If HOB in the Device Control register is cleared to zero the host reads the most recently written content when the register is read A write to any Command Block register shall cause the device to clear the HOB bit to zero in the Device Control register The most recently written content always gets written by a register write regardless of...

Page 112: ...operation is device vendor specific The streaming commands may access any user LBA on a device These commands may be interspersed with non streaming commands but there may be an impact on performance due to the unknown time required to complete the non streaming commands The streaming commands should be issued using a specified minimum number of sectors transferred per command as specified in word...

Page 113: ...ain undefined data A future read of this area may not report an error even though the data is erroneous 10 17 7 Handle Streaming Error bit The Handle Streaming Error bit specifies to the device that this command starts at the LBA of a recently reported error section so the device may attempt to continue its corresponding error recovery sequence where it left off earlier This mechanism allows the h...

Page 114: ...Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification 100 ...

Page 115: ...blem such as a device that is no longer responding Interrupts are cleared when the host reads the Status Register issues a reset or writes to the Command Register 11 1 PIO Data In commands The following are Data In commands Device Configuration Identity Identify Device Read Buffer Read Log Ext Read Long Read Multiple Read Multiple Ext Read Sector s Read Sector s Ext Read Stream PIO S M A R T Read ...

Page 116: ... will abort the command by setting BSY 0 ERR 1 ABT 1 and interrupting the host If an error occurs the device will set BSY 0 ERR 1 and DRQ 1 The device will then store the error status in the Error Register and interrupt the host The registers will contain the location of the sector in error The error location will be reported using CHS mode or LBA mode The mode is decided by the mode select bit bi...

Page 117: ...s ready to receive a sector b The host writes one sector of data including ECC bytes via the Data Register c The device sets BSY 1 after it has received the sector d After processing the sector of data the device sets BSY 0 and interrupts the host e In response to the interrupt the host reads the Status Register f The device clears the interrupt in response to the Status Register being read The Wr...

Page 118: ...Disable Attribute Autosave S M A R T Enable Disable Automatic Off Line S M A R T Enable Operations S M A R T Execute Off line Data Collection S M A R T Return Status S M A R T Save Attribute Values Standby Standby Immediate Execution of these commands involves no data transfer a The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head Registers b ...

Page 119: ...isector commands The host resets the DMA channel prior to reading status from the device The DMA protocol allows high performance multitasking operating systems to eliminate processor overhead asso ciated with PIO transfers Host write any required parameters to the Features Sector Count Sector Number Cylinder and Device Head registers The host initializes the Slave DMA channel The host writes any ...

Page 120: ...Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification 106 ...

Page 121: ... 1 1 1 1 Identify Device EC 1 1 1 0 1 1 0 0 3 Idle E3 1 1 1 0 0 0 1 1 3 Idle 97 1 0 0 1 0 1 1 1 3 Idle Immediate E1 1 1 1 0 0 0 0 1 3 Idle Immediate 95 1 0 0 1 0 1 0 1 3 Initialize Device Parameters 91 1 0 0 1 0 0 0 1 3 NOP 00 0 0 0 0 0 0 0 0 1 Read Buffer E4 1 1 1 0 0 1 0 0 4 Read DMA C8 1 1 0 0 1 0 0 0 4 Read DMA C9 1 1 0 0 1 0 0 1 4 Read DMA Ext 25 0 0 1 0 0 1 0 1 1 Read Long 22 0 0 1 0 0 0 1 0...

Page 122: ... 0 0 0 0 1 S M A R T Read Attribute Thresholds B0 1 0 1 1 0 0 0 0 3 S M A R T Return Status B0 1 0 1 1 0 0 0 0 3 S M A R T Save Attribute Values B0 1 0 1 1 0 0 0 0 2 S M A R T Write Log Sector B0 1 0 1 1 0 0 0 0 3 Standby E2 1 1 1 0 0 0 1 0 3 Standby 96 1 0 0 1 0 1 1 0 3 Standby Immediate E0 1 1 1 0 0 0 0 0 3 Standby Immediate 94 1 0 0 1 0 1 0 0 2 Write Buffer E8 1 1 1 0 1 0 0 0 4 Write DMA CA 1 1...

Page 123: ...M A R T Enable Disable Automatic Off line B0 DB Set Features Enable Write Cache EF 02 Set Transfer mode EF 03 Enable Advanced Power Management EF 05 Enable Power up in Standby Feature Set EF 06 Power up in Standby Feature Set Device Spin up EF 07 Enable Address Offset mode EF 09 Enable Automatic Acoustic Management EF 42 52 bytes of ECC apply on Read Write Long EF 44 Disable read look ahead featur...

Page 124: ... Original meaning is already obsolete there is no difference between 0 and 1 Using 0 is recommended for future compatibility B Option Bit This indicates that the Option Bit of the Sector Count Register be specified This bit is used by Set Max ADDRESS command V Valid This indicates that the bit is part of an output parameter and should be specified x This indicates that the hex character is not use...

Page 125: ...indle motor is at speed and the device is not in Standby or Sleep mode Other wise the Sector Count Register is set to 0 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count V V V V V V V V Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head...

Page 126: ...ata High Data High Feature Current V V V V V Error See Below Previous V V V V V V V V Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V V HOB 1 Sector Number Current Sector Number HOB 0 Previous HOB 1 Cylinder Low Current Cylinder Low HOB 0 Previous HOB 1 Cylinder High Current Cylinder High HOB 0 V V V V V V V V Previous HOB 1 Device Head 1 1 1 D Device Head Command 0 ...

Page 127: ...he Features register Identify Device words 99 98 micriseconds This time shall be used by the device when a streaming command with the same stream ID and a CCTL of zero is issued The time is measured from the write of the command register to the final INTRQ for command completion Sector Count Current Allocation Unit Size In Sectors 7 0 Sector Count Previous Allocation Unit Size In Sectors 15 8 ...

Page 128: ...on Overlay settings After successful execution of a DEVICE CONFIGURATION FREEZE LOCK com mand all DEVICE CONFIGURATION SET DEVICE CONFIGURATION FREEZE LOCK DEVICE CONFIGURATION IDENTIFY and DEVICE CONFIGURATION RESTORE commands are aborted by the device The DEVICE CONFIGURATION FREEZE LOCK condition shall be cleared by a power down The DEVICE CONFIGURATION FREEZE LOCK condition shall not be cleare...

Page 129: ...that is not set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command no action is taken for that bit The format of the overlay transmitted by the device is described in the table in Table 80 Device Configuration Overlay Data structure on page 116 The restrictions on changing these bits is described in the text following that table If any of the bit modification restrictions describ...

Page 130: ...des supported 15 7 Reserved 6 1 Ultra DMA mode 6 and below are supported 5 1 Ultra DMA mode 5 and below are supported 4 1 Ultra DMA mode 4 and below are supported 3 1 Ultra DMA mode 3 and below are supported 2 1 Ultra DMA mode 2 and below are supported 1 1 Ultra DMA mode 1 and below are supported 0 1 Ultra DMA mode 0 is supported 3 6 Maximum LBA address 7 Command set feature set supported 15 13 Re...

Page 131: ...umber Invalid bit location bits 7 0 Sector count error reason code description 01h DCO feature is frozen 02h Device is now Security Locked mode 03h Device s feature is already modified with DCO 04h User attempt to disable any feature enabled 05h Device is now SET MAX Locked or Frozen mode 06h Protected area is now established 07h DCO is not supported 08h Subcommand code is invalid FFh other reason...

Page 132: ... reload new microcode This error is reported only when the reload of microcode is requested In reloading new microcode the device does not preserve its state and settings but reset them just like the device is executing a power on For instance the device does DASP handshake in reloading new microcode Thus the device does not recognize the slave device even though it exists Also when the spin up of...

Page 133: ...Instead the register contains a diagnostic code See Table 66 Default Register Values on page 76 for the definition Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 Device Head Comm...

Page 134: ...media Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 0 1 1 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC...

Page 135: ...7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current Sector Count HOB 0 Previous HOB 1 Sector Number Current Sector Number HOB 0 Previous HOB 1 Cylinder Low Current Cylinder Low HOB 0 Previous HOB 1 Cylinder High Current Cylinder High HOB 0 Previous HOB 1 Device Head D Device Head Command 1 1 1 0 1 0 1 0 Status...

Page 136: ...es that LBA address bits 8 15 Low and bits 16 23 High are to be formatted L 1 H This indicates the head number of the track to be formatted L 0 In LBA mode this reg ister specifies that LBA address bits 24 27 are to be formatted L 1 Input parameters from the device Sector Number In LBA mode this register specifies the current LBA address bits as 0 7 L 1 Cylinder High Low In LBA mode this register ...

Page 137: ...tialized The Security Erase Prepare F3h command should be completed immediately prior to the Format Unit command If the device receives a Format Unit command without a prior Security Erase Prepare command the device aborts the Format Unit command All values in Feature register are reserved and any values other than 11h should not be put into Feature register This command does not request a data tr...

Page 138: ...in Table 89 beginning on page 125 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 1 1 0 0 Status see below Error Register Status Register 7 6 5 4 3 2...

Page 139: ...ature for spin up after power up Identify Device is incomplete 03 00XXH Number of heads in default translate mode 04 0 Reserved 05 0 Reserved 06 003FH Number of sectors per track in default translate mode 07 0000H Number of bytes in sector gap 08 0000H Number of bytes in sync field 09 0000H Reserved 10 19 XXXX Serial number in ASCII 0 not specified 20 0003H Controller type 0003 dual ported multipl...

Page 140: ...0H PIO data transfer cycle timing mode 52 0200H DMA data transfer cycle timing mode Refer to Word 62 and 63 53 0007H Validity flag of the word 15 3 0 Reserved 2 1 1 Word 88 is Valid 1 1 1 Word 64 70 are Valid 0 1 1 Word 54 58 are Valid 54 XXXXH Number of current cylinders 55 XXXXH Number of current heads 56 XXXXH Number of current sectors per track 57 58 XXXXH Current capacity in sectors Word 57 s...

Page 141: ...n nanoseconds 240 ns 8 3 MB s 68 0078H Minimum PIO Transfer Cycle Time With IORDY Flow Control 15 0 78h Cycle time in nanoseconds 120 ns 16 6 MB s 69 74 0000H Reserved 75 00XXH Queue depth 15 5 Reserved 4 0 Maximum queue depth 76 79 0000H Reserved 80 00FCH Major version number 15 0 Fch ATA 2 ATA 3 ATA ATAPI 4 ATA ATAPI 5 ATA ATAPI 7 81 001AH Minor version number 15 0 1Ah ATA ATAPI 7 T13 1532D revi...

Page 142: ...pported 4 0 Removable Media Status Notification feature 3 1 Advanced Power Management Feature Set 2 0 CFA feature set 1 1 READ WRITE DMA QUEUED 0 1 DOWNLOAD MICROCODE command 84 4733H Command set feature supported extension 15 14 01 Word 84 is valid 13 11 0 Reserved 10 1 URG bit supported for WRITE STREAM DMA and WRITE STREAM PIO 9 1 URG bit supported for READ STREAM DMA and READ STREAM PIO 8 1 Wo...

Page 143: ...NOP command 13 READ BUFFER command 12 WRITE BUFFER command 11 Reserved 10 Host Protected Area Feature Set 9 DEVICE RESET command 8 SERVICE interrupt 7 RELEASE interrupt 6 LOOK AHEAD 5 WRITE CACHE 4 PACKET Command Feature Set 3 Power Management Feature Set 2 Removable Feature Set 1 Security Feature Set 0 SMART Feature Set ...

Page 144: ... Removable Media Status Notification feature 3 Advanced Power Management Feature Set 2 CFA feature set 1 READ WRITE DMA QUEUED 0 DOWNLOAD MICROCODE command 87 4723H or 4733H Command set feature enabled 15 14 01 Word 87 is valid 13 11 0 Reserved 10 1 URG bit supported for WRITE STREAM DMA and WRITE STREAM PIO 9 1 URG bit supported for READ STREAM DMA and READ STREAM PIO 8 1 World wide name supporte...

Page 145: ... 1 Active 0 Not Active 9 Mode 1 1 Active 0 Not Active 8 Mode 0 1 Active 0 Not Active 7 0 7F Ultra DMA transfer mode supported 7 Reserved 0 6 Mode 6 1 Support 5 Mode 5 1 Support 4 Mode 4 1 Support 3 Mode 3 1 Support 2 Mode 2 1 Support 1 Mode 1 1 Support 0 Mode 0 1 Support 89 XXXXH Time required for Security Erase Unit completion Time value x 2 minutes 90 0000H Time required for Enhanced Security Er...

Page 146: ...1 Other method 0 Shall be set to one if Device 0 94 XXXXH Current Advanced Acoustic Management value 15 8 Vendor s Recommended Acoustic Management level 7 0 Current Acoustic Management level 95 xxxxH Stream Minimum Request Size Number of sectors that provides optimum performance in streaming environment This number shall be a power of two with a minimum of eight sectors 4096 bytes The starting LBA...

Page 147: ...4 xxxxH Streaming Transfer Time PIO The worst case sustainable transfer time per sector for the device is calculated as follows Streaming Transfer Time word 104 words 99 98 65536 If the Streaming Feature set is not supported by the device the content of word 104 shall be zero 105 106 0000H Reserved 107 58C5H Inter seek delay for ISO 779 acoustic testing in microseconds 108 111 xxxxH World wide nam...

Page 148: ...rameters that are vendor specific Word Content Description 129 xxxxH Current Set Feature Option Bit assignments 15 4 Reserve 3 Auto reassign 1 Enabled 2 Reverting 1 Enabled 1 Read Look ahead 1 Enabled 0 Write Cache 1 Enabled 130 159 xxxxH Reserved 160 254 0000H Reserved 255 xxA5H 15 8 Checksum This value is the two s complement of the sum of all bytes in byte 0 through 510 7 0 Signature ...

Page 149: ... shown below When the automatic power down sequence is enabled the drive will enter Standby mode automatically if the time out interval expires with no drive access from the host The time out interval will be reinitialized if there is a drive access before the time out interval expires Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Da...

Page 150: ...to the host commands immediately The Idle Immediate command will not affect the auto power down time out parameter Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Co...

Page 151: ... Zero 0 means that there are no sectors rather than 256 sectors per track H This indicates the number of heads minus 1 per cylinder The minimum is 0 and the maxi mum is 15 The following condition needs to be met to avoid invalid number of cylinders beyond FFFFh Total number of user addressable sectors sector count x H 1 FFFFh The total number of user addressable sectors is described in Identify De...

Page 152: ... The contents of the sector may be different if any reads or writes have occurred since the Write Buffer command was issued Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Devic...

Page 153: ... address bits 0 7 L 1 Cylinder High Low This indicates the cylinder number of the first sector to be transferred L 0 In LBA mode this register specifies the transfer of LBA address bits 8 15 Low and 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register specifies that LBA bits 24 27 is to be transferred L 1 R This indicates the retry bit...

Page 154: ... this register contains the current LBA bits 0 7 L 1 Cylinder High Low This indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 155: ...If 0000h in the Sector Count register is specified then 65 536 sectors will be transferred Sector Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Pre...

Page 156: ...he first unrecoverable error Sector Number HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unre...

Page 157: ...e below Cylinder Low Current The first sector of the log to be read low order bits 7 0 Cylinder Low Previous The first sector of the log to be read high order bits 15 8 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sect...

Page 158: ...ature set associated with the log specified in the Sector Number register is not supported or enabled or if the values in the Sector Count Sector Number or Cylinder Low registers are invalid the device shall return com mand aborted Log Address Content Feature set Type 00h Log directory N A Read Only 03h Extended Comprehensive SMART error log SMART error logging Ready Only 06h SMART self test log S...

Page 159: ...g at log address 01h 7 0 1 02h Number of sectors in the log at log address 01h 15 8 1 03h Number of sectors in the log at log address 01h 7 0 1 04h Number of sectors in the log at log address 01h 15 8 1 05h Number of sectors in the log at log address 20h 7 0 1 40h Number of sectors in the log at log address 20h 15 8 1 41h Number of sectors in the log at log address 21h 7 0 1 42h Number of sectors ...

Page 160: ...st four errors reported by the device These error log data structure entries are viewed as a circular buffer The fifth error shall create an error log structure that replaces the first error log data structure The next error after that shall create an error log data structure that replaces the second error log structure etc Unused error log data structures shall be filled with zeros 12 17 2 3 1 Da...

Page 161: ... Sector number register 7 0 1 05h Sector number register 15 8 1 06h Cylinder Low register 7 0 1 07h Cylinder Low register 15 8 1 08h Cylinder High register 7 0 1 09h Cylinder High register 15 8 1 0Ah Device Head register 1 0Bh Command register 1 0Ch Reserved 1 0Dh Timestamp milliseconds from Power on 4 0Eh 18 Description Bytes Offset Reserved 1 00h Error register 7 0 1 01h Sector count register 7 ...

Page 162: ...logged 12 17 3 Extended Self test log sector The figure below defines the format of each of the sectors that comprise the Extended SMART self test log The Extended SMART self test log sector shall support 48 bit and 28 bit addressing All 28 bit entries contained in the SMART self test log defined in shall also be included in the Extended SMART self test log with all 48 bit entries These descriptor...

Page 163: ...r count may be greater than 31 but only the most recent 31 errors are represented by entries in the log If the Read Stream Error Count reaches the maximum value that can be represented after the next error is detected the Read Stream Error Count shall remain at the maximum value After successful completion of a Read Log Ext command with the LBA Low Register set to 22h the Read Stream Error Log sha...

Page 164: ...s the format of the Write Stream Error log Entries are placed into the Write Stream Error log only when the SE bit is set to one in the Status Register The 512 bytes returned shall contain a maximum of 31 error entries The Write Stream Error Count shall contain the total number of Write Stream Errors detected since the last successful completion of the Read Log Ext command with LBA Low register se...

Page 165: ... the LBA Low register is 20h This data set is referred to as the Streaming Performance Parameters log the length of which in sectors is statically indicated in Read Log Ext log address 00h Log Directory The host should base its calculations on the larger of its Typical Host Interface Sector Time and the device reported Sector Time values and on the sum of the device reported Access Time values and...

Page 166: ...reference location LBA 7 0 LBA 47 40 n n 5 Identify Device words 99 98 65536 time units per sector at the reference location n 6 n 7 Description Bytes LBA of start of region LBA 7 0 LBA 47 40 n n 5 Position number in the range 0 32767 n 6 n 7 Description Bytes Difference in position from last stream access to new stream access n n 1 Time that may be required to begin access at new stream access po...

Page 167: ... The Sector Count must be set to one Sector Number This indicates the sector number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 0 7 L 1 Cylinder High Low This indicates the cylinder number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In...

Page 168: ...his indicates the cylinder number of the transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 The device internally uses 52 bytes of ECC data on all data written or read from the disk The 4 byte mode of oper ation is provided via...

Page 169: ...his register contains LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 24 27 L 1 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred This number is zero unless an unrecoverable error occurs Sector Number This indicates the sector number of the tr...

Page 170: ...er High Low This indicates the cylinder number of the transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 ...

Page 171: ... Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V ...

Page 172: ...tor Number HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 173: ...contains the native max LBA bits 8 15 Low and bits 16 23 High L 1 In CHS mode this register contains the native max cylinder number L 0 H In LBA mode this register contains the native max LBA bits 24 27 L 1 In CHS mode this register contains the native maximum head number L 0 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Fe...

Page 174: ... Native max address Cylinder High HOB 1 LBA 47 40 of the address of the Native max address Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current Sector Count HOB 0 Previous HOB 1 Sector Number Current Sector Number HOB 0 V V V V V V V V Previo...

Page 175: ...1 H This is the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This is the retry bit but this bit is ignored Input parameters from the device Sector Count This is the number of requested sectors not transferred This will be zero unless an unre coverable error occurs Sector Number This is the sector number of the last transferred se...

Page 176: ... Low This is the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This is the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 177: ...31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V ...

Page 178: ...tor Number HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 179: ...the RC bit is set to one and the Command Completion Time Limit expires the device shall stop execution of the command and pro vide ending status with BSY bit cleared to zero the SE bit set to one the ERR bit cleared to zero and report the fact that the Command Completion Time Limit expired by setting the CCTO bit in the error log to one In all cases the device shall attempt to transfer the amount ...

Page 180: ...one if the next read stream command with the same Stream ID may not be sequential in LBA space HSE bit4 HSE Handle Stream Error specifies that this command starts at the LBA of the last reported error for this stream so the device may attempt to continue its cor responding error recovery sequence where it left off earlier Stream ID bit 0 2 Stream ID specifies the stream to be read The device shall...

Page 181: ...tream Error shall be set to one if an error has occurred during the execution of the command and the RC bit is set to one In this case the LBA returned in the Sector Number registers shall be the address of the first sector in error and the Sector Count registers shall contain the number of consecutive sectors that may contain errors If the RC bit is set to one when the command is issued and ICRC ...

Page 182: ...o one and the Command Completion Time Limit expires the device shall stop execution of the command and pro vide ending status with BSY bit cleared to zero the SE bit set to one the ERR bit cleared to zero and report the fact that the Command Completion Time Limit expired by setting the CCTO bit in the error log to one In all cases the device shall attempt to transfer the amount of data requested w...

Page 183: ...xt read stream command with the same Stream ID may not be sequential in LBA space HSE bit4 HSE Handle Stream Error specifies that this command starts at the LBA of the last reported error for this stream so the device may attempt to continue its corresponding error recovery sequence where it left off earlier Stream ID bit 0 2 Stream ID specifies the stream to be read The device shall operate accor...

Page 184: ...if an error has occurred during the execution of the command and the RC bit is set to one In this case the LBA returned in the Sector Number registers shall be the address of the first sector in error and the Sector Count registers shall contain the number of consecutive sectors that may contain errors If the RC bit is set to one when the command is issued and a UNC IDNF ABRT or CCTO error occurs ...

Page 185: ...and bits 16 23 High L 1 H This is the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This is the retry bit this bit is ignored Input parameters from the device Sector Count This is the number of requested sectors not verified This number will be zero unless an unrecoverable error occurs Sector Number This is the sector number of th...

Page 186: ... Low This is the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This is the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 187: ...0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Coun...

Page 188: ...tor Number HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 189: ...the Error Register Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 0 0 0 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CR...

Page 190: ...for Security Disable Password command The device will compare the password sent from this host with that specified in the control word Identifier Zero indicates that the device should check the supplied password against the user pass word stored internally One indicates that the device should check the given password against the master password stored internally Command Block Output Registers Comm...

Page 191: ...s com mand is to prevent accidental erasure of the device This command does not request the transfer of data Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command ...

Page 192: ...isables the security mode feature device lock func tion After the completion of this command all the user data will be initialized to zero with a write operation At this time the data write is not verified with a read operation to determine if the data sector is initialized correctly At this time the defective sector information and the reassigned sector information for the device are not updated ...

Page 193: ... command disables the security mode feature device lock function however the master password is still stored internally within the device and may be reactivated later when a new user password is set If you execute this command when disabling the security mode feature device lock function the password sent by the host is NOT compared with either the Master Password or the User Password The device t...

Page 194: ... are rejected when the device is in frozen mode Security Set Password Security Unlock Security Disable Password Security Erase Unit Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1...

Page 195: ... of this command Table 136 Security Set Password Information Identifier Zero indicates that the device should check the supplied password against the user password stored internally One indicates that the device should check the given password against the master password stored internally Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0...

Page 196: ...curity level bits The setting of the Identifier and Security level bits interact as follows Identifier User Security level High The password supplied with the command will be saved as the new user password The security mode feature lock function will be enabled from the next power on The drive may then be unlocked by either the user password or the previously set master password Identifier Master ...

Page 197: ...remented for each password mismatch When this counter reaches zero all password protected commands are rejected until there is a hard reset or a power off Identifier A zero indicates that the device regards Password as the User Password A one indicates that the device regards Password as the Master Password The user can detect if the attempt to unlock the device has failed due to a mismatched pass...

Page 198: ... Input parameters from the device Sector Number In LBA mode this register contains the current LBA bits 0 7 L 1 Cylinder High Low In LBA mode this register contains the current LBA bits 8 15 Low and bits16 23 High L 1 H In LBA mode this register contains the current LBA bits 24 27 L 1 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Dat...

Page 199: ...r Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 V 02H Enable write cache 03H Set transfer mode based on value in sector count register 05H Enable Advanced Power Management 06H Enable Power up in Standby feature set 07H Power up in Standby feature set device spin up 09H Enable Address Offset mode 42H Enabl...

Page 200: ... Register is 05h Enable Advanced Power Management the Sector Count Register specifies the Advanced Power Management level The idle time to Low power idle mode and Low RPM standby mode vary according to the value in Sector Count register as follows When Low power idle mode is the deepest Power Saving mode DDH Disable release interrupt Write cache Enable ECC bytes 4 bytes Read look ahead Enable Reve...

Page 201: ...re initialized with a hard soft reset unless Reverting to Power on defaults is disabled and the devise receives a soft reset 12 37 3 1 Low Power Idle mode Additional electronics are powered off and the heads are unloaded on the ramp The spindle is still rotated at the full speed 12 37 3 2 The heads are unloaded on the ramp and the spindle is rotated at the 60 65 of the full speed When Feature regi...

Page 202: ...for DMA and word 104 for PIO A value of zero indicates that the host interface shall be capable of transferring data at the maximum rate allowed by the selected transfer mode The Typical PIO Mode Host Interface Sector Time includes the host s interrupt service time Sector Count Typical PIO Mode Host Interface Sector Time 7 0 LBA Low Typical PIO Mode Host Interface Sector Time 15 8 LBA Mid Typical ...

Page 203: ...ommand until the next power on or hardware reset The device returns command aborted during Set Max Locked mode or Set Max Frozen mode After a successful command completion Identify Device response words 61 60 shall reflect the maximum address set with this command If the 48 bit Address feature set is supported the value placed in Identify Device response words 103 100 shall be the same as the valu...

Page 204: ... In CHS mode this register is ignored L 0 Cylinder High Low In LBA mode this register contains LBA bits 8 15 Low 16 23 High which is to be set L 1 In CHS mode this register contains cylinder number which is to be set L 0 H In LBA mode this register contains LBA bits 24 27 which is to be set L 1 In CHS mode this register is ignored L 0 Input parameters from the device Sector Number In LBA mode this...

Page 205: ...the device accepts this command the device is in Set_Max_Unlocked state Table 142 Set Max Set Password data contents Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature 0 0 0 0 0 0 0 1 Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 ...

Page 206: ... are rejected The device remains in this state until a power cycle or the acceptance of a Set Max Unlock or Set Max Freeze Lock command Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature 0 0 0 0 0 0 1 0 Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder ...

Page 207: ...nter is initially set to 5 and is decremented for each password mismatch When this counter reaches zero all Set Max Unlock commands are rejected until a hard reset or a power off occurs If the password compare matches the device sets the Set_Max_Unlocked state and all Set Max commands are accepted Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 ...

Page 208: ...ds are rejected The following commands are disabled by Set Max Freeze Lock Set Max Address Set Max Set PASSWORD Set Max Lock Set Max Unlock Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature 0 0 0 0 0 0 1 0 Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylin...

Page 209: ... Ext command or the device is in the Set Max Locked or Set Max Frozen state the device shall return command aborted If the device in Address Offset mode receives this command with the nonvolatile option the device returns aborted error to the host The device returns the command aborted for a second non volatile Set Max Address Ext command until next power on or hardware reset Command Block Output ...

Page 210: ...by POR B 1 is not valid when the device is in Address Offset mode Sector Number Current Set Max LBA 7 0 Sector Number Previous Set Max LBA 31 24 Cylinder Low Current Set Max LBA 15 8 Cylinder Low Previous Set Max LBA 39 32 Cylinder High Current Set Max LBA 23 16 Cylinder High Previous Set Max LBA 47 40 Input parameters from the device Sector Number HOB 0 Set Max LBA 7 0 Sector Number HOB 1 Set Max...

Page 211: ...ount This indicates the block size to be used for the Read Multiple and the Write Multiple com mands Valid block sizes can be selected from 0 1 2 4 8 or 16 If 0 is specified then the Read Multiple and the Write Multiple commands are disabled Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count ...

Page 212: ...ardware reset is the only way to recover from Sleep Mode Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 0 1 1 0 Status see below Error Register Stat...

Page 213: ...he S M A R T Read Attribute Values subcommand from the host the device saves any updated Attribute Values to the Attribute Data sectors and then transfer the 512 bytes of Attribute Value information to the host Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature V V V V V V V V Error see below Sector Count V V V V V V V V...

Page 214: ...tosave subcommand will not change the current Autosave status However the device will respond with the error code specified in Table 161 S M A R T Error Codes on page 212 The S M A R T Disable Operations subcommand disables the Autosave feature along with the S M A R T opera tions of the device Upon the receipt of the subcommand from the host the device asserts BSY enables or disables the Autosave...

Page 215: ...SMART Read Log Sector command the device shall return command aborted 12 42 1 7 S M A R T Write Log Sector subcommand D6h This command writes 512 bytes of data to the specified log sector The 512 bytes of data are transferred at a command and the Sector Count value shall be set to one The Sector Number shall be set to specify the log sector address as shown above If a Read Only log sector is speci...

Page 216: ...ce saves any updated Pre failure type Attribute Values to the reserved sector and compares the updated Attribute Values to the Attribute Thresholds If the device does not detect a Threshold Exceeded Condition the device loads 4Fh into the Cylinder Low register and C2h into the Cylinder High register If the device detects a Threshold Exceeded Condition the device loads F4h into the Cylinder Low reg...

Page 217: ...cture The following defines the 12 bytes that make up the information for each Attribute entry in the Device Attribute Data Structure Table 151 Individual Attribute Data Structure Description Byte Offset Value Data Structure Revision Number 2 00h 0010h 1st Device Attribute 12 02h 30th Device Attribute 12 15Eh Off line data collection status 1 16Ah Self test execution status 1 16Bh Total time in se...

Page 218: ... Off line testing 1 The attribute value is updated during On line testing or during both On line and Off line testing 2 5 Vendor specific 6 15 Reserved 0 Normalized values The device performs conversion of the raw Attribute Values to transform them into normal ized values which the host can then compare with the Threshold values A Threshold is the excursion limit for a normalized Attribute Value I...

Page 219: ... Bit Definition 0 Execute Off line Immediate implemented bit 0 S M A R T Execute Off line Immediate subcommand is not implemented 1 S M A R T Execute Off line Immediate subcommand is implemented 1 Enable disable Automatic Off line implemented bit 0 S M A R T Enable disable Automatic Off line subcommand is not implemented 1 S M A R T Enable disable Automatic Off line subcommand is implemented Bit D...

Page 220: ...BLE ATTRIBUTE AUTOSAVE command Bit Definition 0 Pre power mode attribute saving capability If bit 1 the device will save its Attribute Values prior to going into a power saving mode Standby or Sleep mode 1 Attribute Autosave capability If bit 1 the device supports the S M A R T ENABLE DISABLE ATTRIBUTE AUTOSAVE command 2 15 Reserved 0 12 42 2 8 Error logging capability Bit Definition 7 1 Reserved ...

Page 221: ... the Individual Threshold Data Structure are in the same order and correspond to the entries in the Individual Attribute Data Structure 12 42 3 3 Attribute ID Numbers Attribute ID Numbers supported by the device are the same as Attribute Values Data Structures 12 42 3 4 Attribute Threshold These values are preset at the factory and are not meant to be changeable 12 42 3 5 Data Structure Checksum T...

Page 222: ...ry error log sector 12 42 5 1 S M A R T error log version This value is set to 01h 12 42 5 2 Error log pointer This points to the most recent error log data structure Only values 1 through 5 are valid 12 42 5 3 Device error count This field contains the total number of errors The value will not roll over Description Byte Offset S M A R T Logging Version 2 00h Number of sectors in the log at log ad...

Page 223: ...12 0Ch 3rd command data structure 12 18h 4th command data structure 12 24h 5th command data structure 12 30h Error data structure 30 3Ch 90 Description Byte Offset Device Control register 1 00h Features register 1 01h Sector count register 1 02h Sector number register 1 03h Cylinder Low register 1 04h Cylinder High register 1 05h Device Head register 1 06h Command register 1 07h Time stamp ms from...

Page 224: ...ta structure is capable to contain up to 21 descriptors After 21 descriptors has been recorded the oldest descriptor will be overwritten with the new descriptor The self test log index points to the most recent descriptor When there is no descriptor the value is 0 When there are one or more descriptors the value is 1 through 21 Value State x0h Unknown x1h Sleep x2h Standby x3h Active Idle x4h S M ...

Page 225: ...00h R W Starting LBA for test span 1 8 02h R W Ending LBA for test span 1 8 0Ah R W Starting LBA for test span 2 8 12h R W Ending LBA for test span 2 8 1Ah R W Starting LBA for test span 3 8 22h R W Ending LBA for test span 3 8 2Ah R W Starting LBA for test span 4 8 32h R W Ending LBA for test span 4 8 3Ah R W Starting LBA for test span 5 8 42h R W Ending LBA for test span 5 8 4Ah R W Reserved 256...

Page 226: ...eing loaded into the Cylinder High and Cylin der Low registers 51h 04h A S M A R T FUNCTION SET command was received by the device with a subcommand value in the Features Register that is either invalid or not supported by this device 51h 04h A S M A R T FUNCTION SET command subcommand other than S M A R T ENABLE OPERATIONS was received by the device while the device was in a S M A R T Disabled st...

Page 227: ...the automatic power down sequence is enabled The time out interval is shown below When the automatic power down sequence is enabled the device will enter the Standby mode automatically if the time out interval expires with no device access from the host The time out interval will be reinitialized if there is a drive access before the time out interval expires Command Block Output Registers Command...

Page 228: ...will be a delay while waiting for the spindle to reach operating speed The Standby Immediate command will not affect the auto power down time out parameter Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylin...

Page 229: ...hat sequential Write Buffer and Read Buffer commands access the same 512 byte within the buffer Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 1 0 0...

Page 230: ... the first sector to be transferred L 0 In LBA mode this reg ister contains the LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This indicates the retry bit This bit is ignored Input parameters from the device Sector Count This indicates the number of requested sectors n...

Page 231: ...is indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 232: ...rred low order bits 15 8 If zero is specified in the Sector Count register 65 536 sectors will be transferred Sector Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current ...

Page 233: ...he first unrecoverable error Sector Number HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unre...

Page 234: ...t The first sector of the log to be written low order bits 7 0 Cylinder Low Previous The first sector of the log to be written high order bits 15 8 If the feature set associated with the log specified in the Sector Number register is not supported or enabled or if the values in the Sector Count Sector Number or Cylinder Low registers are invalid the device shall return com mand aborted If the host...

Page 235: ...High Low This indicates the cylinder number of the sector to be transferred L 0 In LBA mode this register contains the LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R The retry bit This bit is ignored Input parameters from the device Sector Count This indicates the number of r...

Page 236: ...r of the sector to be transferred L 0 In LBA mode this register contains current the LBA bits 24 27 L 1 The drive internally uses 52 bytes of ECC on all data read or writes The 4 byte mode of operation is provided by means of an emulation technique As a consequence of this emulation it is recommended that 52 byte ECC mode be used for all tests to confirm the operation of the ECC hardware of the dr...

Page 237: ...is register contains the LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred The Sector Count will be zero unless an unrecoverable error occurs Sector Number This indic...

Page 238: ...is indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains current the LBA bits 24 27 L 1 ...

Page 239: ...Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error See below Previous Sector Count Current V V V ...

Page 240: ...tor Number HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 241: ...his indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This indicates the retry bit this bit is ignored Input parameters from the device Sector Count This indicates the number of requested sectors not transferred This will be zero unless an unrecoverable error occurs Sector Number This indicates the sector number of the l...

Page 242: ... This indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 243: ...Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error See below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V V HOB 1 Sector Nu...

Page 244: ...tor Number HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 245: ...bit in the error log to one In all cases the device shall attempt to transfer the amount of data requested within the Command Completion Time Limit event if some data transferred is in error Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current V V V V V V V Error See below Previous V V V...

Page 246: ... operate according to the Stream ID set by the Write Stream command Feature Previous CCTL 7 0 The time allowed for the current command s completion is calculated as follows Command Completion Time Limit content of the Feature register Previous Identify Device words 99 98 useconds If the value is zero the device shall use the Default CCTL supplied with a previous Configure Stream command for this S...

Page 247: ... of consecutive sectors that may contain errors If the WC bit is set to one when the command is issued and an ICRC UNC IDNF ABRT or CCTO error occurs the SE bit shall be set to one the ERR bit shall be cleared to zero and the bits that would normally be set in the Error register shall be set in the error log DWE Status bit 4 DWE Deferred Write Error shall be set to one if an error was detected in ...

Page 248: ...sfer the amount of data requested within the Command Completion Time Limit event if some data transferred is in error Output Parameters To The Device Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current V V V V V V V Error See below Previous V V V V V V V V Sector Count Current V V V V V...

Page 249: ...et to one HSE bit4 HSE Handle Stream Error specifies that this command starts at the LBA of the last reported error for this stream so the device may attempt to continue its corresponding error recovery sequence where it left off earlier Stream ID bit 0 2 Stream ID specifies the stream being written The device shall operate according to the Stream ID set by the Write Stream command Feature Previou...

Page 250: ...has occurred SE Status bit 5 SE Stream Error shall be set to one if an error has occurred during the execution of the command and the WC bit is set to one In this case the LBA returned in the Sector Number registers shall be the address of the first sector in error and the Sector Count registers shall contain the number of consecutive sectors that may contain errors If the WC bit is set to one whe...

Page 251: ...0 and RDY 1 31 sec Hard Reset Device Busy After Hard Reset Bus RESET Signal Asserted Status Register BSY 1 400 ns Device Ready After Hard Reset Bus RESET Signal Asserted Status Register BSY 0 and RDY 1 31 sec Data In Com mand Device Busy After Com mand Code Out OUT To Command Reg ister Status Register BSY 1 400 ns Interrupt DRQ For Data Transfer In Status Register BSY 1 Status Register BSY 0 and D...

Page 252: ...ector 24 Attribute thresholds 81 Attribute values 81 Attributes 81 Auto Reassign 92 Automatic Acoustic Management 94 B BSMI mark 63 C Cable noise interference 53 Cabling 43 Capacity formatted 11 Caution 3 CE mark 63 Check Power Mode E5h 98h 111 Command descriptions 107 Command overhead 14 Command protocol 101 Command Register 68 Command table 87 Configure Stream 51h 112 Connector location 23 45 Co...

Page 253: ...iagnostic and Reset considerations 77 DMA commands 105 DMA Data Transfer commands 105 Download Microcode 92h 118 Drive Address Register 70 Drive characteristics 11 Drive format 12 Drive ready time 16 E Electrical Interface 23 Electrical interface 23 Electromagnetic compatibility 63 Environment 50 62 Error log 82 Error Register 71 Error reporting 212 Execute Device Diagnostic 90h 119 Extended Self ...

Page 254: ...inating Write DMA 42 Humidity 50 I Identification labels 61 Identify Device ECh 124 Idle E3h 97h 135 Idle Immediate E1h 95h 136 Initialize Device Parameters 91h 137 Initiating Write DMA 39 Input voltage 51 Interface capability for power modes 80 Interface logic signal levels 29 J Jumper pin assignment 46 Jumper pin identification 45 Jumper pin location 45 Jumper positions 46 Jumper Settings 45 Jum...

Page 255: ...Off line read scanning 81 Operating modes 19 description 17 Operating shock 59 Operating vibration 58 Operation example 84 P Packaging 63 Passwords 84 Performance characteristics 13 Physical dimensions 54 PIO Data In commands 101 PIO Data Out Commands 102 PIO timings 32 Power consumption effiency 52 Power management commands 79 Power management features 79 Power mode 79 Power supply current 51 Pow...

Page 256: ...99 S M A R T Function Set 199 S M A R T Log Directory 208 Safety 62 Secondary circuit protection 62 Sector Addressing 78 Sector Addressing Mode 78 Sector Count Register 71 Sector Number Register 72 Security 83 Security Disable Password F3h 177 Security Disable Password F6h 176 Security Mode Feature Set 83 Seek 184 Seek 7xh 184 Seek overlap 90 Seek time average 15 full stroke 15 single track 16 Sel...

Page 257: ... stop cycles 53 Status Register 72 Streaming commands 98 Streaming feature Set 97 Streaming Logs 99 Streaming Performance log 151 T Temperature 50 Terminology 65 Threshold exceeded condition 81 Throughput 18 Time out values 237 Timings multi word DMA 34 reset 31 Ultra DMA 35 U UL approval 62 Urgent bit 98 V Vibration 58 W Weight 54 World Wide Name Assignment 12 Write Buffer 215 Write cache 91 Writ...

Page 258: ...tered trade marks of their respective companies References in this publication to Hitachi Global Storage Technologies products programs or services do not imply that Hitachi Global Storage Technologies intends to make these available in all countries in which Hitachi Global Storage Technologies operates Product information is provided for information pur poses only and does not constitute a warran...

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