3.5 Communication Methods
26
Standard Event Status Register (SESR) ____________________________
A standard event status register is an 8-bit register.
If any bit in the Standard Event Status Register is set to 1 (after masking by the
Standard Event Status Enable Register), bit 5 (ESB) of the Status Byte Register
is set to 1.
See:
"Standard Event Status Enable Register (SESER)" (p.27)
The standard event status register is cleared at the following times:
• When a "
*
CLS
" command is executed
• When a "
ERR?
" command is executed
• When the device is powered on
Event Registers
Bit 7
PON
Power-On Flag
Set to 1 when the power is turned on, or upon recovery from an outage.
Bit 6
URQ
User Request
unused
Bit 5
CME
Command error (The command to the message terminator is ignored.)
This bit is set to 1 when a received command contains a syntactic or semantic
error:
•
Program header error
•
Incorrect number of data parameters
•
Invalid parameter format
•
Received a command not supported by the device
Bit 4
EXE
Execution Error
This bit is set to 1 when a received command cannot be executed for some
reason.
•
The specified data value is outside of the set range
•
The specified setting data cannot be set
•
Execution is prevented by some other operation being performed
Bit 3
DDE
Device-Dependent Error
This bit is set to 1 when a command cannot be executed due to some reason
other than a command error, a query error or an execution error.
•
When the command cannot be executed because there is an internal
anomaly
Bit 2
QYE
Query Error (the output queue is cleared)
This bit is set to 1 when a query error is detected by the controller of the output
queue.
•
When an attempt has been made to read an empty output queue (GP-IB
only)
•
When the data overflows the output queue
•
When data in the output queue has been lost
Bit 1
RQC
Request Control
unused
Bit 0
OPC
Operation Complete
This bit is set to 1 in response to an "
*
OPC
"
command.
•
It indicates the completion of operations of all messages up to the "
*
OPC
"
command
