Descriptions and Drawings
15/60
NXHX 51-ETM | Development Board
DOC120606HW05EN | Revision 5 | English | 2013-10 | Released | Public
© Hilscher, 2012 - 2013
Use the following setting, if the
NXHX-IO Board
is connected:
X10 DPM
Description
DPM_DIRQ#/PIO 47 is connected to X3 pin 11
Table 15: X10 - Setting for NXHX-IO Board at Host Interface X3
Use the following setting, if the
NXHX-SDR Board
is connected:
X10 SDRAM
Description
SDRAM_CLK is connected to X3 pin 4
SDRAM RAS# is connected to X3 pin 7
Table 16: X10 - Setting for NXHX-SDR Board at Host Interface X3
Use the following setting, if the
NXHX-PHY Board
is connected:
X10 PHY
Description
DPM_DIRQ# is connected to X3 pin 11
DPM_SIRQ# is connected to X3 pin 4
Table 17: X10 - Setting for NXHX-PHY Board at Host Interface X3
Use the following setting, if the
NXHX-PHYSDR Board
is connected:
X10 PHYSDR
Description
SDRAM_CLK is connected to X3 pin 4
MII_RXD0 to X3 pin 11
SDRAM RAS# is connected to X3 pin 7
Table 18: X10 - Setting for NXHX-PHYSDR Board at Host Interface X3
